rseq-or1k.h

  1/* SPDX-License-Identifier: LGPL-2.1 OR MIT */
  2
  3/*
  4 * Select the instruction "l.nop 0x35" as the RSEQ_SIG.
  5 */
  6#define RSEQ_SIG   0x15000035
  7
  8#define rseq_smp_mb()	__asm__ __volatile__ ("l.msync" ::: "memory")
  9#define rseq_smp_rmb()	rseq_smp_mb()
 10#define rseq_smp_wmb()	rseq_smp_mb()
 11#define RSEQ_ASM_TMP_REG_1	"r31"
 12#define RSEQ_ASM_TMP_REG_2	"r29"
 13#define RSEQ_ASM_TMP_REG_3	"r27"
 14#define RSEQ_ASM_TMP_REG_4	"r25"
 15
 16#define rseq_smp_load_acquire(p)					\
 17__extension__ ({							\
 18	rseq_unqual_scalar_typeof(*(p)) ____p1 = RSEQ_READ_ONCE(*(p));	\
 19	rseq_smp_mb();							\
 20	____p1;								\
 21})
 22
 23#define rseq_smp_acquire__after_ctrl_dep()	rseq_smp_rmb()
 24
 25#define rseq_smp_store_release(p, v)					\
 26do {									\
 27	rseq_smp_mb();							\
 28	RSEQ_WRITE_ONCE(*(p), v);					\
 29} while (0)
 30
 31#define __RSEQ_ASM_DEFINE_TABLE(label, version, flags, start_ip,	\
 32				post_commit_offset, abort_ip)		\
 33	".pushsection	__rseq_cs, \"aw\"\n"				\
 34	".balign	32\n"						\
 35	__rseq_str(label) ":\n"						\
 36	".long " __rseq_str(version) ", " __rseq_str(flags) "\n"	\
 37	".long 0x0, " __rseq_str(start_ip) ", "				\
 38		"0x0, " __rseq_str(post_commit_offset) ", "		\
 39		"0x0, " __rseq_str(abort_ip) "\n"			\
 40	".popsection\n\t"						\
 41	".pushsection __rseq_cs_ptr_array, \"aw\"\n"			\
 42	".long 0x0, " __rseq_str(label) "b\n"				\
 43	".popsection\n"
 44
 45#define RSEQ_ASM_DEFINE_TABLE(label, start_ip, post_commit_ip, abort_ip) \
 46	__RSEQ_ASM_DEFINE_TABLE(label, 0x0, 0x0, start_ip,		 \
 47				((post_commit_ip) - (start_ip)), abort_ip)
 48
 49/*
 50 * Exit points of a rseq critical section consist of all instructions outside
 51 * of the critical section where a critical section can either branch to or
 52 * reach through the normal course of its execution. The abort IP and the
 53 * post-commit IP are already part of the __rseq_cs section and should not be
 54 * explicitly defined as additional exit points. Knowing all exit points is
 55 * useful to assist debuggers stepping over the critical section.
 56 */
 57#define RSEQ_ASM_DEFINE_EXIT_POINT(start_ip, exit_ip)			\
 58	".pushsection __rseq_exit_point_array, \"aw\"\n"		\
 59	".long 0x0, " __rseq_str(start_ip) ", 0x0, " __rseq_str(exit_ip) "\n"	\
 60	".popsection\n"
 61
 62#define RSEQ_ASM_STORE_RSEQ_CS(label, cs_label, rseq_cs)		\
 63	RSEQ_INJECT_ASM(1)						\
 64	"l.movhi " RSEQ_ASM_TMP_REG_1 ", hi(" __rseq_str(cs_label) ")\n"\
 65	"l.ori   " RSEQ_ASM_TMP_REG_1 ", " RSEQ_ASM_TMP_REG_1		\
 66		", lo(" __rseq_str(cs_label) ")\n"\
 67	"l.sw  %[" __rseq_str(rseq_cs) "], " RSEQ_ASM_TMP_REG_1 "\n"	\
 68	__rseq_str(label) ":\n"
 69
 70#define RSEQ_ASM_DEFINE_ABORT(label, abort_label)			\
 71	"l.j 222f\n"							\
 72	" l.nop\n"							\
 73	".balign	4\n"						\
 74	".long "	__rseq_str(RSEQ_SIG) "\n"			\
 75	__rseq_str(label) ":\n"						\
 76	"l.j %l[" __rseq_str(abort_label) "]\n"				\
 77	" l.nop\n"							\
 78	"222:\n"
 79
 80#define RSEQ_ASM_OP_STORE(var, value)					\
 81	"l.sw %[" __rseq_str(var) "], %[" __rseq_str(value) "]\n"
 82
 83#define RSEQ_ASM_OP_CMPEQ(var, expect, label)				\
 84	"l.lwz  " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(var) "]\n"	\
 85	"l.sfne " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(expect) "]\n"	\
 86	"l.bf   " __rseq_str(label) "\n"				\
 87	" l.nop\n"
 88
 89#define RSEQ_ASM_OP_CMPNE(var, expect, label)				\
 90	"l.lwz  " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(var) "]\n"	\
 91	"l.sfeq " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(expect) "]\n"	\
 92	"l.bf   " __rseq_str(label) "\n"				\
 93	" l.nop\n"
 94
 95#define RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, label)		\
 96	RSEQ_INJECT_ASM(2)						\
 97	RSEQ_ASM_OP_CMPEQ(current_cpu_id, cpu_id, label)
 98
 99#define RSEQ_ASM_OP_R_LOAD(var)						\
100	"l.lwz " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(var) "]\n"
101
102#define RSEQ_ASM_OP_R_STORE(var)					\
103	"l.sw %[" __rseq_str(var) "], " RSEQ_ASM_TMP_REG_1 "\n"
104
105#define RSEQ_ASM_OP_R_LOAD_OFF(offset)					\
106	"l.lwz " RSEQ_ASM_TMP_REG_1 ", "				\
107		"%[" __rseq_str(offset) "](" RSEQ_ASM_TMP_REG_1 ")\n"
108
109#define RSEQ_ASM_OP_R_ADD(count)					\
110	"l.add " RSEQ_ASM_TMP_REG_1 ", " RSEQ_ASM_TMP_REG_1		\
111		", %[" __rseq_str(count) "]\n"
112
113#define RSEQ_ASM_OP_FINAL_STORE(var, value, post_commit_label)		\
114	RSEQ_ASM_OP_STORE(var, value)					\
115	__rseq_str(post_commit_label) ":\n"
116
117#define RSEQ_ASM_OP_FINAL_STORE_RELEASE(var, value, post_commit_label)	\
118	"l.msync\n"							\
119	RSEQ_ASM_OP_STORE(var, value)					\
120	__rseq_str(post_commit_label) ":\n"
121
122#define RSEQ_ASM_OP_R_FINAL_STORE(var, post_commit_label)		\
123	"l.sw %[" __rseq_str(var) "], " RSEQ_ASM_TMP_REG_1 "\n"		\
124	__rseq_str(post_commit_label) ":\n"
125
126#define RSEQ_ASM_OP_R_BAD_MEMCPY(dst, src, len)				\
127	"l.sfeq	%[" __rseq_str(len) "], r0\n"				\
128	"l.bf 333f\n"							\
129	" l.nop\n"							\
130	"l.ori  " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(len) "], 0\n"	\
131	"l.ori  " RSEQ_ASM_TMP_REG_2 ", %[" __rseq_str(src) "], 0\n"	\
132	"l.ori  " RSEQ_ASM_TMP_REG_3 ", %[" __rseq_str(dst) "], 0\n"	\
133	"222:\n"							\
134	"l.lbz  " RSEQ_ASM_TMP_REG_4 ", 0(" RSEQ_ASM_TMP_REG_2 ")\n"	\
135	"l.sb   0(" RSEQ_ASM_TMP_REG_3 "), " RSEQ_ASM_TMP_REG_4 "\n"	\
136	"l.addi " RSEQ_ASM_TMP_REG_1 ", " RSEQ_ASM_TMP_REG_1 ", -1\n"	\
137	"l.addi " RSEQ_ASM_TMP_REG_2 ", " RSEQ_ASM_TMP_REG_2 ", 1\n"	\
138	"l.addi " RSEQ_ASM_TMP_REG_3 ", " RSEQ_ASM_TMP_REG_3 ", 1\n"	\
139	"l.sfne " RSEQ_ASM_TMP_REG_1 ", r0\n"				\
140	"l.bf 222b\n"							\
141	" l.nop\n"							\
142	"333:\n"
143
144#define RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, inc, post_commit_label)	\
145	"l.ori  " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(ptr) "], 0\n"	\
146	RSEQ_ASM_OP_R_ADD(off)						\
147	"l.lwz  " RSEQ_ASM_TMP_REG_1 ", 0(" RSEQ_ASM_TMP_REG_1 ")\n"	\
148	RSEQ_ASM_OP_R_ADD(inc)						\
149	__rseq_str(post_commit_label) ":\n"
150
151/* Per-cpu-id indexing. */
152
153#define RSEQ_TEMPLATE_CPU_ID
154#define RSEQ_TEMPLATE_MO_RELAXED
155#include "rseq-or1k-bits.h"
156#undef RSEQ_TEMPLATE_MO_RELAXED
157
158#define RSEQ_TEMPLATE_MO_RELEASE
159#include "rseq-or1k-bits.h"
160#undef RSEQ_TEMPLATE_MO_RELEASE
161#undef RSEQ_TEMPLATE_CPU_ID
162
163/* Per-mm-cid indexing. */
164
165#define RSEQ_TEMPLATE_MM_CID
166#define RSEQ_TEMPLATE_MO_RELAXED
167#include "rseq-or1k-bits.h"
168#undef RSEQ_TEMPLATE_MO_RELAXED
169
170#define RSEQ_TEMPLATE_MO_RELEASE
171#include "rseq-or1k-bits.h"
172#undef RSEQ_TEMPLATE_MO_RELEASE
173#undef RSEQ_TEMPLATE_MM_CID
174
175/* APIs which are not based on cpu ids. */
176
177#define RSEQ_TEMPLATE_CPU_ID_NONE
178#define RSEQ_TEMPLATE_MO_RELAXED
179#include "rseq-or1k-bits.h"
180#undef RSEQ_TEMPLATE_MO_RELAXED
181#undef RSEQ_TEMPLATE_CPU_ID_NONE