get-reg-list.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Check for KVM_GET_REG_LIST regressions.
   4 *
   5 * Copyright (c) 2023 Intel Corporation
   6 *
   7 */
   8#include <stdio.h>
   9#include "kvm_util.h"
  10#include "test_util.h"
  11#include "processor.h"
  12
  13#define REG_MASK (KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK)
  14
  15enum {
  16	VCPU_FEATURE_ISA_EXT = 0,
  17	VCPU_FEATURE_SBI_EXT,
  18};
  19
  20enum {
  21	KVM_RISC_V_REG_OFFSET_VSTART = 0,
  22	KVM_RISC_V_REG_OFFSET_VL,
  23	KVM_RISC_V_REG_OFFSET_VTYPE,
  24	KVM_RISC_V_REG_OFFSET_VCSR,
  25	KVM_RISC_V_REG_OFFSET_VLENB,
  26	KVM_RISC_V_REG_OFFSET_MAX,
  27};
  28
  29static bool isa_ext_cant_disable[KVM_RISCV_ISA_EXT_MAX];
  30
  31bool filter_reg(__u64 reg)
  32{
  33	switch (reg & ~REG_MASK) {
  34	/*
  35	 * Same set of ISA_EXT registers are not present on all host because
  36	 * ISA_EXT registers are visible to the KVM user space based on the
  37	 * ISA extensions available on the host. Also, disabling an ISA
  38	 * extension using corresponding ISA_EXT register does not affect
  39	 * the visibility of the ISA_EXT register itself.
  40	 *
  41	 * Based on above, we should filter-out all ISA_EXT registers.
  42	 *
  43	 * Note: The below list is alphabetically sorted.
  44	 */
  45	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_A:
  46	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_C:
  47	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_D:
  48	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_F:
  49	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_H:
  50	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_I:
  51	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_M:
  52	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_V:
  53	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SMNPM:
  54	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SMSTATEEN:
  55	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSAIA:
  56	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSCOFPMF:
  57	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSNPM:
  58	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSTC:
  59	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVADE:
  60	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVADU:
  61	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVINVAL:
  62	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVNAPOT:
  63	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVPBMT:
  64	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVVPTC:
  65	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZAAMO:
  66	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZABHA:
  67	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZACAS:
  68	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZALRSC:
  69	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZAWRS:
  70	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBA:
  71	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBB:
  72	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBC:
  73	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKB:
  74	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKC:
  75	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKX:
  76	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBS:
  77	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCA:
  78	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCB:
  79	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCD:
  80	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCF:
  81	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCMOP:
  82	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFA:
  83	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFBFMIN:
  84	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFH:
  85	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFHMIN:
  86	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM:
  87	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOP:
  88	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ:
  89	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICCRSE:
  90	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICNTR:
  91	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICOND:
  92	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICSR:
  93	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIFENCEI:
  94	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHINTNTL:
  95	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHINTPAUSE:
  96	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHPM:
  97	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIMOP:
  98	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKND:
  99	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKNE:
 100	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKNH:
 101	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKR:
 102	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKSED:
 103	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKSH:
 104	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKT:
 105	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZTSO:
 106	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVBB:
 107	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVBC:
 108	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFBFMIN:
 109	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFBFWMA:
 110	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFH:
 111	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFHMIN:
 112	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKB:
 113	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKG:
 114	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNED:
 115	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNHA:
 116	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNHB:
 117	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKSED:
 118	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKSH:
 119	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKT:
 120	/*
 121	 * Like ISA_EXT registers, SBI_EXT registers are only visible when the
 122	 * host supports them and disabling them does not affect the visibility
 123	 * of the SBI_EXT register itself.
 124	 */
 125	case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_V01:
 126	case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_TIME:
 127	case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_IPI:
 128	case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_RFENCE:
 129	case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_SRST:
 130	case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_HSM:
 131	case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_PMU:
 132	case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_DBCN:
 133	case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_SUSP:
 134	case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_STA:
 135	case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_FWFT:
 136	case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_MPXY:
 137	case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_EXPERIMENTAL:
 138	case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_VENDOR:
 139		return true;
 140	/* AIA registers are always available when Ssaia can't be disabled */
 141	case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect):
 142	case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1):
 143	case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2):
 144	case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(sieh):
 145	case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siph):
 146	case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1h):
 147	case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2h):
 148		return isa_ext_cant_disable[KVM_RISCV_ISA_EXT_SSAIA];
 149	default:
 150		break;
 151	}
 152
 153	return false;
 154}
 155
 156bool check_reject_set(int err)
 157{
 158	return err == EINVAL;
 159}
 160
 161static int override_vector_reg_size(struct kvm_vcpu *vcpu, struct vcpu_reg_sublist *s,
 162				    uint64_t feature)
 163{
 164	unsigned long vlenb_reg = 0;
 165	int rc;
 166	u64 reg, size;
 167
 168	/* Enable V extension so that we can get the vlenb register */
 169	rc = __vcpu_set_reg(vcpu, feature, 1);
 170	if (rc)
 171		return rc;
 172
 173	vlenb_reg = vcpu_get_reg(vcpu, s->regs[KVM_RISC_V_REG_OFFSET_VLENB]);
 174	if (!vlenb_reg) {
 175		TEST_FAIL("Can't compute vector register size from zero vlenb\n");
 176		return -EPERM;
 177	}
 178
 179	size = __builtin_ctzl(vlenb_reg);
 180	size <<= KVM_REG_SIZE_SHIFT;
 181
 182	for (int i = 0; i < 32; i++) {
 183		reg = KVM_REG_RISCV | KVM_REG_RISCV_VECTOR | size | KVM_REG_RISCV_VECTOR_REG(i);
 184		s->regs[KVM_RISC_V_REG_OFFSET_MAX + i] = reg;
 185	}
 186
 187	/* We should assert if disabling failed here while enabling succeeded before */
 188	vcpu_set_reg(vcpu, feature, 0);
 189
 190	return 0;
 191}
 192
 193void finalize_vcpu(struct kvm_vcpu *vcpu, struct vcpu_reg_list *c)
 194{
 195	unsigned long isa_ext_state[KVM_RISCV_ISA_EXT_MAX] = { 0 };
 196	struct vcpu_reg_sublist *s;
 197	uint64_t feature;
 198	int rc;
 199
 200	for (int i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++)
 201		__vcpu_get_reg(vcpu, RISCV_ISA_EXT_REG(i), &isa_ext_state[i]);
 202
 203	/*
 204	 * Disable all extensions which were enabled by default
 205	 * if they were available in the risc-v host.
 206	 */
 207	for (int i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++) {
 208		rc = __vcpu_set_reg(vcpu, RISCV_ISA_EXT_REG(i), 0);
 209		if (rc && isa_ext_state[i])
 210			isa_ext_cant_disable[i] = true;
 211	}
 212
 213	for (int i = 0; i < KVM_RISCV_SBI_EXT_MAX; i++) {
 214		rc = __vcpu_set_reg(vcpu, RISCV_SBI_EXT_REG(i), 0);
 215		TEST_ASSERT(!rc || (rc == -1 && errno == ENOENT), "Unexpected error");
 216	}
 217
 218	for_each_sublist(c, s) {
 219		if (!s->feature)
 220			continue;
 221
 222		if (s->feature == KVM_RISCV_ISA_EXT_V) {
 223			feature = RISCV_ISA_EXT_REG(s->feature);
 224			rc = override_vector_reg_size(vcpu, s, feature);
 225			if (rc)
 226				goto skip;
 227		}
 228
 229		switch (s->feature_type) {
 230		case VCPU_FEATURE_ISA_EXT:
 231			feature = RISCV_ISA_EXT_REG(s->feature);
 232			break;
 233		case VCPU_FEATURE_SBI_EXT:
 234			feature = RISCV_SBI_EXT_REG(s->feature);
 235			break;
 236		default:
 237			TEST_FAIL("Unknown feature type");
 238		}
 239
 240		/* Try to enable the desired extension */
 241		__vcpu_set_reg(vcpu, feature, 1);
 242
 243skip:
 244		/* Double check whether the desired extension was enabled */
 245		__TEST_REQUIRE(__vcpu_has_ext(vcpu, feature),
 246			       "%s not available, skipping tests", s->name);
 247	}
 248}
 249
 250static const char *config_id_to_str(const char *prefix, __u64 id)
 251{
 252	/* reg_off is the offset into struct kvm_riscv_config */
 253	__u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CONFIG);
 254
 255	assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG);
 256
 257	switch (reg_off) {
 258	case KVM_REG_RISCV_CONFIG_REG(isa):
 259		return "KVM_REG_RISCV_CONFIG_REG(isa)";
 260	case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
 261		return "KVM_REG_RISCV_CONFIG_REG(zicbom_block_size)";
 262	case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size):
 263		return "KVM_REG_RISCV_CONFIG_REG(zicboz_block_size)";
 264	case KVM_REG_RISCV_CONFIG_REG(zicbop_block_size):
 265		return "KVM_REG_RISCV_CONFIG_REG(zicbop_block_size)";
 266	case KVM_REG_RISCV_CONFIG_REG(mvendorid):
 267		return "KVM_REG_RISCV_CONFIG_REG(mvendorid)";
 268	case KVM_REG_RISCV_CONFIG_REG(marchid):
 269		return "KVM_REG_RISCV_CONFIG_REG(marchid)";
 270	case KVM_REG_RISCV_CONFIG_REG(mimpid):
 271		return "KVM_REG_RISCV_CONFIG_REG(mimpid)";
 272	case KVM_REG_RISCV_CONFIG_REG(satp_mode):
 273		return "KVM_REG_RISCV_CONFIG_REG(satp_mode)";
 274	}
 275
 276	return strdup_printf("%lld /* UNKNOWN */", reg_off);
 277}
 278
 279static const char *core_id_to_str(const char *prefix, __u64 id)
 280{
 281	/* reg_off is the offset into struct kvm_riscv_core */
 282	__u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CORE);
 283
 284	assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE);
 285
 286	switch (reg_off) {
 287	case KVM_REG_RISCV_CORE_REG(regs.pc):
 288		return "KVM_REG_RISCV_CORE_REG(regs.pc)";
 289	case KVM_REG_RISCV_CORE_REG(regs.ra):
 290		return "KVM_REG_RISCV_CORE_REG(regs.ra)";
 291	case KVM_REG_RISCV_CORE_REG(regs.sp):
 292		return "KVM_REG_RISCV_CORE_REG(regs.sp)";
 293	case KVM_REG_RISCV_CORE_REG(regs.gp):
 294		return "KVM_REG_RISCV_CORE_REG(regs.gp)";
 295	case KVM_REG_RISCV_CORE_REG(regs.tp):
 296		return "KVM_REG_RISCV_CORE_REG(regs.tp)";
 297	case KVM_REG_RISCV_CORE_REG(regs.t0) ... KVM_REG_RISCV_CORE_REG(regs.t2):
 298		return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.t%lld)",
 299			   reg_off - KVM_REG_RISCV_CORE_REG(regs.t0));
 300	case KVM_REG_RISCV_CORE_REG(regs.s0) ... KVM_REG_RISCV_CORE_REG(regs.s1):
 301		return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.s%lld)",
 302			   reg_off - KVM_REG_RISCV_CORE_REG(regs.s0));
 303	case KVM_REG_RISCV_CORE_REG(regs.a0) ... KVM_REG_RISCV_CORE_REG(regs.a7):
 304		return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.a%lld)",
 305			   reg_off - KVM_REG_RISCV_CORE_REG(regs.a0));
 306	case KVM_REG_RISCV_CORE_REG(regs.s2) ... KVM_REG_RISCV_CORE_REG(regs.s11):
 307		return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.s%lld)",
 308			   reg_off - KVM_REG_RISCV_CORE_REG(regs.s2) + 2);
 309	case KVM_REG_RISCV_CORE_REG(regs.t3) ... KVM_REG_RISCV_CORE_REG(regs.t6):
 310		return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.t%lld)",
 311			   reg_off - KVM_REG_RISCV_CORE_REG(regs.t3) + 3);
 312	case KVM_REG_RISCV_CORE_REG(mode):
 313		return "KVM_REG_RISCV_CORE_REG(mode)";
 314	}
 315
 316	return strdup_printf("%lld /* UNKNOWN */", reg_off);
 317}
 318
 319#define RISCV_CSR_GENERAL(csr) \
 320	"KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(" #csr ")"
 321#define RISCV_CSR_AIA(csr) \
 322	"KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_REG(" #csr ")"
 323#define RISCV_CSR_SMSTATEEN(csr) \
 324	"KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_REG(" #csr ")"
 325
 326static const char *general_csr_id_to_str(__u64 reg_off)
 327{
 328	/* reg_off is the offset into struct kvm_riscv_csr */
 329	switch (reg_off) {
 330	case KVM_REG_RISCV_CSR_REG(sstatus):
 331		return RISCV_CSR_GENERAL(sstatus);
 332	case KVM_REG_RISCV_CSR_REG(sie):
 333		return RISCV_CSR_GENERAL(sie);
 334	case KVM_REG_RISCV_CSR_REG(stvec):
 335		return RISCV_CSR_GENERAL(stvec);
 336	case KVM_REG_RISCV_CSR_REG(sscratch):
 337		return RISCV_CSR_GENERAL(sscratch);
 338	case KVM_REG_RISCV_CSR_REG(sepc):
 339		return RISCV_CSR_GENERAL(sepc);
 340	case KVM_REG_RISCV_CSR_REG(scause):
 341		return RISCV_CSR_GENERAL(scause);
 342	case KVM_REG_RISCV_CSR_REG(stval):
 343		return RISCV_CSR_GENERAL(stval);
 344	case KVM_REG_RISCV_CSR_REG(sip):
 345		return RISCV_CSR_GENERAL(sip);
 346	case KVM_REG_RISCV_CSR_REG(satp):
 347		return RISCV_CSR_GENERAL(satp);
 348	case KVM_REG_RISCV_CSR_REG(scounteren):
 349		return RISCV_CSR_GENERAL(scounteren);
 350	case KVM_REG_RISCV_CSR_REG(senvcfg):
 351		return RISCV_CSR_GENERAL(senvcfg);
 352	}
 353
 354	return strdup_printf("KVM_REG_RISCV_CSR_GENERAL | %lld /* UNKNOWN */", reg_off);
 355}
 356
 357static const char *aia_csr_id_to_str(__u64 reg_off)
 358{
 359	/* reg_off is the offset into struct kvm_riscv_aia_csr */
 360	switch (reg_off) {
 361	case KVM_REG_RISCV_CSR_AIA_REG(siselect):
 362		return RISCV_CSR_AIA(siselect);
 363	case KVM_REG_RISCV_CSR_AIA_REG(iprio1):
 364		return RISCV_CSR_AIA(iprio1);
 365	case KVM_REG_RISCV_CSR_AIA_REG(iprio2):
 366		return RISCV_CSR_AIA(iprio2);
 367	case KVM_REG_RISCV_CSR_AIA_REG(sieh):
 368		return RISCV_CSR_AIA(sieh);
 369	case KVM_REG_RISCV_CSR_AIA_REG(siph):
 370		return RISCV_CSR_AIA(siph);
 371	case KVM_REG_RISCV_CSR_AIA_REG(iprio1h):
 372		return RISCV_CSR_AIA(iprio1h);
 373	case KVM_REG_RISCV_CSR_AIA_REG(iprio2h):
 374		return RISCV_CSR_AIA(iprio2h);
 375	}
 376
 377	return strdup_printf("KVM_REG_RISCV_CSR_AIA | %lld /* UNKNOWN */", reg_off);
 378}
 379
 380static const char *smstateen_csr_id_to_str(__u64 reg_off)
 381{
 382	/* reg_off is the offset into struct kvm_riscv_smstateen_csr */
 383	switch (reg_off) {
 384	case KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0):
 385		return RISCV_CSR_SMSTATEEN(sstateen0);
 386	}
 387
 388	TEST_FAIL("Unknown smstateen csr reg: 0x%llx", reg_off);
 389	return NULL;
 390}
 391
 392static const char *csr_id_to_str(const char *prefix, __u64 id)
 393{
 394	__u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CSR);
 395	__u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK;
 396
 397	assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR);
 398
 399	reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK;
 400
 401	switch (reg_subtype) {
 402	case KVM_REG_RISCV_CSR_GENERAL:
 403		return general_csr_id_to_str(reg_off);
 404	case KVM_REG_RISCV_CSR_AIA:
 405		return aia_csr_id_to_str(reg_off);
 406	case KVM_REG_RISCV_CSR_SMSTATEEN:
 407		return smstateen_csr_id_to_str(reg_off);
 408	}
 409
 410	return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off);
 411}
 412
 413static const char *timer_id_to_str(const char *prefix, __u64 id)
 414{
 415	/* reg_off is the offset into struct kvm_riscv_timer */
 416	__u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_TIMER);
 417
 418	assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER);
 419
 420	switch (reg_off) {
 421	case KVM_REG_RISCV_TIMER_REG(frequency):
 422		return "KVM_REG_RISCV_TIMER_REG(frequency)";
 423	case KVM_REG_RISCV_TIMER_REG(time):
 424		return "KVM_REG_RISCV_TIMER_REG(time)";
 425	case KVM_REG_RISCV_TIMER_REG(compare):
 426		return "KVM_REG_RISCV_TIMER_REG(compare)";
 427	case KVM_REG_RISCV_TIMER_REG(state):
 428		return "KVM_REG_RISCV_TIMER_REG(state)";
 429	}
 430
 431	return strdup_printf("%lld /* UNKNOWN */", reg_off);
 432}
 433
 434static const char *fp_f_id_to_str(const char *prefix, __u64 id)
 435{
 436	/* reg_off is the offset into struct __riscv_f_ext_state */
 437	__u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_FP_F);
 438
 439	assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F);
 440
 441	switch (reg_off) {
 442	case KVM_REG_RISCV_FP_F_REG(f[0]) ...
 443	     KVM_REG_RISCV_FP_F_REG(f[31]):
 444		return strdup_printf("KVM_REG_RISCV_FP_F_REG(f[%lld])", reg_off);
 445	case KVM_REG_RISCV_FP_F_REG(fcsr):
 446		return "KVM_REG_RISCV_FP_F_REG(fcsr)";
 447	}
 448
 449	return strdup_printf("%lld /* UNKNOWN */", reg_off);
 450}
 451
 452static const char *fp_d_id_to_str(const char *prefix, __u64 id)
 453{
 454	/* reg_off is the offset into struct __riscv_d_ext_state */
 455	__u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_FP_D);
 456
 457	assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D);
 458
 459	switch (reg_off) {
 460	case KVM_REG_RISCV_FP_D_REG(f[0]) ...
 461	     KVM_REG_RISCV_FP_D_REG(f[31]):
 462		return strdup_printf("KVM_REG_RISCV_FP_D_REG(f[%lld])", reg_off);
 463	case KVM_REG_RISCV_FP_D_REG(fcsr):
 464		return "KVM_REG_RISCV_FP_D_REG(fcsr)";
 465	}
 466
 467	return strdup_printf("%lld /* UNKNOWN */", reg_off);
 468}
 469
 470static const char *vector_id_to_str(const char *prefix, __u64 id)
 471{
 472	/* reg_off is the offset into struct __riscv_v_ext_state */
 473	__u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_VECTOR);
 474	int reg_index = 0;
 475
 476	assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_VECTOR);
 477
 478	if (reg_off >= KVM_REG_RISCV_VECTOR_REG(0))
 479		reg_index = reg_off -  KVM_REG_RISCV_VECTOR_REG(0);
 480	switch (reg_off) {
 481	case KVM_REG_RISCV_VECTOR_REG(0) ...
 482	     KVM_REG_RISCV_VECTOR_REG(31):
 483		return strdup_printf("KVM_REG_RISCV_VECTOR_REG(%d)", reg_index);
 484	case KVM_REG_RISCV_VECTOR_CSR_REG(vstart):
 485		return "KVM_REG_RISCV_VECTOR_CSR_REG(vstart)";
 486	case KVM_REG_RISCV_VECTOR_CSR_REG(vl):
 487		return "KVM_REG_RISCV_VECTOR_CSR_REG(vl)";
 488	case KVM_REG_RISCV_VECTOR_CSR_REG(vtype):
 489		return "KVM_REG_RISCV_VECTOR_CSR_REG(vtype)";
 490	case KVM_REG_RISCV_VECTOR_CSR_REG(vcsr):
 491		return "KVM_REG_RISCV_VECTOR_CSR_REG(vcsr)";
 492	case KVM_REG_RISCV_VECTOR_CSR_REG(vlenb):
 493		return "KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)";
 494	}
 495
 496	return strdup_printf("%lld /* UNKNOWN */", reg_off);
 497}
 498
 499#define KVM_ISA_EXT_ARR(ext)		\
 500[KVM_RISCV_ISA_EXT_##ext] = "KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_" #ext
 501
 502static const char *isa_ext_single_id_to_str(__u64 reg_off)
 503{
 504	static const char * const kvm_isa_ext_reg_name[] = {
 505		KVM_ISA_EXT_ARR(A),
 506		KVM_ISA_EXT_ARR(C),
 507		KVM_ISA_EXT_ARR(D),
 508		KVM_ISA_EXT_ARR(F),
 509		KVM_ISA_EXT_ARR(H),
 510		KVM_ISA_EXT_ARR(I),
 511		KVM_ISA_EXT_ARR(M),
 512		KVM_ISA_EXT_ARR(V),
 513		KVM_ISA_EXT_ARR(SMNPM),
 514		KVM_ISA_EXT_ARR(SMSTATEEN),
 515		KVM_ISA_EXT_ARR(SSAIA),
 516		KVM_ISA_EXT_ARR(SSCOFPMF),
 517		KVM_ISA_EXT_ARR(SSNPM),
 518		KVM_ISA_EXT_ARR(SSTC),
 519		KVM_ISA_EXT_ARR(SVADE),
 520		KVM_ISA_EXT_ARR(SVADU),
 521		KVM_ISA_EXT_ARR(SVINVAL),
 522		KVM_ISA_EXT_ARR(SVNAPOT),
 523		KVM_ISA_EXT_ARR(SVPBMT),
 524		KVM_ISA_EXT_ARR(SVVPTC),
 525		KVM_ISA_EXT_ARR(ZAAMO),
 526		KVM_ISA_EXT_ARR(ZABHA),
 527		KVM_ISA_EXT_ARR(ZACAS),
 528		KVM_ISA_EXT_ARR(ZALRSC),
 529		KVM_ISA_EXT_ARR(ZAWRS),
 530		KVM_ISA_EXT_ARR(ZBA),
 531		KVM_ISA_EXT_ARR(ZBB),
 532		KVM_ISA_EXT_ARR(ZBC),
 533		KVM_ISA_EXT_ARR(ZBKB),
 534		KVM_ISA_EXT_ARR(ZBKC),
 535		KVM_ISA_EXT_ARR(ZBKX),
 536		KVM_ISA_EXT_ARR(ZBS),
 537		KVM_ISA_EXT_ARR(ZCA),
 538		KVM_ISA_EXT_ARR(ZCB),
 539		KVM_ISA_EXT_ARR(ZCD),
 540		KVM_ISA_EXT_ARR(ZCF),
 541		KVM_ISA_EXT_ARR(ZCMOP),
 542		KVM_ISA_EXT_ARR(ZFA),
 543		KVM_ISA_EXT_ARR(ZFBFMIN),
 544		KVM_ISA_EXT_ARR(ZFH),
 545		KVM_ISA_EXT_ARR(ZFHMIN),
 546		KVM_ISA_EXT_ARR(ZICBOM),
 547		KVM_ISA_EXT_ARR(ZICBOP),
 548		KVM_ISA_EXT_ARR(ZICBOZ),
 549		KVM_ISA_EXT_ARR(ZICCRSE),
 550		KVM_ISA_EXT_ARR(ZICNTR),
 551		KVM_ISA_EXT_ARR(ZICOND),
 552		KVM_ISA_EXT_ARR(ZICSR),
 553		KVM_ISA_EXT_ARR(ZIFENCEI),
 554		KVM_ISA_EXT_ARR(ZIHINTNTL),
 555		KVM_ISA_EXT_ARR(ZIHINTPAUSE),
 556		KVM_ISA_EXT_ARR(ZIHPM),
 557		KVM_ISA_EXT_ARR(ZIMOP),
 558		KVM_ISA_EXT_ARR(ZKND),
 559		KVM_ISA_EXT_ARR(ZKNE),
 560		KVM_ISA_EXT_ARR(ZKNH),
 561		KVM_ISA_EXT_ARR(ZKR),
 562		KVM_ISA_EXT_ARR(ZKSED),
 563		KVM_ISA_EXT_ARR(ZKSH),
 564		KVM_ISA_EXT_ARR(ZKT),
 565		KVM_ISA_EXT_ARR(ZTSO),
 566		KVM_ISA_EXT_ARR(ZVBB),
 567		KVM_ISA_EXT_ARR(ZVBC),
 568		KVM_ISA_EXT_ARR(ZVFBFMIN),
 569		KVM_ISA_EXT_ARR(ZVFBFWMA),
 570		KVM_ISA_EXT_ARR(ZVFH),
 571		KVM_ISA_EXT_ARR(ZVFHMIN),
 572		KVM_ISA_EXT_ARR(ZVKB),
 573		KVM_ISA_EXT_ARR(ZVKG),
 574		KVM_ISA_EXT_ARR(ZVKNED),
 575		KVM_ISA_EXT_ARR(ZVKNHA),
 576		KVM_ISA_EXT_ARR(ZVKNHB),
 577		KVM_ISA_EXT_ARR(ZVKSED),
 578		KVM_ISA_EXT_ARR(ZVKSH),
 579		KVM_ISA_EXT_ARR(ZVKT),
 580	};
 581
 582	if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name))
 583		return strdup_printf("KVM_REG_RISCV_ISA_SINGLE | %lld /* UNKNOWN */", reg_off);
 584
 585	return kvm_isa_ext_reg_name[reg_off];
 586}
 587
 588static const char *isa_ext_multi_id_to_str(__u64 reg_subtype, __u64 reg_off)
 589{
 590	const char *unknown = "";
 591
 592	if (reg_off > KVM_REG_RISCV_ISA_MULTI_REG_LAST)
 593		unknown = " /* UNKNOWN */";
 594
 595	switch (reg_subtype) {
 596	case KVM_REG_RISCV_ISA_MULTI_EN:
 597		return strdup_printf("KVM_REG_RISCV_ISA_MULTI_EN | %lld%s", reg_off, unknown);
 598	case KVM_REG_RISCV_ISA_MULTI_DIS:
 599		return strdup_printf("KVM_REG_RISCV_ISA_MULTI_DIS | %lld%s", reg_off, unknown);
 600	}
 601
 602	return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off);
 603}
 604
 605static const char *isa_ext_id_to_str(const char *prefix, __u64 id)
 606{
 607	__u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_ISA_EXT);
 608	__u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK;
 609
 610	assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT);
 611
 612	reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK;
 613
 614	switch (reg_subtype) {
 615	case KVM_REG_RISCV_ISA_SINGLE:
 616		return isa_ext_single_id_to_str(reg_off);
 617	case KVM_REG_RISCV_ISA_MULTI_EN:
 618	case KVM_REG_RISCV_ISA_MULTI_DIS:
 619		return isa_ext_multi_id_to_str(reg_subtype, reg_off);
 620	}
 621
 622	return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off);
 623}
 624
 625#define KVM_SBI_EXT_ARR(ext)		\
 626[ext] = "KVM_REG_RISCV_SBI_SINGLE | " #ext
 627
 628static const char *sbi_ext_single_id_to_str(__u64 reg_off)
 629{
 630	/* reg_off is KVM_RISCV_SBI_EXT_ID */
 631	static const char * const kvm_sbi_ext_reg_name[] = {
 632		KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_V01),
 633		KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_TIME),
 634		KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_IPI),
 635		KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_RFENCE),
 636		KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_SRST),
 637		KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_HSM),
 638		KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_PMU),
 639		KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_DBCN),
 640		KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_SUSP),
 641		KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_STA),
 642		KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_FWFT),
 643		KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_MPXY),
 644		KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_EXPERIMENTAL),
 645		KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_VENDOR),
 646	};
 647
 648	if (reg_off >= ARRAY_SIZE(kvm_sbi_ext_reg_name))
 649		return strdup_printf("KVM_REG_RISCV_SBI_SINGLE | %lld /* UNKNOWN */", reg_off);
 650
 651	return kvm_sbi_ext_reg_name[reg_off];
 652}
 653
 654static const char *sbi_ext_multi_id_to_str(__u64 reg_subtype, __u64 reg_off)
 655{
 656	const char *unknown = "";
 657
 658	if (reg_off > KVM_REG_RISCV_SBI_MULTI_REG_LAST)
 659		unknown = " /* UNKNOWN */";
 660
 661	switch (reg_subtype) {
 662	case KVM_REG_RISCV_SBI_MULTI_EN:
 663		return strdup_printf("KVM_REG_RISCV_SBI_MULTI_EN | %lld%s", reg_off, unknown);
 664	case KVM_REG_RISCV_SBI_MULTI_DIS:
 665		return strdup_printf("KVM_REG_RISCV_SBI_MULTI_DIS | %lld%s", reg_off, unknown);
 666	}
 667
 668	return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off);
 669}
 670
 671static const char *sbi_ext_id_to_str(const char *prefix, __u64 id)
 672{
 673	__u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_SBI_EXT);
 674	__u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK;
 675
 676	assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_SBI_EXT);
 677
 678	reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK;
 679
 680	switch (reg_subtype) {
 681	case KVM_REG_RISCV_SBI_SINGLE:
 682		return sbi_ext_single_id_to_str(reg_off);
 683	case KVM_REG_RISCV_SBI_MULTI_EN:
 684	case KVM_REG_RISCV_SBI_MULTI_DIS:
 685		return sbi_ext_multi_id_to_str(reg_subtype, reg_off);
 686	}
 687
 688	return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off);
 689}
 690
 691static const char *sbi_sta_id_to_str(__u64 reg_off)
 692{
 693	switch (reg_off) {
 694	case 0: return "KVM_REG_RISCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_lo)";
 695	case 1: return "KVM_REG_RISCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_hi)";
 696	}
 697	return strdup_printf("KVM_REG_RISCV_SBI_STA | %lld /* UNKNOWN */", reg_off);
 698}
 699
 700static const char *sbi_fwft_id_to_str(__u64 reg_off)
 701{
 702	switch (reg_off) {
 703	case 0: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.enable)";
 704	case 1: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.flags)";
 705	case 2: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.value)";
 706	case 3: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.enable)";
 707	case 4: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.flags)";
 708	case 5: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.value)";
 709	}
 710	return strdup_printf("KVM_REG_RISCV_SBI_FWFT | %lld /* UNKNOWN */", reg_off);
 711}
 712
 713static const char *sbi_id_to_str(const char *prefix, __u64 id)
 714{
 715	__u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_SBI_STATE);
 716	__u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK;
 717
 718	assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_SBI_STATE);
 719
 720	reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK;
 721
 722	switch (reg_subtype) {
 723	case KVM_REG_RISCV_SBI_STA:
 724		return sbi_sta_id_to_str(reg_off);
 725	case KVM_REG_RISCV_SBI_FWFT:
 726		return sbi_fwft_id_to_str(reg_off);
 727	}
 728
 729	return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off);
 730}
 731
 732void print_reg(const char *prefix, __u64 id)
 733{
 734	const char *reg_size = NULL;
 735
 736	TEST_ASSERT((id & KVM_REG_ARCH_MASK) == KVM_REG_RISCV,
 737		    "%s: KVM_REG_RISCV missing in reg id: 0x%llx", prefix, id);
 738
 739	switch (id & KVM_REG_SIZE_MASK) {
 740	case KVM_REG_SIZE_U32:
 741		reg_size = "KVM_REG_SIZE_U32";
 742		break;
 743	case KVM_REG_SIZE_U64:
 744		reg_size = "KVM_REG_SIZE_U64";
 745		break;
 746	case KVM_REG_SIZE_U128:
 747		reg_size = "KVM_REG_SIZE_U128";
 748		break;
 749	case KVM_REG_SIZE_U256:
 750		reg_size = "KVM_REG_SIZE_U256";
 751		break;
 752	default:
 753		printf("\tKVM_REG_RISCV | (%lld << KVM_REG_SIZE_SHIFT) | 0x%llx /* UNKNOWN */,\n",
 754		       (id & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT, id & ~REG_MASK);
 755		return;
 756	}
 757
 758	switch (id & KVM_REG_RISCV_TYPE_MASK) {
 759	case KVM_REG_RISCV_CONFIG:
 760		printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_CONFIG | %s,\n",
 761				reg_size, config_id_to_str(prefix, id));
 762		break;
 763	case KVM_REG_RISCV_CORE:
 764		printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_CORE | %s,\n",
 765				reg_size, core_id_to_str(prefix, id));
 766		break;
 767	case KVM_REG_RISCV_CSR:
 768		printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_CSR | %s,\n",
 769				reg_size, csr_id_to_str(prefix, id));
 770		break;
 771	case KVM_REG_RISCV_TIMER:
 772		printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_TIMER | %s,\n",
 773				reg_size, timer_id_to_str(prefix, id));
 774		break;
 775	case KVM_REG_RISCV_FP_F:
 776		printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_FP_F | %s,\n",
 777				reg_size, fp_f_id_to_str(prefix, id));
 778		break;
 779	case KVM_REG_RISCV_FP_D:
 780		printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_FP_D | %s,\n",
 781				reg_size, fp_d_id_to_str(prefix, id));
 782		break;
 783	case KVM_REG_RISCV_VECTOR:
 784		printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_VECTOR | %s,\n",
 785		       reg_size, vector_id_to_str(prefix, id));
 786		break;
 787	case KVM_REG_RISCV_ISA_EXT:
 788		printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_ISA_EXT | %s,\n",
 789				reg_size, isa_ext_id_to_str(prefix, id));
 790		break;
 791	case KVM_REG_RISCV_SBI_EXT:
 792		printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_SBI_EXT | %s,\n",
 793				reg_size, sbi_ext_id_to_str(prefix, id));
 794		break;
 795	case KVM_REG_RISCV_SBI_STATE:
 796		printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_SBI_STATE | %s,\n",
 797				reg_size, sbi_id_to_str(prefix, id));
 798		break;
 799	default:
 800		printf("\tKVM_REG_RISCV | %s | 0x%llx /* UNKNOWN */,\n",
 801				reg_size, id & ~REG_MASK);
 802		return;
 803	}
 804}
 805
 806/*
 807 * The current blessed list was primed with the output of kernel version
 808 * v6.5-rc3 and then later updated with new registers.
 809 */
 810static __u64 base_regs[] = {
 811	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(isa),
 812	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbom_block_size),
 813	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(mvendorid),
 814	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(marchid),
 815	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(mimpid),
 816	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicboz_block_size),
 817	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(satp_mode),
 818	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbop_block_size),
 819	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.pc),
 820	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.ra),
 821	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.sp),
 822	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.gp),
 823	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.tp),
 824	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t0),
 825	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t1),
 826	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t2),
 827	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s0),
 828	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s1),
 829	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a0),
 830	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a1),
 831	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a2),
 832	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a3),
 833	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a4),
 834	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a5),
 835	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a6),
 836	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a7),
 837	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s2),
 838	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s3),
 839	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s4),
 840	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s5),
 841	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s6),
 842	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s7),
 843	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s8),
 844	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s9),
 845	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s10),
 846	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s11),
 847	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t3),
 848	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t4),
 849	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t5),
 850	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t6),
 851	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(mode),
 852	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sstatus),
 853	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sie),
 854	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(stvec),
 855	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sscratch),
 856	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sepc),
 857	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(scause),
 858	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(stval),
 859	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sip),
 860	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(satp),
 861	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(scounteren),
 862	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(senvcfg),
 863	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(frequency),
 864	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(time),
 865	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(compare),
 866	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(state),
 867};
 868
 869/*
 870 * The skips_set list registers that should skip set test.
 871 *  - KVM_REG_RISCV_TIMER_REG(state): set would fail if it was not initialized properly.
 872 */
 873static __u64 base_skips_set[] = {
 874	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(state),
 875};
 876
 877static __u64 sbi_base_regs[] = {
 878	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_V01,
 879	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_TIME,
 880	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_IPI,
 881	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_RFENCE,
 882	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_SRST,
 883	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_HSM,
 884	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_EXPERIMENTAL,
 885	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_VENDOR,
 886};
 887
 888static __u64 sbi_sta_regs[] = {
 889	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_STA,
 890	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_lo),
 891	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_hi),
 892};
 893
 894static __u64 sbi_fwft_regs[] = {
 895	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_FWFT,
 896	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.enable),
 897	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.flags),
 898	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.value),
 899	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.enable),
 900	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.flags),
 901	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.value),
 902};
 903
 904static __u64 zicbom_regs[] = {
 905	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbom_block_size),
 906	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM,
 907};
 908
 909static __u64 zicbop_regs[] = {
 910	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbop_block_size),
 911	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOP,
 912};
 913
 914static __u64 zicboz_regs[] = {
 915	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicboz_block_size),
 916	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ,
 917};
 918
 919static __u64 aia_regs[] = {
 920	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect),
 921	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1),
 922	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2),
 923	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(sieh),
 924	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siph),
 925	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1h),
 926	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2h),
 927	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSAIA,
 928};
 929
 930static __u64 smstateen_regs[] = {
 931	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0),
 932	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SMSTATEEN,
 933};
 934
 935static __u64 fp_f_regs[] = {
 936	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[0]),
 937	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[1]),
 938	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[2]),
 939	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[3]),
 940	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[4]),
 941	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[5]),
 942	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[6]),
 943	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[7]),
 944	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[8]),
 945	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[9]),
 946	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[10]),
 947	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[11]),
 948	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[12]),
 949	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[13]),
 950	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[14]),
 951	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[15]),
 952	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[16]),
 953	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[17]),
 954	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[18]),
 955	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[19]),
 956	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[20]),
 957	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[21]),
 958	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[22]),
 959	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[23]),
 960	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[24]),
 961	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[25]),
 962	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[26]),
 963	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[27]),
 964	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[28]),
 965	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[29]),
 966	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[30]),
 967	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[31]),
 968	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(fcsr),
 969	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_F,
 970};
 971
 972static __u64 fp_d_regs[] = {
 973	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[0]),
 974	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[1]),
 975	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[2]),
 976	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[3]),
 977	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[4]),
 978	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[5]),
 979	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[6]),
 980	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[7]),
 981	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[8]),
 982	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[9]),
 983	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[10]),
 984	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[11]),
 985	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[12]),
 986	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[13]),
 987	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[14]),
 988	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[15]),
 989	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[16]),
 990	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[17]),
 991	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[18]),
 992	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[19]),
 993	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[20]),
 994	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[21]),
 995	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[22]),
 996	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[23]),
 997	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[24]),
 998	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[25]),
 999	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[26]),
1000	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[27]),
1001	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[28]),
1002	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[29]),
1003	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[30]),
1004	KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[31]),
1005	KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(fcsr),
1006	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_D,
1007};
1008
1009/* Define a default vector registers with length. This will be overwritten at runtime */
1010static __u64 vector_regs[] = {
1011	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_CSR_REG(vstart),
1012	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_CSR_REG(vl),
1013	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_CSR_REG(vtype),
1014	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_CSR_REG(vcsr),
1015	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_CSR_REG(vlenb),
1016	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(0),
1017	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(1),
1018	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(2),
1019	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(3),
1020	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(4),
1021	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(5),
1022	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(6),
1023	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(7),
1024	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(8),
1025	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(9),
1026	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(10),
1027	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(11),
1028	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(12),
1029	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(13),
1030	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(14),
1031	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(15),
1032	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(16),
1033	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(17),
1034	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(18),
1035	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(19),
1036	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(20),
1037	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(21),
1038	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(22),
1039	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(23),
1040	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(24),
1041	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(25),
1042	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(26),
1043	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(27),
1044	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(28),
1045	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(29),
1046	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(30),
1047	KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(31),
1048	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_V,
1049};
1050
1051#define SUBLIST_BASE \
1052	{"base", .regs = base_regs, .regs_n = ARRAY_SIZE(base_regs), \
1053	 .skips_set = base_skips_set, .skips_set_n = ARRAY_SIZE(base_skips_set),}
1054#define SUBLIST_SBI_BASE \
1055	{"sbi-base", .feature_type = VCPU_FEATURE_SBI_EXT, .feature = KVM_RISCV_SBI_EXT_V01, \
1056	 .regs = sbi_base_regs, .regs_n = ARRAY_SIZE(sbi_base_regs),}
1057#define SUBLIST_SBI_STA \
1058	{"sbi-sta", .feature_type = VCPU_FEATURE_SBI_EXT, .feature = KVM_RISCV_SBI_EXT_STA, \
1059	 .regs = sbi_sta_regs, .regs_n = ARRAY_SIZE(sbi_sta_regs),}
1060#define SUBLIST_SBI_FWFT \
1061	{"sbi-fwft", .feature_type = VCPU_FEATURE_SBI_EXT, .feature = KVM_RISCV_SBI_EXT_FWFT, \
1062	 .regs = sbi_fwft_regs, .regs_n = ARRAY_SIZE(sbi_fwft_regs),}
1063#define SUBLIST_ZICBOM \
1064	{"zicbom", .feature = KVM_RISCV_ISA_EXT_ZICBOM, .regs = zicbom_regs, .regs_n = ARRAY_SIZE(zicbom_regs),}
1065#define SUBLIST_ZICBOP \
1066	{"zicbop", .feature = KVM_RISCV_ISA_EXT_ZICBOP, .regs = zicbop_regs, .regs_n = ARRAY_SIZE(zicbop_regs),}
1067#define SUBLIST_ZICBOZ \
1068	{"zicboz", .feature = KVM_RISCV_ISA_EXT_ZICBOZ, .regs = zicboz_regs, .regs_n = ARRAY_SIZE(zicboz_regs),}
1069#define SUBLIST_AIA \
1070	{"aia", .feature = KVM_RISCV_ISA_EXT_SSAIA, .regs = aia_regs, .regs_n = ARRAY_SIZE(aia_regs),}
1071#define SUBLIST_SMSTATEEN \
1072	{"smstateen", .feature = KVM_RISCV_ISA_EXT_SMSTATEEN, .regs = smstateen_regs, .regs_n = ARRAY_SIZE(smstateen_regs),}
1073#define SUBLIST_FP_F \
1074	{"fp_f", .feature = KVM_RISCV_ISA_EXT_F, .regs = fp_f_regs, \
1075		.regs_n = ARRAY_SIZE(fp_f_regs),}
1076#define SUBLIST_FP_D \
1077	{"fp_d", .feature = KVM_RISCV_ISA_EXT_D, .regs = fp_d_regs, \
1078		.regs_n = ARRAY_SIZE(fp_d_regs),}
1079
1080#define SUBLIST_V \
1081	{"v", .feature = KVM_RISCV_ISA_EXT_V, .regs = vector_regs, .regs_n = ARRAY_SIZE(vector_regs),}
1082
1083#define KVM_ISA_EXT_SIMPLE_CONFIG(ext, extu)			\
1084static __u64 regs_##ext[] = {					\
1085	KVM_REG_RISCV | KVM_REG_SIZE_ULONG |			\
1086	KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE |	\
1087	KVM_RISCV_ISA_EXT_##extu,				\
1088};								\
1089static struct vcpu_reg_list config_##ext = {			\
1090	.sublists = {						\
1091		SUBLIST_BASE,					\
1092		{						\
1093			.name = #ext,				\
1094			.feature = KVM_RISCV_ISA_EXT_##extu,	\
1095			.regs = regs_##ext,			\
1096			.regs_n = ARRAY_SIZE(regs_##ext),	\
1097		},						\
1098		{0},						\
1099	},							\
1100}								\
1101
1102#define KVM_SBI_EXT_SIMPLE_CONFIG(ext, extu)			\
1103static __u64 regs_sbi_##ext[] = {				\
1104	KVM_REG_RISCV | KVM_REG_SIZE_ULONG |			\
1105	KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE |	\
1106	KVM_RISCV_SBI_EXT_##extu,				\
1107};								\
1108static struct vcpu_reg_list config_sbi_##ext = {		\
1109	.sublists = {						\
1110		SUBLIST_BASE,					\
1111		{						\
1112			.name = "sbi-"#ext,			\
1113			.feature_type = VCPU_FEATURE_SBI_EXT,	\
1114			.feature = KVM_RISCV_SBI_EXT_##extu,	\
1115			.regs = regs_sbi_##ext,			\
1116			.regs_n = ARRAY_SIZE(regs_sbi_##ext),	\
1117		},						\
1118		{0},						\
1119	},							\
1120}								\
1121
1122#define KVM_ISA_EXT_SUBLIST_CONFIG(ext, extu)			\
1123static struct vcpu_reg_list config_##ext = {			\
1124	.sublists = {						\
1125		SUBLIST_BASE,					\
1126		SUBLIST_##extu,					\
1127		{0},						\
1128	},							\
1129}								\
1130
1131#define KVM_SBI_EXT_SUBLIST_CONFIG(ext, extu)			\
1132static struct vcpu_reg_list config_sbi_##ext = {		\
1133	.sublists = {						\
1134		SUBLIST_BASE,					\
1135		SUBLIST_SBI_##extu,				\
1136		{0},						\
1137	},							\
1138}								\
1139
1140/* Note: The below list is alphabetically sorted. */
1141
1142KVM_SBI_EXT_SUBLIST_CONFIG(base, BASE);
1143KVM_SBI_EXT_SUBLIST_CONFIG(sta, STA);
1144KVM_SBI_EXT_SIMPLE_CONFIG(pmu, PMU);
1145KVM_SBI_EXT_SIMPLE_CONFIG(dbcn, DBCN);
1146KVM_SBI_EXT_SIMPLE_CONFIG(susp, SUSP);
1147KVM_SBI_EXT_SIMPLE_CONFIG(mpxy, MPXY);
1148KVM_SBI_EXT_SUBLIST_CONFIG(fwft, FWFT);
1149
1150KVM_ISA_EXT_SUBLIST_CONFIG(aia, AIA);
1151KVM_ISA_EXT_SUBLIST_CONFIG(fp_f, FP_F);
1152KVM_ISA_EXT_SUBLIST_CONFIG(fp_d, FP_D);
1153KVM_ISA_EXT_SUBLIST_CONFIG(v, V);
1154KVM_ISA_EXT_SIMPLE_CONFIG(h, H);
1155KVM_ISA_EXT_SIMPLE_CONFIG(smnpm, SMNPM);
1156KVM_ISA_EXT_SUBLIST_CONFIG(smstateen, SMSTATEEN);
1157KVM_ISA_EXT_SIMPLE_CONFIG(sscofpmf, SSCOFPMF);
1158KVM_ISA_EXT_SIMPLE_CONFIG(ssnpm, SSNPM);
1159KVM_ISA_EXT_SIMPLE_CONFIG(sstc, SSTC);
1160KVM_ISA_EXT_SIMPLE_CONFIG(svade, SVADE);
1161KVM_ISA_EXT_SIMPLE_CONFIG(svadu, SVADU);
1162KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL);
1163KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT);
1164KVM_ISA_EXT_SIMPLE_CONFIG(svpbmt, SVPBMT);
1165KVM_ISA_EXT_SIMPLE_CONFIG(svvptc, SVVPTC);
1166KVM_ISA_EXT_SIMPLE_CONFIG(zaamo, ZAAMO);
1167KVM_ISA_EXT_SIMPLE_CONFIG(zabha, ZABHA);
1168KVM_ISA_EXT_SIMPLE_CONFIG(zacas, ZACAS);
1169KVM_ISA_EXT_SIMPLE_CONFIG(zalrsc, ZALRSC);
1170KVM_ISA_EXT_SIMPLE_CONFIG(zawrs, ZAWRS);
1171KVM_ISA_EXT_SIMPLE_CONFIG(zba, ZBA);
1172KVM_ISA_EXT_SIMPLE_CONFIG(zbb, ZBB);
1173KVM_ISA_EXT_SIMPLE_CONFIG(zbc, ZBC);
1174KVM_ISA_EXT_SIMPLE_CONFIG(zbkb, ZBKB);
1175KVM_ISA_EXT_SIMPLE_CONFIG(zbkc, ZBKC);
1176KVM_ISA_EXT_SIMPLE_CONFIG(zbkx, ZBKX);
1177KVM_ISA_EXT_SIMPLE_CONFIG(zbs, ZBS);
1178KVM_ISA_EXT_SIMPLE_CONFIG(zca, ZCA);
1179KVM_ISA_EXT_SIMPLE_CONFIG(zcb, ZCB);
1180KVM_ISA_EXT_SIMPLE_CONFIG(zcd, ZCD);
1181KVM_ISA_EXT_SIMPLE_CONFIG(zcf, ZCF);
1182KVM_ISA_EXT_SIMPLE_CONFIG(zcmop, ZCMOP);
1183KVM_ISA_EXT_SIMPLE_CONFIG(zfa, ZFA);
1184KVM_ISA_EXT_SIMPLE_CONFIG(zfbfmin, ZFBFMIN);
1185KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH);
1186KVM_ISA_EXT_SIMPLE_CONFIG(zfhmin, ZFHMIN);
1187KVM_ISA_EXT_SUBLIST_CONFIG(zicbom, ZICBOM);
1188KVM_ISA_EXT_SUBLIST_CONFIG(zicbop, ZICBOP);
1189KVM_ISA_EXT_SUBLIST_CONFIG(zicboz, ZICBOZ);
1190KVM_ISA_EXT_SIMPLE_CONFIG(ziccrse, ZICCRSE);
1191KVM_ISA_EXT_SIMPLE_CONFIG(zicntr, ZICNTR);
1192KVM_ISA_EXT_SIMPLE_CONFIG(zicond, ZICOND);
1193KVM_ISA_EXT_SIMPLE_CONFIG(zicsr, ZICSR);
1194KVM_ISA_EXT_SIMPLE_CONFIG(zifencei, ZIFENCEI);
1195KVM_ISA_EXT_SIMPLE_CONFIG(zihintntl, ZIHINTNTL);
1196KVM_ISA_EXT_SIMPLE_CONFIG(zihintpause, ZIHINTPAUSE);
1197KVM_ISA_EXT_SIMPLE_CONFIG(zihpm, ZIHPM);
1198KVM_ISA_EXT_SIMPLE_CONFIG(zimop, ZIMOP);
1199KVM_ISA_EXT_SIMPLE_CONFIG(zknd, ZKND);
1200KVM_ISA_EXT_SIMPLE_CONFIG(zkne, ZKNE);
1201KVM_ISA_EXT_SIMPLE_CONFIG(zknh, ZKNH);
1202KVM_ISA_EXT_SIMPLE_CONFIG(zkr, ZKR);
1203KVM_ISA_EXT_SIMPLE_CONFIG(zksed, ZKSED);
1204KVM_ISA_EXT_SIMPLE_CONFIG(zksh, ZKSH);
1205KVM_ISA_EXT_SIMPLE_CONFIG(zkt, ZKT);
1206KVM_ISA_EXT_SIMPLE_CONFIG(ztso, ZTSO);
1207KVM_ISA_EXT_SIMPLE_CONFIG(zvbb, ZVBB);
1208KVM_ISA_EXT_SIMPLE_CONFIG(zvbc, ZVBC);
1209KVM_ISA_EXT_SIMPLE_CONFIG(zvfbfmin, ZVFBFMIN);
1210KVM_ISA_EXT_SIMPLE_CONFIG(zvfbfwma, ZVFBFWMA);
1211KVM_ISA_EXT_SIMPLE_CONFIG(zvfh, ZVFH);
1212KVM_ISA_EXT_SIMPLE_CONFIG(zvfhmin, ZVFHMIN);
1213KVM_ISA_EXT_SIMPLE_CONFIG(zvkb, ZVKB);
1214KVM_ISA_EXT_SIMPLE_CONFIG(zvkg, ZVKG);
1215KVM_ISA_EXT_SIMPLE_CONFIG(zvkned, ZVKNED);
1216KVM_ISA_EXT_SIMPLE_CONFIG(zvknha, ZVKNHA);
1217KVM_ISA_EXT_SIMPLE_CONFIG(zvknhb, ZVKNHB);
1218KVM_ISA_EXT_SIMPLE_CONFIG(zvksed, ZVKSED);
1219KVM_ISA_EXT_SIMPLE_CONFIG(zvksh, ZVKSH);
1220KVM_ISA_EXT_SIMPLE_CONFIG(zvkt, ZVKT);
1221
1222struct vcpu_reg_list *vcpu_configs[] = {
1223	&config_sbi_base,
1224	&config_sbi_sta,
1225	&config_sbi_pmu,
1226	&config_sbi_dbcn,
1227	&config_sbi_susp,
1228	&config_sbi_mpxy,
1229	&config_sbi_fwft,
1230	&config_aia,
1231	&config_fp_f,
1232	&config_fp_d,
1233	&config_h,
1234	&config_v,
1235	&config_smnpm,
1236	&config_smstateen,
1237	&config_sscofpmf,
1238	&config_ssnpm,
1239	&config_sstc,
1240	&config_svade,
1241	&config_svadu,
1242	&config_svinval,
1243	&config_svnapot,
1244	&config_svpbmt,
1245	&config_svvptc,
1246	&config_zaamo,
1247	&config_zabha,
1248	&config_zacas,
1249	&config_zalrsc,
1250	&config_zawrs,
1251	&config_zba,
1252	&config_zbb,
1253	&config_zbc,
1254	&config_zbkb,
1255	&config_zbkc,
1256	&config_zbkx,
1257	&config_zbs,
1258	&config_zca,
1259	&config_zcb,
1260	&config_zcd,
1261	&config_zcf,
1262	&config_zcmop,
1263	&config_zfa,
1264	&config_zfbfmin,
1265	&config_zfh,
1266	&config_zfhmin,
1267	&config_zicbom,
1268	&config_zicbop,
1269	&config_zicboz,
1270	&config_ziccrse,
1271	&config_zicntr,
1272	&config_zicond,
1273	&config_zicsr,
1274	&config_zifencei,
1275	&config_zihintntl,
1276	&config_zihintpause,
1277	&config_zihpm,
1278	&config_zimop,
1279	&config_zknd,
1280	&config_zkne,
1281	&config_zknh,
1282	&config_zkr,
1283	&config_zksed,
1284	&config_zksh,
1285	&config_zkt,
1286	&config_ztso,
1287	&config_zvbb,
1288	&config_zvbc,
1289	&config_zvfbfmin,
1290	&config_zvfbfwma,
1291	&config_zvfh,
1292	&config_zvfhmin,
1293	&config_zvkb,
1294	&config_zvkg,
1295	&config_zvkned,
1296	&config_zvknha,
1297	&config_zvknhb,
1298	&config_zvksed,
1299	&config_zvksh,
1300	&config_zvkt,
1301};
1302int vcpu_configs_n = ARRAY_SIZE(vcpu_configs);