processor.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * AArch64 code
  4 *
  5 * Copyright (C) 2018, Red Hat, Inc.
  6 */
  7
  8#include <linux/compiler.h>
  9#include <assert.h>
 10
 11#include "guest_modes.h"
 12#include "kvm_util.h"
 13#include "processor.h"
 14#include "ucall_common.h"
 15#include "vgic.h"
 16
 17#include <linux/bitfield.h>
 18#include <linux/sizes.h>
 19
 20#define DEFAULT_ARM64_GUEST_STACK_VADDR_MIN	0xac0000
 21
 22static vm_vaddr_t exception_handlers;
 23
 24static uint64_t page_align(struct kvm_vm *vm, uint64_t v)
 25{
 26	return (v + vm->page_size) & ~(vm->page_size - 1);
 27}
 28
 29static uint64_t pgd_index(struct kvm_vm *vm, vm_vaddr_t gva)
 30{
 31	unsigned int shift = (vm->pgtable_levels - 1) * (vm->page_shift - 3) + vm->page_shift;
 32	uint64_t mask = (1UL << (vm->va_bits - shift)) - 1;
 33
 34	return (gva >> shift) & mask;
 35}
 36
 37static uint64_t pud_index(struct kvm_vm *vm, vm_vaddr_t gva)
 38{
 39	unsigned int shift = 2 * (vm->page_shift - 3) + vm->page_shift;
 40	uint64_t mask = (1UL << (vm->page_shift - 3)) - 1;
 41
 42	TEST_ASSERT(vm->pgtable_levels == 4,
 43		"Mode %d does not have 4 page table levels", vm->mode);
 44
 45	return (gva >> shift) & mask;
 46}
 47
 48static uint64_t pmd_index(struct kvm_vm *vm, vm_vaddr_t gva)
 49{
 50	unsigned int shift = (vm->page_shift - 3) + vm->page_shift;
 51	uint64_t mask = (1UL << (vm->page_shift - 3)) - 1;
 52
 53	TEST_ASSERT(vm->pgtable_levels >= 3,
 54		"Mode %d does not have >= 3 page table levels", vm->mode);
 55
 56	return (gva >> shift) & mask;
 57}
 58
 59static uint64_t pte_index(struct kvm_vm *vm, vm_vaddr_t gva)
 60{
 61	uint64_t mask = (1UL << (vm->page_shift - 3)) - 1;
 62	return (gva >> vm->page_shift) & mask;
 63}
 64
 65static inline bool use_lpa2_pte_format(struct kvm_vm *vm)
 66{
 67	return (vm->page_size == SZ_4K || vm->page_size == SZ_16K) &&
 68	    (vm->pa_bits > 48 || vm->va_bits > 48);
 69}
 70
 71static uint64_t addr_pte(struct kvm_vm *vm, uint64_t pa, uint64_t attrs)
 72{
 73	uint64_t pte;
 74
 75	if (use_lpa2_pte_format(vm)) {
 76		pte = pa & PTE_ADDR_MASK_LPA2(vm->page_shift);
 77		pte |= FIELD_GET(GENMASK(51, 50), pa) << PTE_ADDR_51_50_LPA2_SHIFT;
 78		attrs &= ~PTE_ADDR_51_50_LPA2;
 79	} else {
 80		pte = pa & PTE_ADDR_MASK(vm->page_shift);
 81		if (vm->page_shift == 16)
 82			pte |= FIELD_GET(GENMASK(51, 48), pa) << PTE_ADDR_51_48_SHIFT;
 83	}
 84	pte |= attrs;
 85
 86	return pte;
 87}
 88
 89static uint64_t pte_addr(struct kvm_vm *vm, uint64_t pte)
 90{
 91	uint64_t pa;
 92
 93	if (use_lpa2_pte_format(vm)) {
 94		pa = pte & PTE_ADDR_MASK_LPA2(vm->page_shift);
 95		pa |= FIELD_GET(PTE_ADDR_51_50_LPA2, pte) << 50;
 96	} else {
 97		pa = pte & PTE_ADDR_MASK(vm->page_shift);
 98		if (vm->page_shift == 16)
 99			pa |= FIELD_GET(PTE_ADDR_51_48, pte) << 48;
100	}
101
102	return pa;
103}
104
105static uint64_t ptrs_per_pgd(struct kvm_vm *vm)
106{
107	unsigned int shift = (vm->pgtable_levels - 1) * (vm->page_shift - 3) + vm->page_shift;
108	return 1 << (vm->va_bits - shift);
109}
110
111static uint64_t __maybe_unused ptrs_per_pte(struct kvm_vm *vm)
112{
113	return 1 << (vm->page_shift - 3);
114}
115
116void virt_arch_pgd_alloc(struct kvm_vm *vm)
117{
118	size_t nr_pages = page_align(vm, ptrs_per_pgd(vm) * 8) / vm->page_size;
119
120	if (vm->pgd_created)
121		return;
122
123	vm->pgd = vm_phy_pages_alloc(vm, nr_pages,
124				     KVM_GUEST_PAGE_TABLE_MIN_PADDR,
125				     vm->memslots[MEM_REGION_PT]);
126	vm->pgd_created = true;
127}
128
129static void _virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr,
130			 uint64_t flags)
131{
132	uint8_t attr_idx = flags & (PTE_ATTRINDX_MASK >> PTE_ATTRINDX_SHIFT);
133	uint64_t pg_attr;
134	uint64_t *ptep;
135
136	TEST_ASSERT((vaddr % vm->page_size) == 0,
137		"Virtual address not on page boundary,\n"
138		"  vaddr: 0x%lx vm->page_size: 0x%x", vaddr, vm->page_size);
139	TEST_ASSERT(sparsebit_is_set(vm->vpages_valid,
140		(vaddr >> vm->page_shift)),
141		"Invalid virtual address, vaddr: 0x%lx", vaddr);
142	TEST_ASSERT((paddr % vm->page_size) == 0,
143		"Physical address not on page boundary,\n"
144		"  paddr: 0x%lx vm->page_size: 0x%x", paddr, vm->page_size);
145	TEST_ASSERT((paddr >> vm->page_shift) <= vm->max_gfn,
146		"Physical address beyond beyond maximum supported,\n"
147		"  paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x",
148		paddr, vm->max_gfn, vm->page_size);
149
150	ptep = addr_gpa2hva(vm, vm->pgd) + pgd_index(vm, vaddr) * 8;
151	if (!*ptep)
152		*ptep = addr_pte(vm, vm_alloc_page_table(vm),
153				 PGD_TYPE_TABLE | PTE_VALID);
154
155	switch (vm->pgtable_levels) {
156	case 4:
157		ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pud_index(vm, vaddr) * 8;
158		if (!*ptep)
159			*ptep = addr_pte(vm, vm_alloc_page_table(vm),
160					 PUD_TYPE_TABLE | PTE_VALID);
161		/* fall through */
162	case 3:
163		ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pmd_index(vm, vaddr) * 8;
164		if (!*ptep)
165			*ptep = addr_pte(vm, vm_alloc_page_table(vm),
166					 PMD_TYPE_TABLE | PTE_VALID);
167		/* fall through */
168	case 2:
169		ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pte_index(vm, vaddr) * 8;
170		break;
171	default:
172		TEST_FAIL("Page table levels must be 2, 3, or 4");
173	}
174
175	pg_attr = PTE_AF | PTE_ATTRINDX(attr_idx) | PTE_TYPE_PAGE | PTE_VALID;
176	if (!use_lpa2_pte_format(vm))
177		pg_attr |= PTE_SHARED;
178
179	*ptep = addr_pte(vm, paddr, pg_attr);
180}
181
182void virt_arch_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr)
183{
184	uint64_t attr_idx = MT_NORMAL;
185
186	_virt_pg_map(vm, vaddr, paddr, attr_idx);
187}
188
189uint64_t *virt_get_pte_hva_at_level(struct kvm_vm *vm, vm_vaddr_t gva, int level)
190{
191	uint64_t *ptep;
192
193	if (!vm->pgd_created)
194		goto unmapped_gva;
195
196	ptep = addr_gpa2hva(vm, vm->pgd) + pgd_index(vm, gva) * 8;
197	if (!ptep)
198		goto unmapped_gva;
199	if (level == 0)
200		return ptep;
201
202	switch (vm->pgtable_levels) {
203	case 4:
204		ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pud_index(vm, gva) * 8;
205		if (!ptep)
206			goto unmapped_gva;
207		if (level == 1)
208			break;
209		/* fall through */
210	case 3:
211		ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pmd_index(vm, gva) * 8;
212		if (!ptep)
213			goto unmapped_gva;
214		if (level == 2)
215			break;
216		/* fall through */
217	case 2:
218		ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pte_index(vm, gva) * 8;
219		if (!ptep)
220			goto unmapped_gva;
221		break;
222	default:
223		TEST_FAIL("Page table levels must be 2, 3, or 4");
224	}
225
226	return ptep;
227
228unmapped_gva:
229	TEST_FAIL("No mapping for vm virtual address, gva: 0x%lx", gva);
230	exit(EXIT_FAILURE);
231}
232
233uint64_t *virt_get_pte_hva(struct kvm_vm *vm, vm_vaddr_t gva)
234{
235	return virt_get_pte_hva_at_level(vm, gva, 3);
236}
237
238vm_paddr_t addr_arch_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva)
239{
240	uint64_t *ptep = virt_get_pte_hva(vm, gva);
241
242	return pte_addr(vm, *ptep) + (gva & (vm->page_size - 1));
243}
244
245static void pte_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent, uint64_t page, int level)
246{
247#ifdef DEBUG
248	static const char * const type[] = { "", "pud", "pmd", "pte" };
249	uint64_t pte, *ptep;
250
251	if (level == 4)
252		return;
253
254	for (pte = page; pte < page + ptrs_per_pte(vm) * 8; pte += 8) {
255		ptep = addr_gpa2hva(vm, pte);
256		if (!*ptep)
257			continue;
258		fprintf(stream, "%*s%s: %lx: %lx at %p\n", indent, "", type[level], pte, *ptep, ptep);
259		pte_dump(stream, vm, indent + 1, pte_addr(vm, *ptep), level + 1);
260	}
261#endif
262}
263
264void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent)
265{
266	int level = 4 - (vm->pgtable_levels - 1);
267	uint64_t pgd, *ptep;
268
269	if (!vm->pgd_created)
270		return;
271
272	for (pgd = vm->pgd; pgd < vm->pgd + ptrs_per_pgd(vm) * 8; pgd += 8) {
273		ptep = addr_gpa2hva(vm, pgd);
274		if (!*ptep)
275			continue;
276		fprintf(stream, "%*spgd: %lx: %lx at %p\n", indent, "", pgd, *ptep, ptep);
277		pte_dump(stream, vm, indent + 1, pte_addr(vm, *ptep), level);
278	}
279}
280
281bool vm_supports_el2(struct kvm_vm *vm)
282{
283	const char *value = getenv("NV");
284
285	if (value && *value == '0')
286		return false;
287
288	return vm_check_cap(vm, KVM_CAP_ARM_EL2) && vm->arch.has_gic;
289}
290
291void kvm_get_default_vcpu_target(struct kvm_vm *vm, struct kvm_vcpu_init *init)
292{
293	struct kvm_vcpu_init preferred = {};
294
295	vm_ioctl(vm, KVM_ARM_PREFERRED_TARGET, &preferred);
296	if (vm_supports_el2(vm))
297		preferred.features[0] |= BIT(KVM_ARM_VCPU_HAS_EL2);
298
299	*init = preferred;
300}
301
302void aarch64_vcpu_setup(struct kvm_vcpu *vcpu, struct kvm_vcpu_init *init)
303{
304	struct kvm_vcpu_init default_init = { .target = -1, };
305	struct kvm_vm *vm = vcpu->vm;
306	uint64_t sctlr_el1, tcr_el1, ttbr0_el1;
307
308	if (!init) {
309		kvm_get_default_vcpu_target(vm, &default_init);
310		init = &default_init;
311	}
312
313	vcpu_ioctl(vcpu, KVM_ARM_VCPU_INIT, init);
314	vcpu->init = *init;
315
316	/*
317	 * Enable FP/ASIMD to avoid trapping when accessing Q0-Q15
318	 * registers, which the variable argument list macros do.
319	 */
320	vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_CPACR_EL1), 3 << 20);
321
322	sctlr_el1 = vcpu_get_reg(vcpu, ctxt_reg_alias(vcpu, SYS_SCTLR_EL1));
323	tcr_el1 = vcpu_get_reg(vcpu, ctxt_reg_alias(vcpu, SYS_TCR_EL1));
324
325	/* Configure base granule size */
326	switch (vm->mode) {
327	case VM_MODE_PXXVYY_4K:
328		TEST_FAIL("AArch64 does not support 4K sized pages "
329			  "with ANY-bit physical address ranges");
330	case VM_MODE_P52V48_64K:
331	case VM_MODE_P48V48_64K:
332	case VM_MODE_P40V48_64K:
333	case VM_MODE_P36V48_64K:
334		tcr_el1 |= TCR_TG0_64K;
335		break;
336	case VM_MODE_P52V48_16K:
337	case VM_MODE_P48V48_16K:
338	case VM_MODE_P40V48_16K:
339	case VM_MODE_P36V48_16K:
340	case VM_MODE_P36V47_16K:
341		tcr_el1 |= TCR_TG0_16K;
342		break;
343	case VM_MODE_P52V48_4K:
344	case VM_MODE_P48V48_4K:
345	case VM_MODE_P40V48_4K:
346	case VM_MODE_P36V48_4K:
347		tcr_el1 |= TCR_TG0_4K;
348		break;
349	default:
350		TEST_FAIL("Unknown guest mode, mode: 0x%x", vm->mode);
351	}
352
353	ttbr0_el1 = vm->pgd & GENMASK(47, vm->page_shift);
354
355	/* Configure output size */
356	switch (vm->mode) {
357	case VM_MODE_P52V48_4K:
358	case VM_MODE_P52V48_16K:
359	case VM_MODE_P52V48_64K:
360		tcr_el1 |= TCR_IPS_52_BITS;
361		ttbr0_el1 |= FIELD_GET(GENMASK(51, 48), vm->pgd) << 2;
362		break;
363	case VM_MODE_P48V48_4K:
364	case VM_MODE_P48V48_16K:
365	case VM_MODE_P48V48_64K:
366		tcr_el1 |= TCR_IPS_48_BITS;
367		break;
368	case VM_MODE_P40V48_4K:
369	case VM_MODE_P40V48_16K:
370	case VM_MODE_P40V48_64K:
371		tcr_el1 |= TCR_IPS_40_BITS;
372		break;
373	case VM_MODE_P36V48_4K:
374	case VM_MODE_P36V48_16K:
375	case VM_MODE_P36V48_64K:
376	case VM_MODE_P36V47_16K:
377		tcr_el1 |= TCR_IPS_36_BITS;
378		break;
379	default:
380		TEST_FAIL("Unknown guest mode, mode: 0x%x", vm->mode);
381	}
382
383	sctlr_el1 |= SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_I;
384
385	tcr_el1 |= TCR_IRGN0_WBWA | TCR_ORGN0_WBWA | TCR_SH0_INNER;
386	tcr_el1 |= TCR_T0SZ(vm->va_bits);
387	if (use_lpa2_pte_format(vm))
388		tcr_el1 |= TCR_DS;
389
390	vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_SCTLR_EL1), sctlr_el1);
391	vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_TCR_EL1), tcr_el1);
392	vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_MAIR_EL1), DEFAULT_MAIR_EL1);
393	vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_TTBR0_EL1), ttbr0_el1);
394	vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_TPIDR_EL1), vcpu->id);
395
396	if (!vcpu_has_el2(vcpu))
397		return;
398
399	vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_HCR_EL2),
400		     HCR_EL2_RW | HCR_EL2_TGE | HCR_EL2_E2H);
401}
402
403void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent)
404{
405	uint64_t pstate, pc;
406
407	pstate = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pstate));
408	pc = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc));
409
410	fprintf(stream, "%*spstate: 0x%.16lx pc: 0x%.16lx\n",
411		indent, "", pstate, pc);
412}
413
414void vcpu_arch_set_entry_point(struct kvm_vcpu *vcpu, void *guest_code)
415{
416	vcpu_set_reg(vcpu, ARM64_CORE_REG(regs.pc), (uint64_t)guest_code);
417}
418
419static struct kvm_vcpu *__aarch64_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id,
420					   struct kvm_vcpu_init *init)
421{
422	size_t stack_size;
423	uint64_t stack_vaddr;
424	struct kvm_vcpu *vcpu = __vm_vcpu_add(vm, vcpu_id);
425
426	stack_size = vm->page_size == 4096 ? DEFAULT_STACK_PGS * vm->page_size :
427					     vm->page_size;
428	stack_vaddr = __vm_vaddr_alloc(vm, stack_size,
429				       DEFAULT_ARM64_GUEST_STACK_VADDR_MIN,
430				       MEM_REGION_DATA);
431
432	aarch64_vcpu_setup(vcpu, init);
433
434	vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_SP_EL1), stack_vaddr + stack_size);
435	return vcpu;
436}
437
438struct kvm_vcpu *aarch64_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id,
439				  struct kvm_vcpu_init *init, void *guest_code)
440{
441	struct kvm_vcpu *vcpu = __aarch64_vcpu_add(vm, vcpu_id, init);
442
443	vcpu_arch_set_entry_point(vcpu, guest_code);
444
445	return vcpu;
446}
447
448struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id)
449{
450	return __aarch64_vcpu_add(vm, vcpu_id, NULL);
451}
452
453void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...)
454{
455	va_list ap;
456	int i;
457
458	TEST_ASSERT(num >= 1 && num <= 8, "Unsupported number of args,\n"
459		    "  num: %u", num);
460
461	va_start(ap, num);
462
463	for (i = 0; i < num; i++) {
464		vcpu_set_reg(vcpu, ARM64_CORE_REG(regs.regs[i]),
465			     va_arg(ap, uint64_t));
466	}
467
468	va_end(ap);
469}
470
471void kvm_exit_unexpected_exception(int vector, uint64_t ec, bool valid_ec)
472{
473	ucall(UCALL_UNHANDLED, 3, vector, ec, valid_ec);
474	while (1)
475		;
476}
477
478void assert_on_unhandled_exception(struct kvm_vcpu *vcpu)
479{
480	struct ucall uc;
481
482	if (get_ucall(vcpu, &uc) != UCALL_UNHANDLED)
483		return;
484
485	if (uc.args[2]) /* valid_ec */ {
486		assert(VECTOR_IS_SYNC(uc.args[0]));
487		TEST_FAIL("Unexpected exception (vector:0x%lx, ec:0x%lx)",
488			  uc.args[0], uc.args[1]);
489	} else {
490		assert(!VECTOR_IS_SYNC(uc.args[0]));
491		TEST_FAIL("Unexpected exception (vector:0x%lx)",
492			  uc.args[0]);
493	}
494}
495
496struct handlers {
497	handler_fn exception_handlers[VECTOR_NUM][ESR_ELx_EC_MAX + 1];
498};
499
500void vcpu_init_descriptor_tables(struct kvm_vcpu *vcpu)
501{
502	extern char vectors;
503
504	vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_VBAR_EL1), (uint64_t)&vectors);
505}
506
507void route_exception(struct ex_regs *regs, int vector)
508{
509	struct handlers *handlers = (struct handlers *)exception_handlers;
510	bool valid_ec;
511	int ec = 0;
512
513	switch (vector) {
514	case VECTOR_SYNC_CURRENT:
515	case VECTOR_SYNC_LOWER_64:
516		ec = ESR_ELx_EC(read_sysreg(esr_el1));
517		valid_ec = true;
518		break;
519	case VECTOR_IRQ_CURRENT:
520	case VECTOR_IRQ_LOWER_64:
521	case VECTOR_FIQ_CURRENT:
522	case VECTOR_FIQ_LOWER_64:
523	case VECTOR_ERROR_CURRENT:
524	case VECTOR_ERROR_LOWER_64:
525		ec = 0;
526		valid_ec = false;
527		break;
528	default:
529		valid_ec = false;
530		goto unexpected_exception;
531	}
532
533	if (handlers && handlers->exception_handlers[vector][ec])
534		return handlers->exception_handlers[vector][ec](regs);
535
536unexpected_exception:
537	kvm_exit_unexpected_exception(vector, ec, valid_ec);
538}
539
540void vm_init_descriptor_tables(struct kvm_vm *vm)
541{
542	vm->handlers = __vm_vaddr_alloc(vm, sizeof(struct handlers),
543					vm->page_size, MEM_REGION_DATA);
544
545	*(vm_vaddr_t *)addr_gva2hva(vm, (vm_vaddr_t)(&exception_handlers)) = vm->handlers;
546}
547
548void vm_install_sync_handler(struct kvm_vm *vm, int vector, int ec,
549			 void (*handler)(struct ex_regs *))
550{
551	struct handlers *handlers = addr_gva2hva(vm, vm->handlers);
552
553	assert(VECTOR_IS_SYNC(vector));
554	assert(vector < VECTOR_NUM);
555	assert(ec <= ESR_ELx_EC_MAX);
556	handlers->exception_handlers[vector][ec] = handler;
557}
558
559void vm_install_exception_handler(struct kvm_vm *vm, int vector,
560			 void (*handler)(struct ex_regs *))
561{
562	struct handlers *handlers = addr_gva2hva(vm, vm->handlers);
563
564	assert(!VECTOR_IS_SYNC(vector));
565	assert(vector < VECTOR_NUM);
566	handlers->exception_handlers[vector][0] = handler;
567}
568
569uint32_t guest_get_vcpuid(void)
570{
571	return read_sysreg(tpidr_el1);
572}
573
574static uint32_t max_ipa_for_page_size(uint32_t vm_ipa, uint32_t gran,
575				uint32_t not_sup_val, uint32_t ipa52_min_val)
576{
577	if (gran == not_sup_val)
578		return 0;
579	else if (gran >= ipa52_min_val && vm_ipa >= 52)
580		return 52;
581	else
582		return min(vm_ipa, 48U);
583}
584
585void aarch64_get_supported_page_sizes(uint32_t ipa, uint32_t *ipa4k,
586					uint32_t *ipa16k, uint32_t *ipa64k)
587{
588	struct kvm_vcpu_init preferred_init;
589	int kvm_fd, vm_fd, vcpu_fd, err;
590	uint64_t val;
591	uint32_t gran;
592	struct kvm_one_reg reg = {
593		.id	= KVM_ARM64_SYS_REG(SYS_ID_AA64MMFR0_EL1),
594		.addr	= (uint64_t)&val,
595	};
596
597	kvm_fd = open_kvm_dev_path_or_exit();
598	vm_fd = __kvm_ioctl(kvm_fd, KVM_CREATE_VM, (void *)(unsigned long)ipa);
599	TEST_ASSERT(vm_fd >= 0, KVM_IOCTL_ERROR(KVM_CREATE_VM, vm_fd));
600
601	vcpu_fd = ioctl(vm_fd, KVM_CREATE_VCPU, 0);
602	TEST_ASSERT(vcpu_fd >= 0, KVM_IOCTL_ERROR(KVM_CREATE_VCPU, vcpu_fd));
603
604	err = ioctl(vm_fd, KVM_ARM_PREFERRED_TARGET, &preferred_init);
605	TEST_ASSERT(err == 0, KVM_IOCTL_ERROR(KVM_ARM_PREFERRED_TARGET, err));
606	err = ioctl(vcpu_fd, KVM_ARM_VCPU_INIT, &preferred_init);
607	TEST_ASSERT(err == 0, KVM_IOCTL_ERROR(KVM_ARM_VCPU_INIT, err));
608
609	err = ioctl(vcpu_fd, KVM_GET_ONE_REG, &reg);
610	TEST_ASSERT(err == 0, KVM_IOCTL_ERROR(KVM_GET_ONE_REG, vcpu_fd));
611
612	gran = FIELD_GET(ID_AA64MMFR0_EL1_TGRAN4, val);
613	*ipa4k = max_ipa_for_page_size(ipa, gran, ID_AA64MMFR0_EL1_TGRAN4_NI,
614					ID_AA64MMFR0_EL1_TGRAN4_52_BIT);
615
616	gran = FIELD_GET(ID_AA64MMFR0_EL1_TGRAN64, val);
617	*ipa64k = max_ipa_for_page_size(ipa, gran, ID_AA64MMFR0_EL1_TGRAN64_NI,
618					ID_AA64MMFR0_EL1_TGRAN64_IMP);
619
620	gran = FIELD_GET(ID_AA64MMFR0_EL1_TGRAN16, val);
621	*ipa16k = max_ipa_for_page_size(ipa, gran, ID_AA64MMFR0_EL1_TGRAN16_NI,
622					ID_AA64MMFR0_EL1_TGRAN16_52_BIT);
623
624	close(vcpu_fd);
625	close(vm_fd);
626	close(kvm_fd);
627}
628
629#define __smccc_call(insn, function_id, arg0, arg1, arg2, arg3, arg4, arg5,	\
630		     arg6, res)							\
631	asm volatile("mov   w0, %w[function_id]\n"				\
632		     "mov   x1, %[arg0]\n"					\
633		     "mov   x2, %[arg1]\n"					\
634		     "mov   x3, %[arg2]\n"					\
635		     "mov   x4, %[arg3]\n"					\
636		     "mov   x5, %[arg4]\n"					\
637		     "mov   x6, %[arg5]\n"					\
638		     "mov   x7, %[arg6]\n"					\
639		     #insn  "#0\n"						\
640		     "mov   %[res0], x0\n"					\
641		     "mov   %[res1], x1\n"					\
642		     "mov   %[res2], x2\n"					\
643		     "mov   %[res3], x3\n"					\
644		     : [res0] "=r"(res->a0), [res1] "=r"(res->a1),		\
645		       [res2] "=r"(res->a2), [res3] "=r"(res->a3)		\
646		     : [function_id] "r"(function_id), [arg0] "r"(arg0),	\
647		       [arg1] "r"(arg1), [arg2] "r"(arg2), [arg3] "r"(arg3),	\
648		       [arg4] "r"(arg4), [arg5] "r"(arg5), [arg6] "r"(arg6)	\
649		     : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7")
650
651
652void smccc_hvc(uint32_t function_id, uint64_t arg0, uint64_t arg1,
653	       uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5,
654	       uint64_t arg6, struct arm_smccc_res *res)
655{
656	__smccc_call(hvc, function_id, arg0, arg1, arg2, arg3, arg4, arg5,
657		     arg6, res);
658}
659
660void smccc_smc(uint32_t function_id, uint64_t arg0, uint64_t arg1,
661	       uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5,
662	       uint64_t arg6, struct arm_smccc_res *res)
663{
664	__smccc_call(smc, function_id, arg0, arg1, arg2, arg3, arg4, arg5,
665		     arg6, res);
666}
667
668void kvm_selftest_arch_init(void)
669{
670	/*
671	 * arm64 doesn't have a true default mode, so start by computing the
672	 * available IPA space and page sizes early.
673	 */
674	guest_modes_append_default();
675}
676
677void vm_vaddr_populate_bitmap(struct kvm_vm *vm)
678{
679	/*
680	 * arm64 selftests use only TTBR0_EL1, meaning that the valid VA space
681	 * is [0, 2^(64 - TCR_EL1.T0SZ)).
682	 */
683	sparsebit_set_num(vm->vpages_valid, 0,
684			  (1ULL << vm->va_bits) >> vm->page_shift);
685}
686
687/* Helper to call wfi instruction. */
688void wfi(void)
689{
690	asm volatile("wfi");
691}
692
693static bool request_mte;
694static bool request_vgic = true;
695
696void test_wants_mte(void)
697{
698	request_mte = true;
699}
700
701void test_disable_default_vgic(void)
702{
703	request_vgic = false;
704}
705
706void kvm_arch_vm_post_create(struct kvm_vm *vm, unsigned int nr_vcpus)
707{
708	if (request_mte && vm_check_cap(vm, KVM_CAP_ARM_MTE))
709		vm_enable_cap(vm, KVM_CAP_ARM_MTE, 0);
710
711	if (request_vgic && kvm_supports_vgic_v3()) {
712		vm->arch.gic_fd = __vgic_v3_setup(vm, nr_vcpus, 64);
713		vm->arch.has_gic = true;
714	}
715}
716
717void kvm_arch_vm_finalize_vcpus(struct kvm_vm *vm)
718{
719	if (vm->arch.has_gic)
720		__vgic_v3_init(vm->arch.gic_fd);
721}
722
723void kvm_arch_vm_release(struct kvm_vm *vm)
724{
725	if (vm->arch.has_gic)
726		close(vm->arch.gic_fd);
727}
728
729bool kvm_arch_has_default_irqchip(void)
730{
731	return request_vgic && kvm_supports_vgic_v3();
732}