svm.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2#ifndef SELFTEST_KVM_SVM_H
  3#define SELFTEST_KVM_SVM_H
  4
  5enum {
  6	INTERCEPT_INTR,
  7	INTERCEPT_NMI,
  8	INTERCEPT_SMI,
  9	INTERCEPT_INIT,
 10	INTERCEPT_VINTR,
 11	INTERCEPT_SELECTIVE_CR0,
 12	INTERCEPT_STORE_IDTR,
 13	INTERCEPT_STORE_GDTR,
 14	INTERCEPT_STORE_LDTR,
 15	INTERCEPT_STORE_TR,
 16	INTERCEPT_LOAD_IDTR,
 17	INTERCEPT_LOAD_GDTR,
 18	INTERCEPT_LOAD_LDTR,
 19	INTERCEPT_LOAD_TR,
 20	INTERCEPT_RDTSC,
 21	INTERCEPT_RDPMC,
 22	INTERCEPT_PUSHF,
 23	INTERCEPT_POPF,
 24	INTERCEPT_CPUID,
 25	INTERCEPT_RSM,
 26	INTERCEPT_IRET,
 27	INTERCEPT_INTn,
 28	INTERCEPT_INVD,
 29	INTERCEPT_PAUSE,
 30	INTERCEPT_HLT,
 31	INTERCEPT_INVLPG,
 32	INTERCEPT_INVLPGA,
 33	INTERCEPT_IOIO_PROT,
 34	INTERCEPT_MSR_PROT,
 35	INTERCEPT_TASK_SWITCH,
 36	INTERCEPT_FERR_FREEZE,
 37	INTERCEPT_SHUTDOWN,
 38	INTERCEPT_VMRUN,
 39	INTERCEPT_VMMCALL,
 40	INTERCEPT_VMLOAD,
 41	INTERCEPT_VMSAVE,
 42	INTERCEPT_STGI,
 43	INTERCEPT_CLGI,
 44	INTERCEPT_SKINIT,
 45	INTERCEPT_RDTSCP,
 46	INTERCEPT_ICEBP,
 47	INTERCEPT_WBINVD,
 48	INTERCEPT_MONITOR,
 49	INTERCEPT_MWAIT,
 50	INTERCEPT_MWAIT_COND,
 51	INTERCEPT_XSETBV,
 52	INTERCEPT_RDPRU,
 53};
 54
 55struct hv_vmcb_enlightenments {
 56	struct __packed hv_enlightenments_control {
 57		u32 nested_flush_hypercall:1;
 58		u32 msr_bitmap:1;
 59		u32 enlightened_npt_tlb: 1;
 60		u32 reserved:29;
 61	} __packed hv_enlightenments_control;
 62	u32 hv_vp_id;
 63	u64 hv_vm_id;
 64	u64 partition_assist_page;
 65	u64 reserved;
 66} __packed;
 67
 68/*
 69 * Hyper-V uses the software reserved clean bit in VMCB
 70 */
 71#define HV_VMCB_NESTED_ENLIGHTENMENTS (1U << 31)
 72
 73/* Synthetic VM-Exit */
 74#define HV_SVM_EXITCODE_ENL			0xf0000000
 75#define HV_SVM_ENL_EXITCODE_TRAP_AFTER_FLUSH	(1)
 76
 77struct __attribute__ ((__packed__)) vmcb_control_area {
 78	u32 intercept_cr;
 79	u32 intercept_dr;
 80	u32 intercept_exceptions;
 81	u64 intercept;
 82	u8 reserved_1[40];
 83	u16 pause_filter_thresh;
 84	u16 pause_filter_count;
 85	u64 iopm_base_pa;
 86	u64 msrpm_base_pa;
 87	u64 tsc_offset;
 88	u32 asid;
 89	u8 tlb_ctl;
 90	u8 reserved_2[3];
 91	u32 int_ctl;
 92	u32 int_vector;
 93	u32 int_state;
 94	u8 reserved_3[4];
 95	u32 exit_code;
 96	u32 exit_code_hi;
 97	u64 exit_info_1;
 98	u64 exit_info_2;
 99	u32 exit_int_info;
100	u32 exit_int_info_err;
101	u64 nested_ctl;
102	u64 avic_vapic_bar;
103	u8 reserved_4[8];
104	u32 event_inj;
105	u32 event_inj_err;
106	u64 nested_cr3;
107	u64 virt_ext;
108	u32 clean;
109	u32 reserved_5;
110	u64 next_rip;
111	u8 insn_len;
112	u8 insn_bytes[15];
113	u64 avic_backing_page;	/* Offset 0xe0 */
114	u8 reserved_6[8];	/* Offset 0xe8 */
115	u64 avic_logical_id;	/* Offset 0xf0 */
116	u64 avic_physical_id;	/* Offset 0xf8 */
117	u8 reserved_7[8];
118	u64 vmsa_pa;		/* Used for an SEV-ES guest */
119	u8 reserved_8[720];
120	/*
121	 * Offset 0x3e0, 32 bytes reserved
122	 * for use by hypervisor/software.
123	 */
124	union {
125		struct hv_vmcb_enlightenments hv_enlightenments;
126		u8 reserved_sw[32];
127	};
128};
129
130
131#define TLB_CONTROL_DO_NOTHING 0
132#define TLB_CONTROL_FLUSH_ALL_ASID 1
133#define TLB_CONTROL_FLUSH_ASID 3
134#define TLB_CONTROL_FLUSH_ASID_LOCAL 7
135
136#define V_TPR_MASK 0x0f
137
138#define V_IRQ_SHIFT 8
139#define V_IRQ_MASK (1 << V_IRQ_SHIFT)
140
141#define V_GIF_SHIFT 9
142#define V_GIF_MASK (1 << V_GIF_SHIFT)
143
144#define V_INTR_PRIO_SHIFT 16
145#define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
146
147#define V_IGN_TPR_SHIFT 20
148#define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
149
150#define V_INTR_MASKING_SHIFT 24
151#define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
152
153#define V_GIF_ENABLE_SHIFT 25
154#define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)
155
156#define AVIC_ENABLE_SHIFT 31
157#define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
158
159#define LBR_CTL_ENABLE_MASK BIT_ULL(0)
160#define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
161
162#define SVM_INTERRUPT_SHADOW_MASK 1
163
164#define SVM_IOIO_STR_SHIFT 2
165#define SVM_IOIO_REP_SHIFT 3
166#define SVM_IOIO_SIZE_SHIFT 4
167#define SVM_IOIO_ASIZE_SHIFT 7
168
169#define SVM_IOIO_TYPE_MASK 1
170#define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
171#define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
172#define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
173#define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
174
175#define SVM_VM_CR_VALID_MASK	0x001fULL
176#define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
177#define SVM_VM_CR_SVM_DIS_MASK  0x0010ULL
178
179#define SVM_NESTED_CTL_NP_ENABLE	BIT(0)
180#define SVM_NESTED_CTL_SEV_ENABLE	BIT(1)
181
182struct __attribute__ ((__packed__)) vmcb_seg {
183	u16 selector;
184	u16 attrib;
185	u32 limit;
186	u64 base;
187};
188
189struct __attribute__ ((__packed__)) vmcb_save_area {
190	struct vmcb_seg es;
191	struct vmcb_seg cs;
192	struct vmcb_seg ss;
193	struct vmcb_seg ds;
194	struct vmcb_seg fs;
195	struct vmcb_seg gs;
196	struct vmcb_seg gdtr;
197	struct vmcb_seg ldtr;
198	struct vmcb_seg idtr;
199	struct vmcb_seg tr;
200	u8 reserved_1[43];
201	u8 cpl;
202	u8 reserved_2[4];
203	u64 efer;
204	u8 reserved_3[112];
205	u64 cr4;
206	u64 cr3;
207	u64 cr0;
208	u64 dr7;
209	u64 dr6;
210	u64 rflags;
211	u64 rip;
212	u8 reserved_4[88];
213	u64 rsp;
214	u8 reserved_5[24];
215	u64 rax;
216	u64 star;
217	u64 lstar;
218	u64 cstar;
219	u64 sfmask;
220	u64 kernel_gs_base;
221	u64 sysenter_cs;
222	u64 sysenter_esp;
223	u64 sysenter_eip;
224	u64 cr2;
225	u8 reserved_6[32];
226	u64 g_pat;
227	u64 dbgctl;
228	u64 br_from;
229	u64 br_to;
230	u64 last_excp_from;
231	u64 last_excp_to;
232};
233
234struct __attribute__ ((__packed__)) vmcb {
235	struct vmcb_control_area control;
236	struct vmcb_save_area save;
237};
238
239#define SVM_VM_CR_SVM_DISABLE 4
240
241#define SVM_SELECTOR_S_SHIFT 4
242#define SVM_SELECTOR_DPL_SHIFT 5
243#define SVM_SELECTOR_P_SHIFT 7
244#define SVM_SELECTOR_AVL_SHIFT 8
245#define SVM_SELECTOR_L_SHIFT 9
246#define SVM_SELECTOR_DB_SHIFT 10
247#define SVM_SELECTOR_G_SHIFT 11
248
249#define SVM_SELECTOR_TYPE_MASK (0xf)
250#define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
251#define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
252#define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
253#define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
254#define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
255#define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
256#define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
257
258#define SVM_SELECTOR_WRITE_MASK (1 << 1)
259#define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
260#define SVM_SELECTOR_CODE_MASK (1 << 3)
261
262#define INTERCEPT_CR0_READ	0
263#define INTERCEPT_CR3_READ	3
264#define INTERCEPT_CR4_READ	4
265#define INTERCEPT_CR8_READ	8
266#define INTERCEPT_CR0_WRITE	(16 + 0)
267#define INTERCEPT_CR3_WRITE	(16 + 3)
268#define INTERCEPT_CR4_WRITE	(16 + 4)
269#define INTERCEPT_CR8_WRITE	(16 + 8)
270
271#define INTERCEPT_DR0_READ	0
272#define INTERCEPT_DR1_READ	1
273#define INTERCEPT_DR2_READ	2
274#define INTERCEPT_DR3_READ	3
275#define INTERCEPT_DR4_READ	4
276#define INTERCEPT_DR5_READ	5
277#define INTERCEPT_DR6_READ	6
278#define INTERCEPT_DR7_READ	7
279#define INTERCEPT_DR0_WRITE	(16 + 0)
280#define INTERCEPT_DR1_WRITE	(16 + 1)
281#define INTERCEPT_DR2_WRITE	(16 + 2)
282#define INTERCEPT_DR3_WRITE	(16 + 3)
283#define INTERCEPT_DR4_WRITE	(16 + 4)
284#define INTERCEPT_DR5_WRITE	(16 + 5)
285#define INTERCEPT_DR6_WRITE	(16 + 6)
286#define INTERCEPT_DR7_WRITE	(16 + 7)
287
288#define SVM_EVTINJ_VEC_MASK 0xff
289
290#define SVM_EVTINJ_TYPE_SHIFT 8
291#define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
292
293#define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
294#define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
295#define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
296#define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
297
298#define SVM_EVTINJ_VALID (1 << 31)
299#define SVM_EVTINJ_VALID_ERR (1 << 11)
300
301#define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
302#define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
303
304#define	SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
305#define	SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
306#define	SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
307#define	SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
308
309#define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
310#define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
311
312#define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
313#define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
314#define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
315
316#define SVM_EXITINFO_REG_MASK 0x0F
317
318#define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
319
320#endif /* SELFTEST_KVM_SVM_H */