FILE
cache.json
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linux-6.19.14/tools/perf/pmu-events/arch/x86/westmereex/cache.json
1[ 2 { 3 "BriefDescription": "Cycles L1D locked", 4 "Counter": "0,1", 5 "EventCode": "0x63", 6 "EventName": "CACHE_LOCK_CYCLES.L1D", 7 "SampleAfterValue": "2000000", 8 "UMask": "0x2" 9 }, 10 { 11 "BriefDescription": "Cycles L1D and L2 locked", 12 "Counter": "0,1", 13 "EventCode": "0x63", 14 "EventName": "CACHE_LOCK_CYCLES.L1D_L2", 15 "SampleAfterValue": "2000000", 16 "UMask": "0x1" 17 }, 18 { 19 "BriefDescription": "L1D cache lines replaced in M state", 20 "Counter": "0,1", 21 "EventCode": "0x51", 22 "EventName": "L1D.M_EVICT", 23 "SampleAfterValue": "2000000", 24 "UMask": "0x4" 25 }, 26 { 27 "BriefDescription": "L1D cache lines allocated in the M state", 28 "Counter": "0,1", 29 "EventCode": "0x51", 30 "EventName": "L1D.M_REPL", 31 "SampleAfterValue": "2000000", 32 "UMask": "0x2" 33 }, 34 { 35 "BriefDescription": "L1D snoop eviction of cache lines in M state", 36 "Counter": "0,1", 37 "EventCode": "0x51", 38 "EventName": "L1D.M_SNOOP_EVICT", 39 "SampleAfterValue": "2000000", 40 "UMask": "0x8" 41 }, 42 { 43 "BriefDescription": "L1 data cache lines allocated", 44 "Counter": "0,1", 45 "EventCode": "0x51", 46 "EventName": "L1D.REPL", 47 "SampleAfterValue": "2000000", 48 "UMask": "0x1" 49 }, 50 { 51 "BriefDescription": "L1D prefetch load lock accepted in fill buffer", 52 "Counter": "0,1", 53 "EventCode": "0x52", 54 "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", 55 "SampleAfterValue": "2000000", 56 "UMask": "0x1" 57 }, 58 { 59 "BriefDescription": "L1D hardware prefetch misses", 60 "Counter": "0,1", 61 "EventCode": "0x4E", 62 "EventName": "L1D_PREFETCH.MISS", 63 "SampleAfterValue": "200000", 64 "UMask": "0x2" 65 }, 66 { 67 "BriefDescription": "L1D hardware prefetch requests", 68 "Counter": "0,1", 69 "EventCode": "0x4E", 70 "EventName": "L1D_PREFETCH.REQUESTS", 71 "SampleAfterValue": "200000", 72 "UMask": "0x1" 73 }, 74 { 75 "BriefDescription": "L1D hardware prefetch requests triggered", 76 "Counter": "0,1", 77 "EventCode": "0x4E", 78 "EventName": "L1D_PREFETCH.TRIGGERS", 79 "SampleAfterValue": "200000", 80 "UMask": "0x4" 81 }, 82 { 83 "BriefDescription": "L1 writebacks to L2 in E state", 84 "Counter": "0,1,2,3", 85 "EventCode": "0x28", 86 "EventName": "L1D_WB_L2.E_STATE", 87 "SampleAfterValue": "100000", 88 "UMask": "0x4" 89 }, 90 { 91 "BriefDescription": "L1 writebacks to L2 in I state (misses)", 92 "Counter": "0,1,2,3", 93 "EventCode": "0x28", 94 "EventName": "L1D_WB_L2.I_STATE", 95 "SampleAfterValue": "100000", 96 "UMask": "0x1" 97 }, 98 { 99 "BriefDescription": "All L1 writebacks to L2", 100 "Counter": "0,1,2,3", 101 "EventCode": "0x28", 102 "EventName": "L1D_WB_L2.MESI", 103 "SampleAfterValue": "100000", 104 "UMask": "0xf" 105 }, 106 { 107 "BriefDescription": "L1 writebacks to L2 in M state", 108 "Counter": "0,1,2,3", 109 "EventCode": "0x28", 110 "EventName": "L1D_WB_L2.M_STATE", 111 "SampleAfterValue": "100000", 112 "UMask": "0x8" 113 }, 114 { 115 "BriefDescription": "L1 writebacks to L2 in S state", 116 "Counter": "0,1,2,3", 117 "EventCode": "0x28", 118 "EventName": "L1D_WB_L2.S_STATE", 119 "SampleAfterValue": "100000", 120 "UMask": "0x2" 121 }, 122 { 123 "BriefDescription": "L1I instruction fetch stall cycles", 124 "Counter": "0,1,2,3", 125 "EventCode": "0x80", 126 "EventName": "L1I.CYCLES_STALLED", 127 "SampleAfterValue": "2000000", 128 "UMask": "0x4" 129 }, 130 { 131 "BriefDescription": "L1I instruction fetch hits", 132 "Counter": "0,1,2,3", 133 "EventCode": "0x80", 134 "EventName": "L1I.HITS", 135 "SampleAfterValue": "2000000", 136 "UMask": "0x1" 137 }, 138 { 139 "BriefDescription": "L1I instruction fetch misses", 140 "Counter": "0,1,2,3", 141 "EventCode": "0x80", 142 "EventName": "L1I.MISSES", 143 "SampleAfterValue": "2000000", 144 "UMask": "0x2" 145 }, 146 { 147 "BriefDescription": "L1I Instruction fetches", 148 "Counter": "0,1,2,3", 149 "EventCode": "0x80", 150 "EventName": "L1I.READS", 151 "SampleAfterValue": "2000000", 152 "UMask": "0x3" 153 }, 154 { 155 "BriefDescription": "All L2 data requests", 156 "Counter": "0,1,2,3", 157 "EventCode": "0x26", 158 "EventName": "L2_DATA_RQSTS.ANY", 159 "SampleAfterValue": "200000", 160 "UMask": "0xff" 161 }, 162 { 163 "BriefDescription": "L2 data demand loads in E state", 164 "Counter": "0,1,2,3", 165 "EventCode": "0x26", 166 "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", 167 "SampleAfterValue": "200000", 168 "UMask": "0x4" 169 }, 170 { 171 "BriefDescription": "L2 data demand loads in I state (misses)", 172 "Counter": "0,1,2,3", 173 "EventCode": "0x26", 174 "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", 175 "SampleAfterValue": "200000", 176 "UMask": "0x1" 177 }, 178 { 179 "BriefDescription": "L2 data demand requests", 180 "Counter": "0,1,2,3", 181 "EventCode": "0x26", 182 "EventName": "L2_DATA_RQSTS.DEMAND.MESI", 183 "SampleAfterValue": "200000", 184 "UMask": "0xf" 185 }, 186 { 187 "BriefDescription": "L2 data demand loads in M state", 188 "Counter": "0,1,2,3", 189 "EventCode": "0x26", 190 "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", 191 "SampleAfterValue": "200000", 192 "UMask": "0x8" 193 }, 194 { 195 "BriefDescription": "L2 data demand loads in S state", 196 "Counter": "0,1,2,3", 197 "EventCode": "0x26", 198 "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", 199 "SampleAfterValue": "200000", 200 "UMask": "0x2" 201 }, 202 { 203 "BriefDescription": "L2 data prefetches in E state", 204 "Counter": "0,1,2,3", 205 "EventCode": "0x26", 206 "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", 207 "SampleAfterValue": "200000", 208 "UMask": "0x40" 209 }, 210 { 211 "BriefDescription": "L2 data prefetches in the I state (misses)", 212 "Counter": "0,1,2,3", 213 "EventCode": "0x26", 214 "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", 215 "SampleAfterValue": "200000", 216 "UMask": "0x10" 217 }, 218 { 219 "BriefDescription": "All L2 data prefetches", 220 "Counter": "0,1,2,3", 221 "EventCode": "0x26", 222 "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", 223 "SampleAfterValue": "200000", 224 "UMask": "0xf0" 225 }, 226 { 227 "BriefDescription": "L2 data prefetches in M state", 228 "Counter": "0,1,2,3", 229 "EventCode": "0x26", 230 "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", 231 "SampleAfterValue": "200000", 232 "UMask": "0x80" 233 }, 234 { 235 "BriefDescription": "L2 data prefetches in the S state", 236 "Counter": "0,1,2,3", 237 "EventCode": "0x26", 238 "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", 239 "SampleAfterValue": "200000", 240 "UMask": "0x20" 241 }, 242 { 243 "BriefDescription": "L2 lines allocated", 244 "Counter": "0,1,2,3", 245 "EventCode": "0xF1", 246 "EventName": "L2_LINES_IN.ANY", 247 "SampleAfterValue": "100000", 248 "UMask": "0x7" 249 }, 250 { 251 "BriefDescription": "L2 lines allocated in the E state", 252 "Counter": "0,1,2,3", 253 "EventCode": "0xF1", 254 "EventName": "L2_LINES_IN.E_STATE", 255 "SampleAfterValue": "100000", 256 "UMask": "0x4" 257 }, 258 { 259 "BriefDescription": "L2 lines allocated in the S state", 260 "Counter": "0,1,2,3", 261 "EventCode": "0xF1", 262 "EventName": "L2_LINES_IN.S_STATE", 263 "SampleAfterValue": "100000", 264 "UMask": "0x2" 265 }, 266 { 267 "BriefDescription": "L2 lines evicted", 268 "Counter": "0,1,2,3", 269 "EventCode": "0xF2", 270 "EventName": "L2_LINES_OUT.ANY", 271 "SampleAfterValue": "100000", 272 "UMask": "0xf" 273 }, 274 { 275 "BriefDescription": "L2 lines evicted by a demand request", 276 "Counter": "0,1,2,3", 277 "EventCode": "0xF2", 278 "EventName": "L2_LINES_OUT.DEMAND_CLEAN", 279 "SampleAfterValue": "100000", 280 "UMask": "0x1" 281 }, 282 { 283 "BriefDescription": "L2 modified lines evicted by a demand request", 284 "Counter": "0,1,2,3", 285 "EventCode": "0xF2", 286 "EventName": "L2_LINES_OUT.DEMAND_DIRTY", 287 "SampleAfterValue": "100000", 288 "UMask": "0x2" 289 }, 290 { 291 "BriefDescription": "L2 lines evicted by a prefetch request", 292 "Counter": "0,1,2,3", 293 "EventCode": "0xF2", 294 "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", 295 "SampleAfterValue": "100000", 296 "UMask": "0x4" 297 }, 298 { 299 "BriefDescription": "L2 modified lines evicted by a prefetch request", 300 "Counter": "0,1,2,3", 301 "EventCode": "0xF2", 302 "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", 303 "SampleAfterValue": "100000", 304 "UMask": "0x8" 305 }, 306 { 307 "BriefDescription": "L2 instruction fetches", 308 "Counter": "0,1,2,3", 309 "EventCode": "0x24", 310 "EventName": "L2_RQSTS.IFETCHES", 311 "SampleAfterValue": "200000", 312 "UMask": "0x30" 313 }, 314 { 315 "BriefDescription": "L2 instruction fetch hits", 316 "Counter": "0,1,2,3", 317 "EventCode": "0x24", 318 "EventName": "L2_RQSTS.IFETCH_HIT", 319 "SampleAfterValue": "200000", 320 "UMask": "0x10" 321 }, 322 { 323 "BriefDescription": "L2 instruction fetch misses", 324 "Counter": "0,1,2,3", 325 "EventCode": "0x24", 326 "EventName": "L2_RQSTS.IFETCH_MISS", 327 "SampleAfterValue": "200000", 328 "UMask": "0x20" 329 }, 330 { 331 "BriefDescription": "L2 load hits", 332 "Counter": "0,1,2,3", 333 "EventCode": "0x24", 334 "EventName": "L2_RQSTS.LD_HIT", 335 "SampleAfterValue": "200000", 336 "UMask": "0x1" 337 }, 338 { 339 "BriefDescription": "L2 load misses", 340 "Counter": "0,1,2,3", 341 "EventCode": "0x24", 342 "EventName": "L2_RQSTS.LD_MISS", 343 "SampleAfterValue": "200000", 344 "UMask": "0x2" 345 }, 346 { 347 "BriefDescription": "L2 requests", 348 "Counter": "0,1,2,3", 349 "EventCode": "0x24", 350 "EventName": "L2_RQSTS.LOADS", 351 "SampleAfterValue": "200000", 352 "UMask": "0x3" 353 }, 354 { 355 "BriefDescription": "All L2 misses", 356 "Counter": "0,1,2,3", 357 "EventCode": "0x24", 358 "EventName": "L2_RQSTS.MISS", 359 "SampleAfterValue": "200000", 360 "UMask": "0xaa" 361 }, 362 { 363 "BriefDescription": "All L2 prefetches", 364 "Counter": "0,1,2,3", 365 "EventCode": "0x24", 366 "EventName": "L2_RQSTS.PREFETCHES", 367 "SampleAfterValue": "200000", 368 "UMask": "0xc0" 369 }, 370 { 371 "BriefDescription": "L2 prefetch hits", 372 "Counter": "0,1,2,3", 373 "EventCode": "0x24", 374 "EventName": "L2_RQSTS.PREFETCH_HIT", 375 "SampleAfterValue": "200000", 376 "UMask": "0x40" 377 }, 378 { 379 "BriefDescription": "L2 prefetch misses", 380 "Counter": "0,1,2,3", 381 "EventCode": "0x24", 382 "EventName": "L2_RQSTS.PREFETCH_MISS", 383 "SampleAfterValue": "200000", 384 "UMask": "0x80" 385 }, 386 { 387 "BriefDescription": "All L2 requests", 388 "Counter": "0,1,2,3", 389 "EventCode": "0x24", 390 "EventName": "L2_RQSTS.REFERENCES", 391 "SampleAfterValue": "200000", 392 "UMask": "0xff" 393 }, 394 { 395 "BriefDescription": "L2 RFO requests", 396 "Counter": "0,1,2,3", 397 "EventCode": "0x24", 398 "EventName": "L2_RQSTS.RFOS", 399 "SampleAfterValue": "200000", 400 "UMask": "0xc" 401 }, 402 { 403 "BriefDescription": "L2 RFO hits", 404 "Counter": "0,1,2,3", 405 "EventCode": "0x24", 406 "EventName": "L2_RQSTS.RFO_HIT", 407 "SampleAfterValue": "200000", 408 "UMask": "0x4" 409 }, 410 { 411 "BriefDescription": "L2 RFO misses", 412 "Counter": "0,1,2,3", 413 "EventCode": "0x24", 414 "EventName": "L2_RQSTS.RFO_MISS", 415 "SampleAfterValue": "200000", 416 "UMask": "0x8" 417 }, 418 { 419 "BriefDescription": "All L2 transactions", 420 "Counter": "0,1,2,3", 421 "EventCode": "0xF0", 422 "EventName": "L2_TRANSACTIONS.ANY", 423 "SampleAfterValue": "200000", 424 "UMask": "0x80" 425 }, 426 { 427 "BriefDescription": "L2 fill transactions", 428 "Counter": "0,1,2,3", 429 "EventCode": "0xF0", 430 "EventName": "L2_TRANSACTIONS.FILL", 431 "SampleAfterValue": "200000", 432 "UMask": "0x20" 433 }, 434 { 435 "BriefDescription": "L2 instruction fetch transactions", 436 "Counter": "0,1,2,3", 437 "EventCode": "0xF0", 438 "EventName": "L2_TRANSACTIONS.IFETCH", 439 "SampleAfterValue": "200000", 440 "UMask": "0x4" 441 }, 442 { 443 "BriefDescription": "L1D writeback to L2 transactions", 444 "Counter": "0,1,2,3", 445 "EventCode": "0xF0", 446 "EventName": "L2_TRANSACTIONS.L1D_WB", 447 "SampleAfterValue": "200000", 448 "UMask": "0x10" 449 }, 450 { 451 "BriefDescription": "L2 Load transactions", 452 "Counter": "0,1,2,3", 453 "EventCode": "0xF0", 454 "EventName": "L2_TRANSACTIONS.LOAD", 455 "SampleAfterValue": "200000", 456 "UMask": "0x1" 457 }, 458 { 459 "BriefDescription": "L2 prefetch transactions", 460 "Counter": "0,1,2,3", 461 "EventCode": "0xF0", 462 "EventName": "L2_TRANSACTIONS.PREFETCH", 463 "SampleAfterValue": "200000", 464 "UMask": "0x8" 465 }, 466 { 467 "BriefDescription": "L2 RFO transactions", 468 "Counter": "0,1,2,3", 469 "EventCode": "0xF0", 470 "EventName": "L2_TRANSACTIONS.RFO", 471 "SampleAfterValue": "200000", 472 "UMask": "0x2" 473 }, 474 { 475 "BriefDescription": "L2 writeback to LLC transactions", 476 "Counter": "0,1,2,3", 477 "EventCode": "0xF0", 478 "EventName": "L2_TRANSACTIONS.WB", 479 "SampleAfterValue": "200000", 480 "UMask": "0x40" 481 }, 482 { 483 "BriefDescription": "L2 demand lock RFOs in E state", 484 "Counter": "0,1,2,3", 485 "EventCode": "0x27", 486 "EventName": "L2_WRITE.LOCK.E_STATE", 487 "SampleAfterValue": "100000", 488 "UMask": "0x40" 489 }, 490 { 491 "BriefDescription": "All demand L2 lock RFOs that hit the cache", 492 "Counter": "0,1,2,3", 493 "EventCode": "0x27", 494 "EventName": "L2_WRITE.LOCK.HIT", 495 "SampleAfterValue": "100000", 496 "UMask": "0xe0" 497 }, 498 { 499 "BriefDescription": "L2 demand lock RFOs in I state (misses)", 500 "Counter": "0,1,2,3", 501 "EventCode": "0x27", 502 "EventName": "L2_WRITE.LOCK.I_STATE", 503 "SampleAfterValue": "100000", 504 "UMask": "0x10" 505 }, 506 { 507 "BriefDescription": "All demand L2 lock RFOs", 508 "Counter": "0,1,2,3", 509 "EventCode": "0x27", 510 "EventName": "L2_WRITE.LOCK.MESI", 511 "SampleAfterValue": "100000", 512 "UMask": "0xf0" 513 }, 514 { 515 "BriefDescription": "L2 demand lock RFOs in M state", 516 "Counter": "0,1,2,3", 517 "EventCode": "0x27", 518 "EventName": "L2_WRITE.LOCK.M_STATE", 519 "SampleAfterValue": "100000", 520 "UMask": "0x80" 521 }, 522 { 523 "BriefDescription": "L2 demand lock RFOs in S state", 524 "Counter": "0,1,2,3", 525 "EventCode": "0x27", 526 "EventName": "L2_WRITE.LOCK.S_STATE", 527 "SampleAfterValue": "100000", 528 "UMask": "0x20" 529 }, 530 { 531 "BriefDescription": "All L2 demand store RFOs that hit the cache", 532 "Counter": "0,1,2,3", 533 "EventCode": "0x27", 534 "EventName": "L2_WRITE.RFO.HIT", 535 "SampleAfterValue": "100000", 536 "UMask": "0xe" 537 }, 538 { 539 "BriefDescription": "L2 demand store RFOs in I state (misses)", 540 "Counter": "0,1,2,3", 541 "EventCode": "0x27", 542 "EventName": "L2_WRITE.RFO.I_STATE", 543 "SampleAfterValue": "100000", 544 "UMask": "0x1" 545 }, 546 { 547 "BriefDescription": "All L2 demand store RFOs", 548 "Counter": "0,1,2,3", 549 "EventCode": "0x27", 550 "EventName": "L2_WRITE.RFO.MESI", 551 "SampleAfterValue": "100000", 552 "UMask": "0xf" 553 }, 554 { 555 "BriefDescription": "L2 demand store RFOs in M state", 556 "Counter": "0,1,2,3", 557 "EventCode": "0x27", 558 "EventName": "L2_WRITE.RFO.M_STATE", 559 "SampleAfterValue": "100000", 560 "UMask": "0x8" 561 }, 562 { 563 "BriefDescription": "L2 demand store RFOs in S state", 564 "Counter": "0,1,2,3", 565 "EventCode": "0x27", 566 "EventName": "L2_WRITE.RFO.S_STATE", 567 "SampleAfterValue": "100000", 568 "UMask": "0x2" 569 }, 570 { 571 "BriefDescription": "Longest latency cache miss", 572 "Counter": "0,1,2,3", 573 "EventCode": "0x2E", 574 "EventName": "LONGEST_LAT_CACHE.MISS", 575 "SampleAfterValue": "100000", 576 "UMask": "0x41" 577 }, 578 { 579 "BriefDescription": "Longest latency cache reference", 580 "Counter": "0,1,2,3", 581 "EventCode": "0x2E", 582 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 583 "SampleAfterValue": "200000", 584 "UMask": "0x4f" 585 }, 586 { 587 "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)", 588 "Counter": "3", 589 "EventCode": "0xB", 590 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", 591 "MSRIndex": "0x3F6", 592 "PEBS": "2", 593 "SampleAfterValue": "2000000", 594 "UMask": "0x10" 595 }, 596 { 597 "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)", 598 "Counter": "3", 599 "EventCode": "0xB", 600 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", 601 "MSRIndex": "0x3F6", 602 "MSRValue": "0x400", 603 "PEBS": "2", 604 "SampleAfterValue": "100", 605 "UMask": "0x10" 606 }, 607 { 608 "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)", 609 "Counter": "3", 610 "EventCode": "0xB", 611 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", 612 "MSRIndex": "0x3F6", 613 "MSRValue": "0x80", 614 "PEBS": "2", 615 "SampleAfterValue": "1000", 616 "UMask": "0x10" 617 }, 618 { 619 "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)", 620 "Counter": "3", 621 "EventCode": "0xB", 622 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", 623 "MSRIndex": "0x3F6", 624 "MSRValue": "0x10", 625 "PEBS": "2", 626 "SampleAfterValue": "10000", 627 "UMask": "0x10" 628 }, 629 { 630 "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)", 631 "Counter": "3", 632 "EventCode": "0xB", 633 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", 634 "MSRIndex": "0x3F6", 635 "MSRValue": "0x4000", 636 "PEBS": "2", 637 "SampleAfterValue": "5", 638 "UMask": "0x10" 639 }, 640 { 641 "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)", 642 "Counter": "3", 643 "EventCode": "0xB", 644 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", 645 "MSRIndex": "0x3F6", 646 "MSRValue": "0x800", 647 "PEBS": "2", 648 "SampleAfterValue": "50", 649 "UMask": "0x10" 650 }, 651 { 652 "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)", 653 "Counter": "3", 654 "EventCode": "0xB", 655 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", 656 "MSRIndex": "0x3F6", 657 "MSRValue": "0x100", 658 "PEBS": "2", 659 "SampleAfterValue": "500", 660 "UMask": "0x10" 661 }, 662 { 663 "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)", 664 "Counter": "3", 665 "EventCode": "0xB", 666 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", 667 "MSRIndex": "0x3F6", 668 "MSRValue": "0x20", 669 "PEBS": "2", 670 "SampleAfterValue": "5000", 671 "UMask": "0x10" 672 }, 673 { 674 "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)", 675 "Counter": "3", 676 "EventCode": "0xB", 677 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", 678 "MSRIndex": "0x3F6", 679 "MSRValue": "0x8000", 680 "PEBS": "2", 681 "SampleAfterValue": "3", 682 "UMask": "0x10" 683 }, 684 { 685 "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)", 686 "Counter": "3", 687 "EventCode": "0xB", 688 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", 689 "MSRIndex": "0x3F6", 690 "MSRValue": "0x4", 691 "PEBS": "2", 692 "SampleAfterValue": "50000", 693 "UMask": "0x10" 694 }, 695 { 696 "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)", 697 "Counter": "3", 698 "EventCode": "0xB", 699 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", 700 "MSRIndex": "0x3F6", 701 "MSRValue": "0x1000", 702 "PEBS": "2", 703 "SampleAfterValue": "20", 704 "UMask": "0x10" 705 }, 706 { 707 "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)", 708 "Counter": "3", 709 "EventCode": "0xB", 710 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", 711 "MSRIndex": "0x3F6", 712 "MSRValue": "0x200", 713 "PEBS": "2", 714 "SampleAfterValue": "200", 715 "UMask": "0x10" 716 }, 717 { 718 "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)", 719 "Counter": "3", 720 "EventCode": "0xB", 721 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", 722 "MSRIndex": "0x3F6", 723 "MSRValue": "0x40", 724 "PEBS": "2", 725 "SampleAfterValue": "2000", 726 "UMask": "0x10" 727 }, 728 { 729 "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)", 730 "Counter": "3", 731 "EventCode": "0xB", 732 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", 733 "MSRIndex": "0x3F6", 734 "MSRValue": "0x8", 735 "PEBS": "2", 736 "SampleAfterValue": "20000", 737 "UMask": "0x10" 738 }, 739 { 740 "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)", 741 "Counter": "3", 742 "EventCode": "0xB", 743 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", 744 "MSRIndex": "0x3F6", 745 "MSRValue": "0x2000", 746 "PEBS": "2", 747 "SampleAfterValue": "10", 748 "UMask": "0x10" 749 }, 750 { 751 "BriefDescription": "Instructions retired which contains a load (Precise Event)", 752 "Counter": "0,1,2,3", 753 "EventCode": "0xB", 754 "EventName": "MEM_INST_RETIRED.LOADS", 755 "PEBS": "1", 756 "SampleAfterValue": "2000000", 757 "UMask": "0x1" 758 }, 759 { 760 "BriefDescription": "Instructions retired which contains a store (Precise Event)", 761 "Counter": "0,1,2,3", 762 "EventCode": "0xB", 763 "EventName": "MEM_INST_RETIRED.STORES", 764 "PEBS": "1", 765 "SampleAfterValue": "2000000", 766 "UMask": "0x2" 767 }, 768 { 769 "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)", 770 "Counter": "0,1,2,3", 771 "EventCode": "0xCB", 772 "EventName": "MEM_LOAD_RETIRED.HIT_LFB", 773 "PEBS": "1", 774 "SampleAfterValue": "200000", 775 "UMask": "0x40" 776 }, 777 { 778 "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)", 779 "Counter": "0,1,2,3", 780 "EventCode": "0xCB", 781 "EventName": "MEM_LOAD_RETIRED.L1D_HIT", 782 "PEBS": "1", 783 "SampleAfterValue": "2000000", 784 "UMask": "0x1" 785 }, 786 { 787 "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)", 788 "Counter": "0,1,2,3", 789 "EventCode": "0xCB", 790 "EventName": "MEM_LOAD_RETIRED.L2_HIT", 791 "PEBS": "1", 792 "SampleAfterValue": "200000", 793 "UMask": "0x2" 794 }, 795 { 796 "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)", 797 "Counter": "0,1,2,3", 798 "EventCode": "0xCB", 799 "EventName": "MEM_LOAD_RETIRED.LLC_MISS", 800 "PEBS": "1", 801 "SampleAfterValue": "10000", 802 "UMask": "0x10" 803 }, 804 { 805 "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)", 806 "Counter": "0,1,2,3", 807 "EventCode": "0xCB", 808 "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", 809 "PEBS": "1", 810 "SampleAfterValue": "40000", 811 "UMask": "0x4" 812 }, 813 { 814 "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)", 815 "Counter": "0,1,2,3", 816 "EventCode": "0xCB", 817 "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", 818 "PEBS": "1", 819 "SampleAfterValue": "40000", 820 "UMask": "0x8" 821 }, 822 { 823 "BriefDescription": "Load instructions retired local dram and remote cache HIT data sources (Precise Event)", 824 "Counter": "0,1,2,3", 825 "EventCode": "0xF", 826 "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 827 "PEBS": "1", 828 "SampleAfterValue": "20000", 829 "UMask": "0x8" 830 }, 831 { 832 "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)", 833 "Counter": "0,1,2,3", 834 "EventCode": "0xF", 835 "EventName": "MEM_UNCORE_RETIRED.LOCAL_HITM", 836 "PEBS": "1", 837 "SampleAfterValue": "40000", 838 "UMask": "0x2" 839 }, 840 { 841 "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)", 842 "Counter": "0,1,2,3", 843 "EventCode": "0xF", 844 "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", 845 "PEBS": "1", 846 "SampleAfterValue": "10000", 847 "UMask": "0x20" 848 }, 849 { 850 "BriefDescription": "Retired loads that hit remote socket in modified state (Precise Event)", 851 "Counter": "0,1,2,3", 852 "EventCode": "0xF", 853 "EventName": "MEM_UNCORE_RETIRED.REMOTE_HITM", 854 "PEBS": "1", 855 "SampleAfterValue": "40000", 856 "UMask": "0x4" 857 }, 858 { 859 "BriefDescription": "Load instructions retired IO (Precise Event)", 860 "Counter": "0,1,2,3", 861 "EventCode": "0xF", 862 "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", 863 "PEBS": "1", 864 "SampleAfterValue": "4000", 865 "UMask": "0x80" 866 }, 867 { 868 "BriefDescription": "All offcore requests", 869 "Counter": "0,1,2,3", 870 "EventCode": "0xB0", 871 "EventName": "OFFCORE_REQUESTS.ANY", 872 "SampleAfterValue": "100000", 873 "UMask": "0x80" 874 }, 875 { 876 "BriefDescription": "Offcore read requests", 877 "Counter": "0,1,2,3", 878 "EventCode": "0xB0", 879 "EventName": "OFFCORE_REQUESTS.ANY.READ", 880 "SampleAfterValue": "100000", 881 "UMask": "0x8" 882 }, 883 { 884 "BriefDescription": "Offcore RFO requests", 885 "Counter": "0,1,2,3", 886 "EventCode": "0xB0", 887 "EventName": "OFFCORE_REQUESTS.ANY.RFO", 888 "SampleAfterValue": "100000", 889 "UMask": "0x10" 890 }, 891 { 892 "BriefDescription": "Offcore demand code read requests", 893 "Counter": "0,1,2,3", 894 "EventCode": "0xB0", 895 "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE", 896 "SampleAfterValue": "100000", 897 "UMask": "0x2" 898 }, 899 { 900 "BriefDescription": "Offcore demand data read requests", 901 "Counter": "0,1,2,3", 902 "EventCode": "0xB0", 903 "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA", 904 "SampleAfterValue": "100000", 905 "UMask": "0x1" 906 }, 907 { 908 "BriefDescription": "Offcore demand RFO requests", 909 "Counter": "0,1,2,3", 910 "EventCode": "0xB0", 911 "EventName": "OFFCORE_REQUESTS.DEMAND.RFO", 912 "SampleAfterValue": "100000", 913 "UMask": "0x4" 914 }, 915 { 916 "BriefDescription": "Offcore L1 data cache writebacks", 917 "Counter": "0,1,2,3", 918 "EventCode": "0xB0", 919 "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", 920 "SampleAfterValue": "100000", 921 "UMask": "0x40" 922 }, 923 { 924 "BriefDescription": "Outstanding offcore reads", 925 "Counter": "0", 926 "EventCode": "0x60", 927 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", 928 "SampleAfterValue": "2000000", 929 "UMask": "0x8" 930 }, 931 { 932 "BriefDescription": "Cycles offcore reads busy", 933 "Counter": "0", 934 "CounterMask": "1", 935 "EventCode": "0x60", 936 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY", 937 "SampleAfterValue": "2000000", 938 "UMask": "0x8" 939 }, 940 { 941 "BriefDescription": "Outstanding offcore demand code reads", 942 "Counter": "0", 943 "EventCode": "0x60", 944 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", 945 "SampleAfterValue": "2000000", 946 "UMask": "0x2" 947 }, 948 { 949 "BriefDescription": "Cycles offcore demand code read busy", 950 "Counter": "0", 951 "CounterMask": "1", 952 "EventCode": "0x60", 953 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY", 954 "SampleAfterValue": "2000000", 955 "UMask": "0x2" 956 }, 957 { 958 "BriefDescription": "Outstanding offcore demand data reads", 959 "Counter": "0", 960 "EventCode": "0x60", 961 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", 962 "SampleAfterValue": "2000000", 963 "UMask": "0x1" 964 }, 965 { 966 "BriefDescription": "Cycles offcore demand data read busy", 967 "Counter": "0", 968 "CounterMask": "1", 969 "EventCode": "0x60", 970 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY", 971 "SampleAfterValue": "2000000", 972 "UMask": "0x1" 973 }, 974 { 975 "BriefDescription": "Outstanding offcore demand RFOs", 976 "Counter": "0", 977 "EventCode": "0x60", 978 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", 979 "SampleAfterValue": "2000000", 980 "UMask": "0x4" 981 }, 982 { 983 "BriefDescription": "Cycles offcore demand RFOs busy", 984 "Counter": "0", 985 "CounterMask": "1", 986 "EventCode": "0x60", 987 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", 988 "SampleAfterValue": "2000000", 989 "UMask": "0x4" 990 }, 991 { 992 "BriefDescription": "Offcore requests blocked due to Super Queue full", 993 "Counter": "0,1,2,3", 994 "EventCode": "0xB2", 995 "EventName": "OFFCORE_REQUESTS_SQ_FULL", 996 "SampleAfterValue": "100000", 997 "UMask": "0x1" 998 }, 999 { 1000 "BriefDescription": "Offcore data reads satisfied by any cache or DRAM", 1001 "Counter": "2", 1002 "EventCode": "0xB7", 1003 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", 1004 "MSRIndex": "0x1A6", 1005 "MSRValue": "0x7F11", 1006 "SampleAfterValue": "100000", 1007 "UMask": "0x1" 1008 }, 1009 { 1010 "BriefDescription": "All offcore data reads", 1011 "Counter": "2", 1012 "EventCode": "0xB7", 1013 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", 1014 "MSRIndex": "0x1A6", 1015 "MSRValue": "0xFF11", 1016 "SampleAfterValue": "100000", 1017 "UMask": "0x1" 1018 }, 1019 { 1020 "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", 1021 "Counter": "2", 1022 "EventCode": "0xB7", 1023 "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", 1024 "MSRIndex": "0x1A6", 1025 "MSRValue": "0x8011", 1026 "SampleAfterValue": "100000", 1027 "UMask": "0x1" 1028 }, 1029 { 1030 "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", 1031 "Counter": "2", 1032 "EventCode": "0xB7", 1033 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", 1034 "MSRIndex": "0x1A6", 1035 "MSRValue": "0x111", 1036 "SampleAfterValue": "100000", 1037 "UMask": "0x1" 1038 }, 1039 { 1040 "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", 1041 "Counter": "2", 1042 "EventCode": "0xB7", 1043 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", 1044 "MSRIndex": "0x1A6", 1045 "MSRValue": "0x211", 1046 "SampleAfterValue": "100000", 1047 "UMask": "0x1" 1048 }, 1049 { 1050 "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", 1051 "Counter": "2", 1052 "EventCode": "0xB7", 1053 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", 1054 "MSRIndex": "0x1A6", 1055 "MSRValue": "0x411", 1056 "SampleAfterValue": "100000", 1057 "UMask": "0x1" 1058 }, 1059 { 1060 "BriefDescription": "Offcore data reads satisfied by the LLC", 1061 "Counter": "2", 1062 "EventCode": "0xB7", 1063 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", 1064 "MSRIndex": "0x1A6", 1065 "MSRValue": "0x711", 1066 "SampleAfterValue": "100000", 1067 "UMask": "0x1" 1068 }, 1069 { 1070 "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM", 1071 "Counter": "2", 1072 "EventCode": "0xB7", 1073 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", 1074 "MSRIndex": "0x1A6", 1075 "MSRValue": "0x4711", 1076 "SampleAfterValue": "100000", 1077 "UMask": "0x1" 1078 }, 1079 { 1080 "BriefDescription": "Offcore data reads satisfied by a remote cache", 1081 "Counter": "2", 1082 "EventCode": "0xB7", 1083 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", 1084 "MSRIndex": "0x1A6", 1085 "MSRValue": "0x1811", 1086 "SampleAfterValue": "100000", 1087 "UMask": "0x1" 1088 }, 1089 { 1090 "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", 1091 "Counter": "2", 1092 "EventCode": "0xB7", 1093 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", 1094 "MSRIndex": "0x1A6", 1095 "MSRValue": "0x3811", 1096 "SampleAfterValue": "100000", 1097 "UMask": "0x1" 1098 }, 1099 { 1100 "BriefDescription": "Offcore data reads that HIT in a remote cache", 1101 "Counter": "2", 1102 "EventCode": "0xB7", 1103 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", 1104 "MSRIndex": "0x1A6", 1105 "MSRValue": "0x1011", 1106 "SampleAfterValue": "100000", 1107 "UMask": "0x1" 1108 }, 1109 { 1110 "BriefDescription": "Offcore data reads that HITM in a remote cache", 1111 "Counter": "2", 1112 "EventCode": "0xB7", 1113 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", 1114 "MSRIndex": "0x1A6", 1115 "MSRValue": "0x811", 1116 "SampleAfterValue": "100000", 1117 "UMask": "0x1" 1118 }, 1119 { 1120 "BriefDescription": "Offcore code reads satisfied by any cache or DRAM", 1121 "Counter": "2", 1122 "EventCode": "0xB7", 1123 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", 1124 "MSRIndex": "0x1A6", 1125 "MSRValue": "0x7F44", 1126 "SampleAfterValue": "100000", 1127 "UMask": "0x1" 1128 }, 1129 { 1130 "BriefDescription": "All offcore code reads", 1131 "Counter": "2", 1132 "EventCode": "0xB7", 1133 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", 1134 "MSRIndex": "0x1A6", 1135 "MSRValue": "0xFF44", 1136 "SampleAfterValue": "100000", 1137 "UMask": "0x1" 1138 }, 1139 { 1140 "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", 1141 "Counter": "2", 1142 "EventCode": "0xB7", 1143 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", 1144 "MSRIndex": "0x1A6", 1145 "MSRValue": "0x8044", 1146 "SampleAfterValue": "100000", 1147 "UMask": "0x1" 1148 }, 1149 { 1150 "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", 1151 "Counter": "2", 1152 "EventCode": "0xB7", 1153 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", 1154 "MSRIndex": "0x1A6", 1155 "MSRValue": "0x144", 1156 "SampleAfterValue": "100000", 1157 "UMask": "0x1" 1158 }, 1159 { 1160 "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", 1161 "Counter": "2", 1162 "EventCode": "0xB7", 1163 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1164 "MSRIndex": "0x1A6", 1165 "MSRValue": "0x244", 1166 "SampleAfterValue": "100000", 1167 "UMask": "0x1" 1168 }, 1169 { 1170 "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", 1171 "Counter": "2", 1172 "EventCode": "0xB7", 1173 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1174 "MSRIndex": "0x1A6", 1175 "MSRValue": "0x444", 1176 "SampleAfterValue": "100000", 1177 "UMask": "0x1" 1178 }, 1179 { 1180 "BriefDescription": "Offcore code reads satisfied by the LLC", 1181 "Counter": "2", 1182 "EventCode": "0xB7", 1183 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", 1184 "MSRIndex": "0x1A6", 1185 "MSRValue": "0x744", 1186 "SampleAfterValue": "100000", 1187 "UMask": "0x1" 1188 }, 1189 { 1190 "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM", 1191 "Counter": "2", 1192 "EventCode": "0xB7", 1193 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", 1194 "MSRIndex": "0x1A6", 1195 "MSRValue": "0x4744", 1196 "SampleAfterValue": "100000", 1197 "UMask": "0x1" 1198 }, 1199 { 1200 "BriefDescription": "Offcore code reads satisfied by a remote cache", 1201 "Counter": "2", 1202 "EventCode": "0xB7", 1203 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", 1204 "MSRIndex": "0x1A6", 1205 "MSRValue": "0x1844", 1206 "SampleAfterValue": "100000", 1207 "UMask": "0x1" 1208 }, 1209 { 1210 "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", 1211 "Counter": "2", 1212 "EventCode": "0xB7", 1213 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", 1214 "MSRIndex": "0x1A6", 1215 "MSRValue": "0x3844", 1216 "SampleAfterValue": "100000", 1217 "UMask": "0x1" 1218 }, 1219 { 1220 "BriefDescription": "Offcore code reads that HIT in a remote cache", 1221 "Counter": "2", 1222 "EventCode": "0xB7", 1223 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", 1224 "MSRIndex": "0x1A6", 1225 "MSRValue": "0x1044", 1226 "SampleAfterValue": "100000", 1227 "UMask": "0x1" 1228 }, 1229 { 1230 "BriefDescription": "Offcore code reads that HITM in a remote cache", 1231 "Counter": "2", 1232 "EventCode": "0xB7", 1233 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", 1234 "MSRIndex": "0x1A6", 1235 "MSRValue": "0x844", 1236 "SampleAfterValue": "100000", 1237 "UMask": "0x1" 1238 }, 1239 { 1240 "BriefDescription": "Offcore requests satisfied by any cache or DRAM", 1241 "Counter": "2", 1242 "EventCode": "0xB7", 1243 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", 1244 "MSRIndex": "0x1A6", 1245 "MSRValue": "0x7FFF", 1246 "SampleAfterValue": "100000", 1247 "UMask": "0x1" 1248 }, 1249 { 1250 "BriefDescription": "All offcore requests", 1251 "Counter": "2", 1252 "EventCode": "0xB7", 1253 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", 1254 "MSRIndex": "0x1A6", 1255 "MSRValue": "0xFFFF", 1256 "SampleAfterValue": "100000", 1257 "UMask": "0x1" 1258 }, 1259 { 1260 "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", 1261 "Counter": "2", 1262 "EventCode": "0xB7", 1263 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", 1264 "MSRIndex": "0x1A6", 1265 "MSRValue": "0x80FF", 1266 "SampleAfterValue": "100000", 1267 "UMask": "0x1" 1268 }, 1269 { 1270 "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", 1271 "Counter": "2", 1272 "EventCode": "0xB7", 1273 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", 1274 "MSRIndex": "0x1A6", 1275 "MSRValue": "0x1FF", 1276 "SampleAfterValue": "100000", 1277 "UMask": "0x1" 1278 }, 1279 { 1280 "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", 1281 "Counter": "2", 1282 "EventCode": "0xB7", 1283 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", 1284 "MSRIndex": "0x1A6", 1285 "MSRValue": "0x2FF", 1286 "SampleAfterValue": "100000", 1287 "UMask": "0x1" 1288 }, 1289 { 1290 "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", 1291 "Counter": "2", 1292 "EventCode": "0xB7", 1293 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", 1294 "MSRIndex": "0x1A6", 1295 "MSRValue": "0x4FF", 1296 "SampleAfterValue": "100000", 1297 "UMask": "0x1" 1298 }, 1299 { 1300 "BriefDescription": "Offcore requests satisfied by the LLC", 1301 "Counter": "2", 1302 "EventCode": "0xB7", 1303 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", 1304 "MSRIndex": "0x1A6", 1305 "MSRValue": "0x7FF", 1306 "SampleAfterValue": "100000", 1307 "UMask": "0x1" 1308 }, 1309 { 1310 "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM", 1311 "Counter": "2", 1312 "EventCode": "0xB7", 1313 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", 1314 "MSRIndex": "0x1A6", 1315 "MSRValue": "0x47FF", 1316 "SampleAfterValue": "100000", 1317 "UMask": "0x1" 1318 }, 1319 { 1320 "BriefDescription": "Offcore requests satisfied by a remote cache", 1321 "Counter": "2", 1322 "EventCode": "0xB7", 1323 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", 1324 "MSRIndex": "0x1A6", 1325 "MSRValue": "0x18FF", 1326 "SampleAfterValue": "100000", 1327 "UMask": "0x1" 1328 }, 1329 { 1330 "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM", 1331 "Counter": "2", 1332 "EventCode": "0xB7", 1333 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", 1334 "MSRIndex": "0x1A6", 1335 "MSRValue": "0x38FF", 1336 "SampleAfterValue": "100000", 1337 "UMask": "0x1" 1338 }, 1339 { 1340 "BriefDescription": "Offcore requests that HIT in a remote cache", 1341 "Counter": "2", 1342 "EventCode": "0xB7", 1343 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", 1344 "MSRIndex": "0x1A6", 1345 "MSRValue": "0x10FF", 1346 "SampleAfterValue": "100000", 1347 "UMask": "0x1" 1348 }, 1349 { 1350 "BriefDescription": "Offcore requests that HITM in a remote cache", 1351 "Counter": "2", 1352 "EventCode": "0xB7", 1353 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", 1354 "MSRIndex": "0x1A6", 1355 "MSRValue": "0x8FF", 1356 "SampleAfterValue": "100000", 1357 "UMask": "0x1" 1358 }, 1359 { 1360 "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM", 1361 "Counter": "2", 1362 "EventCode": "0xB7", 1363 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", 1364 "MSRIndex": "0x1A6", 1365 "MSRValue": "0x7F22", 1366 "SampleAfterValue": "100000", 1367 "UMask": "0x1" 1368 }, 1369 { 1370 "BriefDescription": "All offcore RFO requests", 1371 "Counter": "2", 1372 "EventCode": "0xB7", 1373 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", 1374 "MSRIndex": "0x1A6", 1375 "MSRValue": "0xFF22", 1376 "SampleAfterValue": "100000", 1377 "UMask": "0x1" 1378 }, 1379 { 1380 "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", 1381 "Counter": "2", 1382 "EventCode": "0xB7", 1383 "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", 1384 "MSRIndex": "0x1A6", 1385 "MSRValue": "0x8022", 1386 "SampleAfterValue": "100000", 1387 "UMask": "0x1" 1388 }, 1389 { 1390 "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", 1391 "Counter": "2", 1392 "EventCode": "0xB7", 1393 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", 1394 "MSRIndex": "0x1A6", 1395 "MSRValue": "0x122", 1396 "SampleAfterValue": "100000", 1397 "UMask": "0x1" 1398 }, 1399 { 1400 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", 1401 "Counter": "2", 1402 "EventCode": "0xB7", 1403 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", 1404 "MSRIndex": "0x1A6", 1405 "MSRValue": "0x222", 1406 "SampleAfterValue": "100000", 1407 "UMask": "0x1" 1408 }, 1409 { 1410 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", 1411 "Counter": "2", 1412 "EventCode": "0xB7", 1413 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", 1414 "MSRIndex": "0x1A6", 1415 "MSRValue": "0x422", 1416 "SampleAfterValue": "100000", 1417 "UMask": "0x1" 1418 }, 1419 { 1420 "BriefDescription": "Offcore RFO requests satisfied by the LLC", 1421 "Counter": "2", 1422 "EventCode": "0xB7", 1423 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", 1424 "MSRIndex": "0x1A6", 1425 "MSRValue": "0x722", 1426 "SampleAfterValue": "100000", 1427 "UMask": "0x1" 1428 }, 1429 { 1430 "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", 1431 "Counter": "2", 1432 "EventCode": "0xB7", 1433 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", 1434 "MSRIndex": "0x1A6", 1435 "MSRValue": "0x4722", 1436 "SampleAfterValue": "100000", 1437 "UMask": "0x1" 1438 }, 1439 { 1440 "BriefDescription": "Offcore RFO requests satisfied by a remote cache", 1441 "Counter": "2", 1442 "EventCode": "0xB7", 1443 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", 1444 "MSRIndex": "0x1A6", 1445 "MSRValue": "0x1822", 1446 "SampleAfterValue": "100000", 1447 "UMask": "0x1" 1448 }, 1449 { 1450 "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", 1451 "Counter": "2", 1452 "EventCode": "0xB7", 1453 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", 1454 "MSRIndex": "0x1A6", 1455 "MSRValue": "0x3822", 1456 "SampleAfterValue": "100000", 1457 "UMask": "0x1" 1458 }, 1459 { 1460 "BriefDescription": "Offcore RFO requests that HIT in a remote cache", 1461 "Counter": "2", 1462 "EventCode": "0xB7", 1463 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", 1464 "MSRIndex": "0x1A6", 1465 "MSRValue": "0x1022", 1466 "SampleAfterValue": "100000", 1467 "UMask": "0x1" 1468 }, 1469 { 1470 "BriefDescription": "Offcore RFO requests that HITM in a remote cache", 1471 "Counter": "2", 1472 "EventCode": "0xB7", 1473 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", 1474 "MSRIndex": "0x1A6", 1475 "MSRValue": "0x822", 1476 "SampleAfterValue": "100000", 1477 "UMask": "0x1" 1478 }, 1479 { 1480 "BriefDescription": "Offcore writebacks to any cache or DRAM.", 1481 "Counter": "2", 1482 "EventCode": "0xB7", 1483 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", 1484 "MSRIndex": "0x1A6", 1485 "MSRValue": "0x7F08", 1486 "SampleAfterValue": "100000", 1487 "UMask": "0x1" 1488 }, 1489 { 1490 "BriefDescription": "All offcore writebacks", 1491 "Counter": "2", 1492 "EventCode": "0xB7", 1493 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", 1494 "MSRIndex": "0x1A6", 1495 "MSRValue": "0xFF08", 1496 "SampleAfterValue": "100000", 1497 "UMask": "0x1" 1498 }, 1499 { 1500 "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", 1501 "Counter": "2", 1502 "EventCode": "0xB7", 1503 "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", 1504 "MSRIndex": "0x1A6", 1505 "MSRValue": "0x8008", 1506 "SampleAfterValue": "100000", 1507 "UMask": "0x1" 1508 }, 1509 { 1510 "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core", 1511 "Counter": "2", 1512 "EventCode": "0xB7", 1513 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", 1514 "MSRIndex": "0x1A6", 1515 "MSRValue": "0x108", 1516 "SampleAfterValue": "100000", 1517 "UMask": "0x1" 1518 }, 1519 { 1520 "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core", 1521 "Counter": "2", 1522 "EventCode": "0xB7", 1523 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", 1524 "MSRIndex": "0x1A6", 1525 "MSRValue": "0x408", 1526 "SampleAfterValue": "100000", 1527 "UMask": "0x1" 1528 }, 1529 { 1530 "BriefDescription": "Offcore writebacks to the LLC", 1531 "Counter": "2", 1532 "EventCode": "0xB7", 1533 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", 1534 "MSRIndex": "0x1A6", 1535 "MSRValue": "0x708", 1536 "SampleAfterValue": "100000", 1537 "UMask": "0x1" 1538 }, 1539 { 1540 "BriefDescription": "Offcore writebacks to the LLC or local DRAM", 1541 "Counter": "2", 1542 "EventCode": "0xB7", 1543 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", 1544 "MSRIndex": "0x1A6", 1545 "MSRValue": "0x4708", 1546 "SampleAfterValue": "100000", 1547 "UMask": "0x1" 1548 }, 1549 { 1550 "BriefDescription": "Offcore writebacks to a remote cache", 1551 "Counter": "2", 1552 "EventCode": "0xB7", 1553 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", 1554 "MSRIndex": "0x1A6", 1555 "MSRValue": "0x1808", 1556 "SampleAfterValue": "100000", 1557 "UMask": "0x1" 1558 }, 1559 { 1560 "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM", 1561 "Counter": "2", 1562 "EventCode": "0xB7", 1563 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", 1564 "MSRIndex": "0x1A6", 1565 "MSRValue": "0x3808", 1566 "SampleAfterValue": "100000", 1567 "UMask": "0x1" 1568 }, 1569 { 1570 "BriefDescription": "Offcore writebacks that HIT in a remote cache", 1571 "Counter": "2", 1572 "EventCode": "0xB7", 1573 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", 1574 "MSRIndex": "0x1A6", 1575 "MSRValue": "0x1008", 1576 "SampleAfterValue": "100000", 1577 "UMask": "0x1" 1578 }, 1579 { 1580 "BriefDescription": "Offcore writebacks that HITM in a remote cache", 1581 "Counter": "2", 1582 "EventCode": "0xB7", 1583 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", 1584 "MSRIndex": "0x1A6", 1585 "MSRValue": "0x808", 1586 "SampleAfterValue": "100000", 1587 "UMask": "0x1" 1588 }, 1589 { 1590 "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", 1591 "Counter": "2", 1592 "EventCode": "0xB7", 1593 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", 1594 "MSRIndex": "0x1A6", 1595 "MSRValue": "0x7F77", 1596 "SampleAfterValue": "100000", 1597 "UMask": "0x1" 1598 }, 1599 { 1600 "BriefDescription": "All offcore code or data read requests", 1601 "Counter": "2", 1602 "EventCode": "0xB7", 1603 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", 1604 "MSRIndex": "0x1A6", 1605 "MSRValue": "0xFF77", 1606 "SampleAfterValue": "100000", 1607 "UMask": "0x1" 1608 }, 1609 { 1610 "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", 1611 "Counter": "2", 1612 "EventCode": "0xB7", 1613 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", 1614 "MSRIndex": "0x1A6", 1615 "MSRValue": "0x8077", 1616 "SampleAfterValue": "100000", 1617 "UMask": "0x1" 1618 }, 1619 { 1620 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", 1621 "Counter": "2", 1622 "EventCode": "0xB7", 1623 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", 1624 "MSRIndex": "0x1A6", 1625 "MSRValue": "0x177", 1626 "SampleAfterValue": "100000", 1627 "UMask": "0x1" 1628 }, 1629 { 1630 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", 1631 "Counter": "2", 1632 "EventCode": "0xB7", 1633 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1634 "MSRIndex": "0x1A6", 1635 "MSRValue": "0x277", 1636 "SampleAfterValue": "100000", 1637 "UMask": "0x1" 1638 }, 1639 { 1640 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", 1641 "Counter": "2", 1642 "EventCode": "0xB7", 1643 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1644 "MSRIndex": "0x1A6", 1645 "MSRValue": "0x477", 1646 "SampleAfterValue": "100000", 1647 "UMask": "0x1" 1648 }, 1649 { 1650 "BriefDescription": "Offcore code or data read requests satisfied by the LLC", 1651 "Counter": "2", 1652 "EventCode": "0xB7", 1653 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", 1654 "MSRIndex": "0x1A6", 1655 "MSRValue": "0x777", 1656 "SampleAfterValue": "100000", 1657 "UMask": "0x1" 1658 }, 1659 { 1660 "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", 1661 "Counter": "2", 1662 "EventCode": "0xB7", 1663 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", 1664 "MSRIndex": "0x1A6", 1665 "MSRValue": "0x4777", 1666 "SampleAfterValue": "100000", 1667 "UMask": "0x1" 1668 }, 1669 { 1670 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache", 1671 "Counter": "2", 1672 "EventCode": "0xB7", 1673 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", 1674 "MSRIndex": "0x1A6", 1675 "MSRValue": "0x1877", 1676 "SampleAfterValue": "100000", 1677 "UMask": "0x1" 1678 }, 1679 { 1680 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", 1681 "Counter": "2", 1682 "EventCode": "0xB7", 1683 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", 1684 "MSRIndex": "0x1A6", 1685 "MSRValue": "0x3877", 1686 "SampleAfterValue": "100000", 1687 "UMask": "0x1" 1688 }, 1689 { 1690 "BriefDescription": "Offcore code or data read requests that HIT in a remote cache", 1691 "Counter": "2", 1692 "EventCode": "0xB7", 1693 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", 1694 "MSRIndex": "0x1A6", 1695 "MSRValue": "0x1077", 1696 "SampleAfterValue": "100000", 1697 "UMask": "0x1" 1698 }, 1699 { 1700 "BriefDescription": "Offcore code or data read requests that HITM in a remote cache", 1701 "Counter": "2", 1702 "EventCode": "0xB7", 1703 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", 1704 "MSRIndex": "0x1A6", 1705 "MSRValue": "0x877", 1706 "SampleAfterValue": "100000", 1707 "UMask": "0x1" 1708 }, 1709 { 1710 "BriefDescription": "Offcore request = all data, response = any cache_dram", 1711 "Counter": "2", 1712 "EventCode": "0xB7", 1713 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", 1714 "MSRIndex": "0x1A6", 1715 "MSRValue": "0x7F33", 1716 "SampleAfterValue": "100000", 1717 "UMask": "0x1" 1718 }, 1719 { 1720 "BriefDescription": "Offcore request = all data, response = any location", 1721 "Counter": "2", 1722 "EventCode": "0xB7", 1723 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", 1724 "MSRIndex": "0x1A6", 1725 "MSRValue": "0xFF33", 1726 "SampleAfterValue": "100000", 1727 "UMask": "0x1" 1728 }, 1729 { 1730 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit", 1731 "Counter": "2", 1732 "EventCode": "0xB7", 1733 "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", 1734 "MSRIndex": "0x1A6", 1735 "MSRValue": "0x8033", 1736 "SampleAfterValue": "100000", 1737 "UMask": "0x1" 1738 }, 1739 { 1740 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core", 1741 "Counter": "2", 1742 "EventCode": "0xB7", 1743 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", 1744 "MSRIndex": "0x1A6", 1745 "MSRValue": "0x133", 1746 "SampleAfterValue": "100000", 1747 "UMask": "0x1" 1748 }, 1749 { 1750 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core", 1751 "Counter": "2", 1752 "EventCode": "0xB7", 1753 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", 1754 "MSRIndex": "0x1A6", 1755 "MSRValue": "0x233", 1756 "SampleAfterValue": "100000", 1757 "UMask": "0x1" 1758 }, 1759 { 1760 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core", 1761 "Counter": "2", 1762 "EventCode": "0xB7", 1763 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", 1764 "MSRIndex": "0x1A6", 1765 "MSRValue": "0x433", 1766 "SampleAfterValue": "100000", 1767 "UMask": "0x1" 1768 }, 1769 { 1770 "BriefDescription": "Offcore request = all data, response = local cache", 1771 "Counter": "2", 1772 "EventCode": "0xB7", 1773 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", 1774 "MSRIndex": "0x1A6", 1775 "MSRValue": "0x733", 1776 "SampleAfterValue": "100000", 1777 "UMask": "0x1" 1778 }, 1779 { 1780 "BriefDescription": "Offcore request = all data, response = local cache or dram", 1781 "Counter": "2", 1782 "EventCode": "0xB7", 1783 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", 1784 "MSRIndex": "0x1A6", 1785 "MSRValue": "0x4733", 1786 "SampleAfterValue": "100000", 1787 "UMask": "0x1" 1788 }, 1789 { 1790 "BriefDescription": "Offcore request = all data, response = remote cache", 1791 "Counter": "2", 1792 "EventCode": "0xB7", 1793 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", 1794 "MSRIndex": "0x1A6", 1795 "MSRValue": "0x1833", 1796 "SampleAfterValue": "100000", 1797 "UMask": "0x1" 1798 }, 1799 { 1800 "BriefDescription": "Offcore request = all data, response = remote cache or dram", 1801 "Counter": "2", 1802 "EventCode": "0xB7", 1803 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", 1804 "MSRIndex": "0x1A6", 1805 "MSRValue": "0x3833", 1806 "SampleAfterValue": "100000", 1807 "UMask": "0x1" 1808 }, 1809 { 1810 "BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache", 1811 "Counter": "2", 1812 "EventCode": "0xB7", 1813 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", 1814 "MSRIndex": "0x1A6", 1815 "MSRValue": "0x1033", 1816 "SampleAfterValue": "100000", 1817 "UMask": "0x1" 1818 }, 1819 { 1820 "BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache", 1821 "Counter": "2", 1822 "EventCode": "0xB7", 1823 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", 1824 "MSRIndex": "0x1A6", 1825 "MSRValue": "0x833", 1826 "SampleAfterValue": "100000", 1827 "UMask": "0x1" 1828 }, 1829 { 1830 "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM", 1831 "Counter": "2", 1832 "EventCode": "0xB7", 1833 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", 1834 "MSRIndex": "0x1A6", 1835 "MSRValue": "0x7F03", 1836 "SampleAfterValue": "100000", 1837 "UMask": "0x1" 1838 }, 1839 { 1840 "BriefDescription": "All offcore demand data requests", 1841 "Counter": "2", 1842 "EventCode": "0xB7", 1843 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", 1844 "MSRIndex": "0x1A6", 1845 "MSRValue": "0xFF03", 1846 "SampleAfterValue": "100000", 1847 "UMask": "0x1" 1848 }, 1849 { 1850 "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", 1851 "Counter": "2", 1852 "EventCode": "0xB7", 1853 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", 1854 "MSRIndex": "0x1A6", 1855 "MSRValue": "0x8003", 1856 "SampleAfterValue": "100000", 1857 "UMask": "0x1" 1858 }, 1859 { 1860 "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", 1861 "Counter": "2", 1862 "EventCode": "0xB7", 1863 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", 1864 "MSRIndex": "0x1A6", 1865 "MSRValue": "0x103", 1866 "SampleAfterValue": "100000", 1867 "UMask": "0x1" 1868 }, 1869 { 1870 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", 1871 "Counter": "2", 1872 "EventCode": "0xB7", 1873 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", 1874 "MSRIndex": "0x1A6", 1875 "MSRValue": "0x203", 1876 "SampleAfterValue": "100000", 1877 "UMask": "0x1" 1878 }, 1879 { 1880 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", 1881 "Counter": "2", 1882 "EventCode": "0xB7", 1883 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", 1884 "MSRIndex": "0x1A6", 1885 "MSRValue": "0x403", 1886 "SampleAfterValue": "100000", 1887 "UMask": "0x1" 1888 }, 1889 { 1890 "BriefDescription": "Offcore demand data requests satisfied by the LLC", 1891 "Counter": "2", 1892 "EventCode": "0xB7", 1893 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", 1894 "MSRIndex": "0x1A6", 1895 "MSRValue": "0x703", 1896 "SampleAfterValue": "100000", 1897 "UMask": "0x1" 1898 }, 1899 { 1900 "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", 1901 "Counter": "2", 1902 "EventCode": "0xB7", 1903 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", 1904 "MSRIndex": "0x1A6", 1905 "MSRValue": "0x4703", 1906 "SampleAfterValue": "100000", 1907 "UMask": "0x1" 1908 }, 1909 { 1910 "BriefDescription": "Offcore demand data requests satisfied by a remote cache", 1911 "Counter": "2", 1912 "EventCode": "0xB7", 1913 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", 1914 "MSRIndex": "0x1A6", 1915 "MSRValue": "0x1803", 1916 "SampleAfterValue": "100000", 1917 "UMask": "0x1" 1918 }, 1919 { 1920 "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", 1921 "Counter": "2", 1922 "EventCode": "0xB7", 1923 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", 1924 "MSRIndex": "0x1A6", 1925 "MSRValue": "0x3803", 1926 "SampleAfterValue": "100000", 1927 "UMask": "0x1" 1928 }, 1929 { 1930 "BriefDescription": "Offcore demand data requests that HIT in a remote cache", 1931 "Counter": "2", 1932 "EventCode": "0xB7", 1933 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", 1934 "MSRIndex": "0x1A6", 1935 "MSRValue": "0x1003", 1936 "SampleAfterValue": "100000", 1937 "UMask": "0x1" 1938 }, 1939 { 1940 "BriefDescription": "Offcore demand data requests that HITM in a remote cache", 1941 "Counter": "2", 1942 "EventCode": "0xB7", 1943 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", 1944 "MSRIndex": "0x1A6", 1945 "MSRValue": "0x803", 1946 "SampleAfterValue": "100000", 1947 "UMask": "0x1" 1948 }, 1949 { 1950 "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.", 1951 "Counter": "2", 1952 "EventCode": "0xB7", 1953 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", 1954 "MSRIndex": "0x1A6", 1955 "MSRValue": "0x7F01", 1956 "SampleAfterValue": "100000", 1957 "UMask": "0x1" 1958 }, 1959 { 1960 "BriefDescription": "All offcore demand data reads", 1961 "Counter": "2", 1962 "EventCode": "0xB7", 1963 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", 1964 "MSRIndex": "0x1A6", 1965 "MSRValue": "0xFF01", 1966 "SampleAfterValue": "100000", 1967 "UMask": "0x1" 1968 }, 1969 { 1970 "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", 1971 "Counter": "2", 1972 "EventCode": "0xB7", 1973 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", 1974 "MSRIndex": "0x1A6", 1975 "MSRValue": "0x8001", 1976 "SampleAfterValue": "100000", 1977 "UMask": "0x1" 1978 }, 1979 { 1980 "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", 1981 "Counter": "2", 1982 "EventCode": "0xB7", 1983 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", 1984 "MSRIndex": "0x1A6", 1985 "MSRValue": "0x101", 1986 "SampleAfterValue": "100000", 1987 "UMask": "0x1" 1988 }, 1989 { 1990 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", 1991 "Counter": "2", 1992 "EventCode": "0xB7", 1993 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 1994 "MSRIndex": "0x1A6", 1995 "MSRValue": "0x201", 1996 "SampleAfterValue": "100000", 1997 "UMask": "0x1" 1998 }, 1999 { 2000 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", 2001 "Counter": "2", 2002 "EventCode": "0xB7", 2003 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 2004 "MSRIndex": "0x1A6", 2005 "MSRValue": "0x401", 2006 "SampleAfterValue": "100000", 2007 "UMask": "0x1" 2008 }, 2009 { 2010 "BriefDescription": "Offcore demand data reads satisfied by the LLC", 2011 "Counter": "2", 2012 "EventCode": "0xB7", 2013 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", 2014 "MSRIndex": "0x1A6", 2015 "MSRValue": "0x701", 2016 "SampleAfterValue": "100000", 2017 "UMask": "0x1" 2018 }, 2019 { 2020 "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", 2021 "Counter": "2", 2022 "EventCode": "0xB7", 2023 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", 2024 "MSRIndex": "0x1A6", 2025 "MSRValue": "0x4701", 2026 "SampleAfterValue": "100000", 2027 "UMask": "0x1" 2028 }, 2029 { 2030 "BriefDescription": "Offcore demand data reads satisfied by a remote cache", 2031 "Counter": "2", 2032 "EventCode": "0xB7", 2033 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", 2034 "MSRIndex": "0x1A6", 2035 "MSRValue": "0x1801", 2036 "SampleAfterValue": "100000", 2037 "UMask": "0x1" 2038 }, 2039 { 2040 "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", 2041 "Counter": "2", 2042 "EventCode": "0xB7", 2043 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", 2044 "MSRIndex": "0x1A6", 2045 "MSRValue": "0x3801", 2046 "SampleAfterValue": "100000", 2047 "UMask": "0x1" 2048 }, 2049 { 2050 "BriefDescription": "Offcore demand data reads that HIT in a remote cache", 2051 "Counter": "2", 2052 "EventCode": "0xB7", 2053 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", 2054 "MSRIndex": "0x1A6", 2055 "MSRValue": "0x1001", 2056 "SampleAfterValue": "100000", 2057 "UMask": "0x1" 2058 }, 2059 { 2060 "BriefDescription": "Offcore demand data reads that HITM in a remote cache", 2061 "Counter": "2", 2062 "EventCode": "0xB7", 2063 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", 2064 "MSRIndex": "0x1A6", 2065 "MSRValue": "0x801", 2066 "SampleAfterValue": "100000", 2067 "UMask": "0x1" 2068 }, 2069 { 2070 "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.", 2071 "Counter": "2", 2072 "EventCode": "0xB7", 2073 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", 2074 "MSRIndex": "0x1A6", 2075 "MSRValue": "0x7F04", 2076 "SampleAfterValue": "100000", 2077 "UMask": "0x1" 2078 }, 2079 { 2080 "BriefDescription": "All offcore demand code reads", 2081 "Counter": "2", 2082 "EventCode": "0xB7", 2083 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", 2084 "MSRIndex": "0x1A6", 2085 "MSRValue": "0xFF04", 2086 "SampleAfterValue": "100000", 2087 "UMask": "0x1" 2088 }, 2089 { 2090 "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", 2091 "Counter": "2", 2092 "EventCode": "0xB7", 2093 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", 2094 "MSRIndex": "0x1A6", 2095 "MSRValue": "0x8004", 2096 "SampleAfterValue": "100000", 2097 "UMask": "0x1" 2098 }, 2099 { 2100 "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", 2101 "Counter": "2", 2102 "EventCode": "0xB7", 2103 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", 2104 "MSRIndex": "0x1A6", 2105 "MSRValue": "0x104", 2106 "SampleAfterValue": "100000", 2107 "UMask": "0x1" 2108 }, 2109 { 2110 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", 2111 "Counter": "2", 2112 "EventCode": "0xB7", 2113 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", 2114 "MSRIndex": "0x1A6", 2115 "MSRValue": "0x204", 2116 "SampleAfterValue": "100000", 2117 "UMask": "0x1" 2118 }, 2119 { 2120 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", 2121 "Counter": "2", 2122 "EventCode": "0xB7", 2123 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", 2124 "MSRIndex": "0x1A6", 2125 "MSRValue": "0x404", 2126 "SampleAfterValue": "100000", 2127 "UMask": "0x1" 2128 }, 2129 { 2130 "BriefDescription": "Offcore demand code reads satisfied by the LLC", 2131 "Counter": "2", 2132 "EventCode": "0xB7", 2133 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", 2134 "MSRIndex": "0x1A6", 2135 "MSRValue": "0x704", 2136 "SampleAfterValue": "100000", 2137 "UMask": "0x1" 2138 }, 2139 { 2140 "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", 2141 "Counter": "2", 2142 "EventCode": "0xB7", 2143 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", 2144 "MSRIndex": "0x1A6", 2145 "MSRValue": "0x4704", 2146 "SampleAfterValue": "100000", 2147 "UMask": "0x1" 2148 }, 2149 { 2150 "BriefDescription": "Offcore demand code reads satisfied by a remote cache", 2151 "Counter": "2", 2152 "EventCode": "0xB7", 2153 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", 2154 "MSRIndex": "0x1A6", 2155 "MSRValue": "0x1804", 2156 "SampleAfterValue": "100000", 2157 "UMask": "0x1" 2158 }, 2159 { 2160 "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", 2161 "Counter": "2", 2162 "EventCode": "0xB7", 2163 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", 2164 "MSRIndex": "0x1A6", 2165 "MSRValue": "0x3804", 2166 "SampleAfterValue": "100000", 2167 "UMask": "0x1" 2168 }, 2169 { 2170 "BriefDescription": "Offcore demand code reads that HIT in a remote cache", 2171 "Counter": "2", 2172 "EventCode": "0xB7", 2173 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", 2174 "MSRIndex": "0x1A6", 2175 "MSRValue": "0x1004", 2176 "SampleAfterValue": "100000", 2177 "UMask": "0x1" 2178 }, 2179 { 2180 "BriefDescription": "Offcore demand code reads that HITM in a remote cache", 2181 "Counter": "2", 2182 "EventCode": "0xB7", 2183 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", 2184 "MSRIndex": "0x1A6", 2185 "MSRValue": "0x804", 2186 "SampleAfterValue": "100000", 2187 "UMask": "0x1" 2188 }, 2189 { 2190 "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", 2191 "Counter": "2", 2192 "EventCode": "0xB7", 2193 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", 2194 "MSRIndex": "0x1A6", 2195 "MSRValue": "0x7F02", 2196 "SampleAfterValue": "100000", 2197 "UMask": "0x1" 2198 }, 2199 { 2200 "BriefDescription": "All offcore demand RFO requests", 2201 "Counter": "2", 2202 "EventCode": "0xB7", 2203 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", 2204 "MSRIndex": "0x1A6", 2205 "MSRValue": "0xFF02", 2206 "SampleAfterValue": "100000", 2207 "UMask": "0x1" 2208 }, 2209 { 2210 "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", 2211 "Counter": "2", 2212 "EventCode": "0xB7", 2213 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", 2214 "MSRIndex": "0x1A6", 2215 "MSRValue": "0x8002", 2216 "SampleAfterValue": "100000", 2217 "UMask": "0x1" 2218 }, 2219 { 2220 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", 2221 "Counter": "2", 2222 "EventCode": "0xB7", 2223 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", 2224 "MSRIndex": "0x1A6", 2225 "MSRValue": "0x102", 2226 "SampleAfterValue": "100000", 2227 "UMask": "0x1" 2228 }, 2229 { 2230 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", 2231 "Counter": "2", 2232 "EventCode": "0xB7", 2233 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", 2234 "MSRIndex": "0x1A6", 2235 "MSRValue": "0x202", 2236 "SampleAfterValue": "100000", 2237 "UMask": "0x1" 2238 }, 2239 { 2240 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", 2241 "Counter": "2", 2242 "EventCode": "0xB7", 2243 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", 2244 "MSRIndex": "0x1A6", 2245 "MSRValue": "0x402", 2246 "SampleAfterValue": "100000", 2247 "UMask": "0x1" 2248 }, 2249 { 2250 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC", 2251 "Counter": "2", 2252 "EventCode": "0xB7", 2253 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", 2254 "MSRIndex": "0x1A6", 2255 "MSRValue": "0x702", 2256 "SampleAfterValue": "100000", 2257 "UMask": "0x1" 2258 }, 2259 { 2260 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", 2261 "Counter": "2", 2262 "EventCode": "0xB7", 2263 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", 2264 "MSRIndex": "0x1A6", 2265 "MSRValue": "0x4702", 2266 "SampleAfterValue": "100000", 2267 "UMask": "0x1" 2268 }, 2269 { 2270 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache", 2271 "Counter": "2", 2272 "EventCode": "0xB7", 2273 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", 2274 "MSRIndex": "0x1A6", 2275 "MSRValue": "0x1802", 2276 "SampleAfterValue": "100000", 2277 "UMask": "0x1" 2278 }, 2279 { 2280 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", 2281 "Counter": "2", 2282 "EventCode": "0xB7", 2283 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", 2284 "MSRIndex": "0x1A6", 2285 "MSRValue": "0x3802", 2286 "SampleAfterValue": "100000", 2287 "UMask": "0x1" 2288 }, 2289 { 2290 "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache", 2291 "Counter": "2", 2292 "EventCode": "0xB7", 2293 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", 2294 "MSRIndex": "0x1A6", 2295 "MSRValue": "0x1002", 2296 "SampleAfterValue": "100000", 2297 "UMask": "0x1" 2298 }, 2299 { 2300 "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache", 2301 "Counter": "2", 2302 "EventCode": "0xB7", 2303 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", 2304 "MSRIndex": "0x1A6", 2305 "MSRValue": "0x802", 2306 "SampleAfterValue": "100000", 2307 "UMask": "0x1" 2308 }, 2309 { 2310 "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.", 2311 "Counter": "2", 2312 "EventCode": "0xB7", 2313 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", 2314 "MSRIndex": "0x1A6", 2315 "MSRValue": "0x7F80", 2316 "SampleAfterValue": "100000", 2317 "UMask": "0x1" 2318 }, 2319 { 2320 "BriefDescription": "All offcore other requests", 2321 "Counter": "2", 2322 "EventCode": "0xB7", 2323 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", 2324 "MSRIndex": "0x1A6", 2325 "MSRValue": "0xFF80", 2326 "SampleAfterValue": "100000", 2327 "UMask": "0x1" 2328 }, 2329 { 2330 "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", 2331 "Counter": "2", 2332 "EventCode": "0xB7", 2333 "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", 2334 "MSRIndex": "0x1A6", 2335 "MSRValue": "0x8080", 2336 "SampleAfterValue": "100000", 2337 "UMask": "0x1" 2338 }, 2339 { 2340 "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", 2341 "Counter": "2", 2342 "EventCode": "0xB7", 2343 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", 2344 "MSRIndex": "0x1A6", 2345 "MSRValue": "0x180", 2346 "SampleAfterValue": "100000", 2347 "UMask": "0x1" 2348 }, 2349 { 2350 "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", 2351 "Counter": "2", 2352 "EventCode": "0xB7", 2353 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", 2354 "MSRIndex": "0x1A6", 2355 "MSRValue": "0x280", 2356 "SampleAfterValue": "100000", 2357 "UMask": "0x1" 2358 }, 2359 { 2360 "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", 2361 "Counter": "2", 2362 "EventCode": "0xB7", 2363 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", 2364 "MSRIndex": "0x1A6", 2365 "MSRValue": "0x480", 2366 "SampleAfterValue": "100000", 2367 "UMask": "0x1" 2368 }, 2369 { 2370 "BriefDescription": "Offcore other requests satisfied by the LLC", 2371 "Counter": "2", 2372 "EventCode": "0xB7", 2373 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", 2374 "MSRIndex": "0x1A6", 2375 "MSRValue": "0x780", 2376 "SampleAfterValue": "100000", 2377 "UMask": "0x1" 2378 }, 2379 { 2380 "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM", 2381 "Counter": "2", 2382 "EventCode": "0xB7", 2383 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", 2384 "MSRIndex": "0x1A6", 2385 "MSRValue": "0x4780", 2386 "SampleAfterValue": "100000", 2387 "UMask": "0x1" 2388 }, 2389 { 2390 "BriefDescription": "Offcore other requests satisfied by a remote cache", 2391 "Counter": "2", 2392 "EventCode": "0xB7", 2393 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", 2394 "MSRIndex": "0x1A6", 2395 "MSRValue": "0x1880", 2396 "SampleAfterValue": "100000", 2397 "UMask": "0x1" 2398 }, 2399 { 2400 "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM", 2401 "Counter": "2", 2402 "EventCode": "0xB7", 2403 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", 2404 "MSRIndex": "0x1A6", 2405 "MSRValue": "0x3880", 2406 "SampleAfterValue": "100000", 2407 "UMask": "0x1" 2408 }, 2409 { 2410 "BriefDescription": "Offcore other requests that HIT in a remote cache", 2411 "Counter": "2", 2412 "EventCode": "0xB7", 2413 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", 2414 "MSRIndex": "0x1A6", 2415 "MSRValue": "0x1080", 2416 "SampleAfterValue": "100000", 2417 "UMask": "0x1" 2418 }, 2419 { 2420 "BriefDescription": "Offcore other requests that HITM in a remote cache", 2421 "Counter": "2", 2422 "EventCode": "0xB7", 2423 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", 2424 "MSRIndex": "0x1A6", 2425 "MSRValue": "0x880", 2426 "SampleAfterValue": "100000", 2427 "UMask": "0x1" 2428 }, 2429 { 2430 "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM", 2431 "Counter": "2", 2432 "EventCode": "0xB7", 2433 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", 2434 "MSRIndex": "0x1A6", 2435 "MSRValue": "0x7F30", 2436 "SampleAfterValue": "100000", 2437 "UMask": "0x1" 2438 }, 2439 { 2440 "BriefDescription": "All offcore prefetch data requests", 2441 "Counter": "2", 2442 "EventCode": "0xB7", 2443 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", 2444 "MSRIndex": "0x1A6", 2445 "MSRValue": "0xFF30", 2446 "SampleAfterValue": "100000", 2447 "UMask": "0x1" 2448 }, 2449 { 2450 "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.", 2451 "Counter": "2", 2452 "EventCode": "0xB7", 2453 "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", 2454 "MSRIndex": "0x1A6", 2455 "MSRValue": "0x8030", 2456 "SampleAfterValue": "100000", 2457 "UMask": "0x1" 2458 }, 2459 { 2460 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core", 2461 "Counter": "2", 2462 "EventCode": "0xB7", 2463 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", 2464 "MSRIndex": "0x1A6", 2465 "MSRValue": "0x130", 2466 "SampleAfterValue": "100000", 2467 "UMask": "0x1" 2468 }, 2469 { 2470 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core", 2471 "Counter": "2", 2472 "EventCode": "0xB7", 2473 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", 2474 "MSRIndex": "0x1A6", 2475 "MSRValue": "0x230", 2476 "SampleAfterValue": "100000", 2477 "UMask": "0x1" 2478 }, 2479 { 2480 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core", 2481 "Counter": "2", 2482 "EventCode": "0xB7", 2483 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", 2484 "MSRIndex": "0x1A6", 2485 "MSRValue": "0x430", 2486 "SampleAfterValue": "100000", 2487 "UMask": "0x1" 2488 }, 2489 { 2490 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC", 2491 "Counter": "2", 2492 "EventCode": "0xB7", 2493 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", 2494 "MSRIndex": "0x1A6", 2495 "MSRValue": "0x730", 2496 "SampleAfterValue": "100000", 2497 "UMask": "0x1" 2498 }, 2499 { 2500 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM", 2501 "Counter": "2", 2502 "EventCode": "0xB7", 2503 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", 2504 "MSRIndex": "0x1A6", 2505 "MSRValue": "0x4730", 2506 "SampleAfterValue": "100000", 2507 "UMask": "0x1" 2508 }, 2509 { 2510 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache", 2511 "Counter": "2", 2512 "EventCode": "0xB7", 2513 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", 2514 "MSRIndex": "0x1A6", 2515 "MSRValue": "0x1830", 2516 "SampleAfterValue": "100000", 2517 "UMask": "0x1" 2518 }, 2519 { 2520 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM", 2521 "Counter": "2", 2522 "EventCode": "0xB7", 2523 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", 2524 "MSRIndex": "0x1A6", 2525 "MSRValue": "0x3830", 2526 "SampleAfterValue": "100000", 2527 "UMask": "0x1" 2528 }, 2529 { 2530 "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache", 2531 "Counter": "2", 2532 "EventCode": "0xB7", 2533 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", 2534 "MSRIndex": "0x1A6", 2535 "MSRValue": "0x1030", 2536 "SampleAfterValue": "100000", 2537 "UMask": "0x1" 2538 }, 2539 { 2540 "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache", 2541 "Counter": "2", 2542 "EventCode": "0xB7", 2543 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", 2544 "MSRIndex": "0x1A6", 2545 "MSRValue": "0x830", 2546 "SampleAfterValue": "100000", 2547 "UMask": "0x1" 2548 }, 2549 { 2550 "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.", 2551 "Counter": "2", 2552 "EventCode": "0xB7", 2553 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", 2554 "MSRIndex": "0x1A6", 2555 "MSRValue": "0x7F10", 2556 "SampleAfterValue": "100000", 2557 "UMask": "0x1" 2558 }, 2559 { 2560 "BriefDescription": "All offcore prefetch data reads", 2561 "Counter": "2", 2562 "EventCode": "0xB7", 2563 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", 2564 "MSRIndex": "0x1A6", 2565 "MSRValue": "0xFF10", 2566 "SampleAfterValue": "100000", 2567 "UMask": "0x1" 2568 }, 2569 { 2570 "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit", 2571 "Counter": "2", 2572 "EventCode": "0xB7", 2573 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", 2574 "MSRIndex": "0x1A6", 2575 "MSRValue": "0x8010", 2576 "SampleAfterValue": "100000", 2577 "UMask": "0x1" 2578 }, 2579 { 2580 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core", 2581 "Counter": "2", 2582 "EventCode": "0xB7", 2583 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", 2584 "MSRIndex": "0x1A6", 2585 "MSRValue": "0x110", 2586 "SampleAfterValue": "100000", 2587 "UMask": "0x1" 2588 }, 2589 { 2590 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core", 2591 "Counter": "2", 2592 "EventCode": "0xB7", 2593 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 2594 "MSRIndex": "0x1A6", 2595 "MSRValue": "0x210", 2596 "SampleAfterValue": "100000", 2597 "UMask": "0x1" 2598 }, 2599 { 2600 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core", 2601 "Counter": "2", 2602 "EventCode": "0xB7", 2603 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 2604 "MSRIndex": "0x1A6", 2605 "MSRValue": "0x410", 2606 "SampleAfterValue": "100000", 2607 "UMask": "0x1" 2608 }, 2609 { 2610 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC", 2611 "Counter": "2", 2612 "EventCode": "0xB7", 2613 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", 2614 "MSRIndex": "0x1A6", 2615 "MSRValue": "0x710", 2616 "SampleAfterValue": "100000", 2617 "UMask": "0x1" 2618 }, 2619 { 2620 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM", 2621 "Counter": "2", 2622 "EventCode": "0xB7", 2623 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", 2624 "MSRIndex": "0x1A6", 2625 "MSRValue": "0x4710", 2626 "SampleAfterValue": "100000", 2627 "UMask": "0x1" 2628 }, 2629 { 2630 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache", 2631 "Counter": "2", 2632 "EventCode": "0xB7", 2633 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", 2634 "MSRIndex": "0x1A6", 2635 "MSRValue": "0x1810", 2636 "SampleAfterValue": "100000", 2637 "UMask": "0x1" 2638 }, 2639 { 2640 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM", 2641 "Counter": "2", 2642 "EventCode": "0xB7", 2643 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", 2644 "MSRIndex": "0x1A6", 2645 "MSRValue": "0x3810", 2646 "SampleAfterValue": "100000", 2647 "UMask": "0x1" 2648 }, 2649 { 2650 "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache", 2651 "Counter": "2", 2652 "EventCode": "0xB7", 2653 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", 2654 "MSRIndex": "0x1A6", 2655 "MSRValue": "0x1010", 2656 "SampleAfterValue": "100000", 2657 "UMask": "0x1" 2658 }, 2659 { 2660 "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache", 2661 "Counter": "2", 2662 "EventCode": "0xB7", 2663 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", 2664 "MSRIndex": "0x1A6", 2665 "MSRValue": "0x810", 2666 "SampleAfterValue": "100000", 2667 "UMask": "0x1" 2668 }, 2669 { 2670 "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.", 2671 "Counter": "2", 2672 "EventCode": "0xB7", 2673 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", 2674 "MSRIndex": "0x1A6", 2675 "MSRValue": "0x7F40", 2676 "SampleAfterValue": "100000", 2677 "UMask": "0x1" 2678 }, 2679 { 2680 "BriefDescription": "All offcore prefetch code reads", 2681 "Counter": "2", 2682 "EventCode": "0xB7", 2683 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", 2684 "MSRIndex": "0x1A6", 2685 "MSRValue": "0xFF40", 2686 "SampleAfterValue": "100000", 2687 "UMask": "0x1" 2688 }, 2689 { 2690 "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit", 2691 "Counter": "2", 2692 "EventCode": "0xB7", 2693 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", 2694 "MSRIndex": "0x1A6", 2695 "MSRValue": "0x8040", 2696 "SampleAfterValue": "100000", 2697 "UMask": "0x1" 2698 }, 2699 { 2700 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core", 2701 "Counter": "2", 2702 "EventCode": "0xB7", 2703 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", 2704 "MSRIndex": "0x1A6", 2705 "MSRValue": "0x140", 2706 "SampleAfterValue": "100000", 2707 "UMask": "0x1" 2708 }, 2709 { 2710 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core", 2711 "Counter": "2", 2712 "EventCode": "0xB7", 2713 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", 2714 "MSRIndex": "0x1A6", 2715 "MSRValue": "0x240", 2716 "SampleAfterValue": "100000", 2717 "UMask": "0x1" 2718 }, 2719 { 2720 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core", 2721 "Counter": "2", 2722 "EventCode": "0xB7", 2723 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", 2724 "MSRIndex": "0x1A6", 2725 "MSRValue": "0x440", 2726 "SampleAfterValue": "100000", 2727 "UMask": "0x1" 2728 }, 2729 { 2730 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC", 2731 "Counter": "2", 2732 "EventCode": "0xB7", 2733 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", 2734 "MSRIndex": "0x1A6", 2735 "MSRValue": "0x740", 2736 "SampleAfterValue": "100000", 2737 "UMask": "0x1" 2738 }, 2739 { 2740 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM", 2741 "Counter": "2", 2742 "EventCode": "0xB7", 2743 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", 2744 "MSRIndex": "0x1A6", 2745 "MSRValue": "0x4740", 2746 "SampleAfterValue": "100000", 2747 "UMask": "0x1" 2748 }, 2749 { 2750 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache", 2751 "Counter": "2", 2752 "EventCode": "0xB7", 2753 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", 2754 "MSRIndex": "0x1A6", 2755 "MSRValue": "0x1840", 2756 "SampleAfterValue": "100000", 2757 "UMask": "0x1" 2758 }, 2759 { 2760 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM", 2761 "Counter": "2", 2762 "EventCode": "0xB7", 2763 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", 2764 "MSRIndex": "0x1A6", 2765 "MSRValue": "0x3840", 2766 "SampleAfterValue": "100000", 2767 "UMask": "0x1" 2768 }, 2769 { 2770 "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache", 2771 "Counter": "2", 2772 "EventCode": "0xB7", 2773 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", 2774 "MSRIndex": "0x1A6", 2775 "MSRValue": "0x1040", 2776 "SampleAfterValue": "100000", 2777 "UMask": "0x1" 2778 }, 2779 { 2780 "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache", 2781 "Counter": "2", 2782 "EventCode": "0xB7", 2783 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", 2784 "MSRIndex": "0x1A6", 2785 "MSRValue": "0x840", 2786 "SampleAfterValue": "100000", 2787 "UMask": "0x1" 2788 }, 2789 { 2790 "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.", 2791 "Counter": "2", 2792 "EventCode": "0xB7", 2793 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", 2794 "MSRIndex": "0x1A6", 2795 "MSRValue": "0x7F20", 2796 "SampleAfterValue": "100000", 2797 "UMask": "0x1" 2798 }, 2799 { 2800 "BriefDescription": "All offcore prefetch RFO requests", 2801 "Counter": "2", 2802 "EventCode": "0xB7", 2803 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", 2804 "MSRIndex": "0x1A6", 2805 "MSRValue": "0xFF20", 2806 "SampleAfterValue": "100000", 2807 "UMask": "0x1" 2808 }, 2809 { 2810 "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit", 2811 "Counter": "2", 2812 "EventCode": "0xB7", 2813 "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", 2814 "MSRIndex": "0x1A6", 2815 "MSRValue": "0x8020", 2816 "SampleAfterValue": "100000", 2817 "UMask": "0x1" 2818 }, 2819 { 2820 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core", 2821 "Counter": "2", 2822 "EventCode": "0xB7", 2823 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", 2824 "MSRIndex": "0x1A6", 2825 "MSRValue": "0x120", 2826 "SampleAfterValue": "100000", 2827 "UMask": "0x1" 2828 }, 2829 { 2830 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core", 2831 "Counter": "2", 2832 "EventCode": "0xB7", 2833 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", 2834 "MSRIndex": "0x1A6", 2835 "MSRValue": "0x220", 2836 "SampleAfterValue": "100000", 2837 "UMask": "0x1" 2838 }, 2839 { 2840 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core", 2841 "Counter": "2", 2842 "EventCode": "0xB7", 2843 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", 2844 "MSRIndex": "0x1A6", 2845 "MSRValue": "0x420", 2846 "SampleAfterValue": "100000", 2847 "UMask": "0x1" 2848 }, 2849 { 2850 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC", 2851 "Counter": "2", 2852 "EventCode": "0xB7", 2853 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", 2854 "MSRIndex": "0x1A6", 2855 "MSRValue": "0x720", 2856 "SampleAfterValue": "100000", 2857 "UMask": "0x1" 2858 }, 2859 { 2860 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM", 2861 "Counter": "2", 2862 "EventCode": "0xB7", 2863 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", 2864 "MSRIndex": "0x1A6", 2865 "MSRValue": "0x4720", 2866 "SampleAfterValue": "100000", 2867 "UMask": "0x1" 2868 }, 2869 { 2870 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache", 2871 "Counter": "2", 2872 "EventCode": "0xB7", 2873 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", 2874 "MSRIndex": "0x1A6", 2875 "MSRValue": "0x1820", 2876 "SampleAfterValue": "100000", 2877 "UMask": "0x1" 2878 }, 2879 { 2880 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM", 2881 "Counter": "2", 2882 "EventCode": "0xB7", 2883 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", 2884 "MSRIndex": "0x1A6", 2885 "MSRValue": "0x3820", 2886 "SampleAfterValue": "100000", 2887 "UMask": "0x1" 2888 }, 2889 { 2890 "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache", 2891 "Counter": "2", 2892 "EventCode": "0xB7", 2893 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", 2894 "MSRIndex": "0x1A6", 2895 "MSRValue": "0x1020", 2896 "SampleAfterValue": "100000", 2897 "UMask": "0x1" 2898 }, 2899 { 2900 "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache", 2901 "Counter": "2", 2902 "EventCode": "0xB7", 2903 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", 2904 "MSRIndex": "0x1A6", 2905 "MSRValue": "0x820", 2906 "SampleAfterValue": "100000", 2907 "UMask": "0x1" 2908 }, 2909 { 2910 "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.", 2911 "Counter": "2", 2912 "EventCode": "0xB7", 2913 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", 2914 "MSRIndex": "0x1A6", 2915 "MSRValue": "0x7F70", 2916 "SampleAfterValue": "100000", 2917 "UMask": "0x1" 2918 }, 2919 { 2920 "BriefDescription": "All offcore prefetch requests", 2921 "Counter": "2", 2922 "EventCode": "0xB7", 2923 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", 2924 "MSRIndex": "0x1A6", 2925 "MSRValue": "0xFF70", 2926 "SampleAfterValue": "100000", 2927 "UMask": "0x1" 2928 }, 2929 { 2930 "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit", 2931 "Counter": "2", 2932 "EventCode": "0xB7", 2933 "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", 2934 "MSRIndex": "0x1A6", 2935 "MSRValue": "0x8070", 2936 "SampleAfterValue": "100000", 2937 "UMask": "0x1" 2938 }, 2939 { 2940 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core", 2941 "Counter": "2", 2942 "EventCode": "0xB7", 2943 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", 2944 "MSRIndex": "0x1A6", 2945 "MSRValue": "0x170", 2946 "SampleAfterValue": "100000", 2947 "UMask": "0x1" 2948 }, 2949 { 2950 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", 2951 "Counter": "2", 2952 "EventCode": "0xB7", 2953 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", 2954 "MSRIndex": "0x1A6", 2955 "MSRValue": "0x270", 2956 "SampleAfterValue": "100000", 2957 "UMask": "0x1" 2958 }, 2959 { 2960 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", 2961 "Counter": "2", 2962 "EventCode": "0xB7", 2963 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", 2964 "MSRIndex": "0x1A6", 2965 "MSRValue": "0x470", 2966 "SampleAfterValue": "100000", 2967 "UMask": "0x1" 2968 }, 2969 { 2970 "BriefDescription": "Offcore prefetch requests satisfied by the LLC", 2971 "Counter": "2", 2972 "EventCode": "0xB7", 2973 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", 2974 "MSRIndex": "0x1A6", 2975 "MSRValue": "0x770", 2976 "SampleAfterValue": "100000", 2977 "UMask": "0x1" 2978 }, 2979 { 2980 "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM", 2981 "Counter": "2", 2982 "EventCode": "0xB7", 2983 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", 2984 "MSRIndex": "0x1A6", 2985 "MSRValue": "0x4770", 2986 "SampleAfterValue": "100000", 2987 "UMask": "0x1" 2988 }, 2989 { 2990 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache", 2991 "Counter": "2", 2992 "EventCode": "0xB7", 2993 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", 2994 "MSRIndex": "0x1A6", 2995 "MSRValue": "0x1870", 2996 "SampleAfterValue": "100000", 2997 "UMask": "0x1" 2998 }, 2999 { 3000 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM", 3001 "Counter": "2", 3002 "EventCode": "0xB7", 3003 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", 3004 "MSRIndex": "0x1A6", 3005 "MSRValue": "0x3870", 3006 "SampleAfterValue": "100000", 3007 "UMask": "0x1" 3008 }, 3009 { 3010 "BriefDescription": "Offcore prefetch requests that HIT in a remote cache", 3011 "Counter": "2", 3012 "EventCode": "0xB7", 3013 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", 3014 "MSRIndex": "0x1A6", 3015 "MSRValue": "0x1070", 3016 "SampleAfterValue": "100000", 3017 "UMask": "0x1" 3018 }, 3019 { 3020 "BriefDescription": "Offcore prefetch requests that HITM in a remote cache", 3021 "Counter": "2", 3022 "EventCode": "0xB7", 3023 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", 3024 "MSRIndex": "0x1A6", 3025 "MSRValue": "0x870", 3026 "SampleAfterValue": "100000", 3027 "UMask": "0x1" 3028 }, 3029 { 3030 "BriefDescription": "Super Queue LRU hints sent to LLC", 3031 "Counter": "0,1,2,3", 3032 "EventCode": "0xF4", 3033 "EventName": "SQ_MISC.LRU_HINTS", 3034 "SampleAfterValue": "2000000", 3035 "UMask": "0x4" 3036 }, 3037 { 3038 "BriefDescription": "Super Queue lock splits across a cache line", 3039 "Counter": "0,1,2,3", 3040 "EventCode": "0xF4", 3041 "EventName": "SQ_MISC.SPLIT_LOCK", 3042 "SampleAfterValue": "2000000", 3043 "UMask": "0x10" 3044 }, 3045 { 3046 "BriefDescription": "Loads delayed with at-Retirement block code", 3047 "Counter": "0,1,2,3", 3048 "EventCode": "0x6", 3049 "EventName": "STORE_BLOCKS.AT_RET", 3050 "SampleAfterValue": "200000", 3051 "UMask": "0x4" 3052 }, 3053 { 3054 "BriefDescription": "Cacheable loads delayed with L1D block code", 3055 "Counter": "0,1,2,3", 3056 "EventCode": "0x6", 3057 "EventName": "STORE_BLOCKS.L1D_BLOCK", 3058 "SampleAfterValue": "200000", 3059 "UMask": "0x8" 3060 } 3061]
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