FILE
cache.json
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linux-6.19.14/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json
1[ 2 { 3 "BriefDescription": "Cycles L1D locked", 4 "Counter": "0,1", 5 "EventCode": "0x63", 6 "EventName": "CACHE_LOCK_CYCLES.L1D", 7 "SampleAfterValue": "2000000", 8 "UMask": "0x2" 9 }, 10 { 11 "BriefDescription": "Cycles L1D and L2 locked", 12 "Counter": "0,1", 13 "EventCode": "0x63", 14 "EventName": "CACHE_LOCK_CYCLES.L1D_L2", 15 "SampleAfterValue": "2000000", 16 "UMask": "0x1" 17 }, 18 { 19 "BriefDescription": "L1D cache lines replaced in M state", 20 "Counter": "0,1", 21 "EventCode": "0x51", 22 "EventName": "L1D.M_EVICT", 23 "SampleAfterValue": "2000000", 24 "UMask": "0x4" 25 }, 26 { 27 "BriefDescription": "L1D cache lines allocated in the M state", 28 "Counter": "0,1", 29 "EventCode": "0x51", 30 "EventName": "L1D.M_REPL", 31 "SampleAfterValue": "2000000", 32 "UMask": "0x2" 33 }, 34 { 35 "BriefDescription": "L1D snoop eviction of cache lines in M state", 36 "Counter": "0,1", 37 "EventCode": "0x51", 38 "EventName": "L1D.M_SNOOP_EVICT", 39 "SampleAfterValue": "2000000", 40 "UMask": "0x8" 41 }, 42 { 43 "BriefDescription": "L1 data cache lines allocated", 44 "Counter": "0,1", 45 "EventCode": "0x51", 46 "EventName": "L1D.REPL", 47 "SampleAfterValue": "2000000", 48 "UMask": "0x1" 49 }, 50 { 51 "BriefDescription": "L1D prefetch load lock accepted in fill buffer", 52 "Counter": "0,1", 53 "EventCode": "0x52", 54 "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", 55 "SampleAfterValue": "2000000", 56 "UMask": "0x1" 57 }, 58 { 59 "BriefDescription": "L1D hardware prefetch misses", 60 "Counter": "0,1", 61 "EventCode": "0x4E", 62 "EventName": "L1D_PREFETCH.MISS", 63 "SampleAfterValue": "200000", 64 "UMask": "0x2" 65 }, 66 { 67 "BriefDescription": "L1D hardware prefetch requests", 68 "Counter": "0,1", 69 "EventCode": "0x4E", 70 "EventName": "L1D_PREFETCH.REQUESTS", 71 "SampleAfterValue": "200000", 72 "UMask": "0x1" 73 }, 74 { 75 "BriefDescription": "L1D hardware prefetch requests triggered", 76 "Counter": "0,1", 77 "EventCode": "0x4E", 78 "EventName": "L1D_PREFETCH.TRIGGERS", 79 "SampleAfterValue": "200000", 80 "UMask": "0x4" 81 }, 82 { 83 "BriefDescription": "L1 writebacks to L2 in E state", 84 "Counter": "0,1,2,3", 85 "EventCode": "0x28", 86 "EventName": "L1D_WB_L2.E_STATE", 87 "SampleAfterValue": "100000", 88 "UMask": "0x4" 89 }, 90 { 91 "BriefDescription": "L1 writebacks to L2 in I state (misses)", 92 "Counter": "0,1,2,3", 93 "EventCode": "0x28", 94 "EventName": "L1D_WB_L2.I_STATE", 95 "SampleAfterValue": "100000", 96 "UMask": "0x1" 97 }, 98 { 99 "BriefDescription": "All L1 writebacks to L2", 100 "Counter": "0,1,2,3", 101 "EventCode": "0x28", 102 "EventName": "L1D_WB_L2.MESI", 103 "SampleAfterValue": "100000", 104 "UMask": "0xf" 105 }, 106 { 107 "BriefDescription": "L1 writebacks to L2 in M state", 108 "Counter": "0,1,2,3", 109 "EventCode": "0x28", 110 "EventName": "L1D_WB_L2.M_STATE", 111 "SampleAfterValue": "100000", 112 "UMask": "0x8" 113 }, 114 { 115 "BriefDescription": "L1 writebacks to L2 in S state", 116 "Counter": "0,1,2,3", 117 "EventCode": "0x28", 118 "EventName": "L1D_WB_L2.S_STATE", 119 "SampleAfterValue": "100000", 120 "UMask": "0x2" 121 }, 122 { 123 "BriefDescription": "L1I instruction fetch stall cycles", 124 "Counter": "0,1,2,3", 125 "EventCode": "0x80", 126 "EventName": "L1I.CYCLES_STALLED", 127 "SampleAfterValue": "2000000", 128 "UMask": "0x4" 129 }, 130 { 131 "BriefDescription": "L1I instruction fetch hits", 132 "Counter": "0,1,2,3", 133 "EventCode": "0x80", 134 "EventName": "L1I.HITS", 135 "SampleAfterValue": "2000000", 136 "UMask": "0x1" 137 }, 138 { 139 "BriefDescription": "L1I instruction fetch misses", 140 "Counter": "0,1,2,3", 141 "EventCode": "0x80", 142 "EventName": "L1I.MISSES", 143 "SampleAfterValue": "2000000", 144 "UMask": "0x2" 145 }, 146 { 147 "BriefDescription": "L1I Instruction fetches", 148 "Counter": "0,1,2,3", 149 "EventCode": "0x80", 150 "EventName": "L1I.READS", 151 "SampleAfterValue": "2000000", 152 "UMask": "0x3" 153 }, 154 { 155 "BriefDescription": "All L2 data requests", 156 "Counter": "0,1,2,3", 157 "EventCode": "0x26", 158 "EventName": "L2_DATA_RQSTS.ANY", 159 "SampleAfterValue": "200000", 160 "UMask": "0xff" 161 }, 162 { 163 "BriefDescription": "L2 data demand loads in E state", 164 "Counter": "0,1,2,3", 165 "EventCode": "0x26", 166 "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", 167 "SampleAfterValue": "200000", 168 "UMask": "0x4" 169 }, 170 { 171 "BriefDescription": "L2 data demand loads in I state (misses)", 172 "Counter": "0,1,2,3", 173 "EventCode": "0x26", 174 "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", 175 "SampleAfterValue": "200000", 176 "UMask": "0x1" 177 }, 178 { 179 "BriefDescription": "L2 data demand requests", 180 "Counter": "0,1,2,3", 181 "EventCode": "0x26", 182 "EventName": "L2_DATA_RQSTS.DEMAND.MESI", 183 "SampleAfterValue": "200000", 184 "UMask": "0xf" 185 }, 186 { 187 "BriefDescription": "L2 data demand loads in M state", 188 "Counter": "0,1,2,3", 189 "EventCode": "0x26", 190 "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", 191 "SampleAfterValue": "200000", 192 "UMask": "0x8" 193 }, 194 { 195 "BriefDescription": "L2 data demand loads in S state", 196 "Counter": "0,1,2,3", 197 "EventCode": "0x26", 198 "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", 199 "SampleAfterValue": "200000", 200 "UMask": "0x2" 201 }, 202 { 203 "BriefDescription": "L2 data prefetches in E state", 204 "Counter": "0,1,2,3", 205 "EventCode": "0x26", 206 "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", 207 "SampleAfterValue": "200000", 208 "UMask": "0x40" 209 }, 210 { 211 "BriefDescription": "L2 data prefetches in the I state (misses)", 212 "Counter": "0,1,2,3", 213 "EventCode": "0x26", 214 "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", 215 "SampleAfterValue": "200000", 216 "UMask": "0x10" 217 }, 218 { 219 "BriefDescription": "All L2 data prefetches", 220 "Counter": "0,1,2,3", 221 "EventCode": "0x26", 222 "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", 223 "SampleAfterValue": "200000", 224 "UMask": "0xf0" 225 }, 226 { 227 "BriefDescription": "L2 data prefetches in M state", 228 "Counter": "0,1,2,3", 229 "EventCode": "0x26", 230 "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", 231 "SampleAfterValue": "200000", 232 "UMask": "0x80" 233 }, 234 { 235 "BriefDescription": "L2 data prefetches in the S state", 236 "Counter": "0,1,2,3", 237 "EventCode": "0x26", 238 "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", 239 "SampleAfterValue": "200000", 240 "UMask": "0x20" 241 }, 242 { 243 "BriefDescription": "L2 lines allocated", 244 "Counter": "0,1,2,3", 245 "EventCode": "0xF1", 246 "EventName": "L2_LINES_IN.ANY", 247 "SampleAfterValue": "100000", 248 "UMask": "0x7" 249 }, 250 { 251 "BriefDescription": "L2 lines allocated in the E state", 252 "Counter": "0,1,2,3", 253 "EventCode": "0xF1", 254 "EventName": "L2_LINES_IN.E_STATE", 255 "SampleAfterValue": "100000", 256 "UMask": "0x4" 257 }, 258 { 259 "BriefDescription": "L2 lines allocated in the S state", 260 "Counter": "0,1,2,3", 261 "EventCode": "0xF1", 262 "EventName": "L2_LINES_IN.S_STATE", 263 "SampleAfterValue": "100000", 264 "UMask": "0x2" 265 }, 266 { 267 "BriefDescription": "L2 lines evicted", 268 "Counter": "0,1,2,3", 269 "EventCode": "0xF2", 270 "EventName": "L2_LINES_OUT.ANY", 271 "SampleAfterValue": "100000", 272 "UMask": "0xf" 273 }, 274 { 275 "BriefDescription": "L2 lines evicted by a demand request", 276 "Counter": "0,1,2,3", 277 "EventCode": "0xF2", 278 "EventName": "L2_LINES_OUT.DEMAND_CLEAN", 279 "SampleAfterValue": "100000", 280 "UMask": "0x1" 281 }, 282 { 283 "BriefDescription": "L2 modified lines evicted by a demand request", 284 "Counter": "0,1,2,3", 285 "EventCode": "0xF2", 286 "EventName": "L2_LINES_OUT.DEMAND_DIRTY", 287 "SampleAfterValue": "100000", 288 "UMask": "0x2" 289 }, 290 { 291 "BriefDescription": "L2 lines evicted by a prefetch request", 292 "Counter": "0,1,2,3", 293 "EventCode": "0xF2", 294 "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", 295 "SampleAfterValue": "100000", 296 "UMask": "0x4" 297 }, 298 { 299 "BriefDescription": "L2 modified lines evicted by a prefetch request", 300 "Counter": "0,1,2,3", 301 "EventCode": "0xF2", 302 "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", 303 "SampleAfterValue": "100000", 304 "UMask": "0x8" 305 }, 306 { 307 "BriefDescription": "L2 instruction fetches", 308 "Counter": "0,1,2,3", 309 "EventCode": "0x24", 310 "EventName": "L2_RQSTS.IFETCHES", 311 "SampleAfterValue": "200000", 312 "UMask": "0x30" 313 }, 314 { 315 "BriefDescription": "L2 instruction fetch hits", 316 "Counter": "0,1,2,3", 317 "EventCode": "0x24", 318 "EventName": "L2_RQSTS.IFETCH_HIT", 319 "SampleAfterValue": "200000", 320 "UMask": "0x10" 321 }, 322 { 323 "BriefDescription": "L2 instruction fetch misses", 324 "Counter": "0,1,2,3", 325 "EventCode": "0x24", 326 "EventName": "L2_RQSTS.IFETCH_MISS", 327 "SampleAfterValue": "200000", 328 "UMask": "0x20" 329 }, 330 { 331 "BriefDescription": "L2 load hits", 332 "Counter": "0,1,2,3", 333 "EventCode": "0x24", 334 "EventName": "L2_RQSTS.LD_HIT", 335 "SampleAfterValue": "200000", 336 "UMask": "0x1" 337 }, 338 { 339 "BriefDescription": "L2 load misses", 340 "Counter": "0,1,2,3", 341 "EventCode": "0x24", 342 "EventName": "L2_RQSTS.LD_MISS", 343 "SampleAfterValue": "200000", 344 "UMask": "0x2" 345 }, 346 { 347 "BriefDescription": "L2 requests", 348 "Counter": "0,1,2,3", 349 "EventCode": "0x24", 350 "EventName": "L2_RQSTS.LOADS", 351 "SampleAfterValue": "200000", 352 "UMask": "0x3" 353 }, 354 { 355 "BriefDescription": "All L2 misses", 356 "Counter": "0,1,2,3", 357 "EventCode": "0x24", 358 "EventName": "L2_RQSTS.MISS", 359 "SampleAfterValue": "200000", 360 "UMask": "0xaa" 361 }, 362 { 363 "BriefDescription": "All L2 prefetches", 364 "Counter": "0,1,2,3", 365 "EventCode": "0x24", 366 "EventName": "L2_RQSTS.PREFETCHES", 367 "SampleAfterValue": "200000", 368 "UMask": "0xc0" 369 }, 370 { 371 "BriefDescription": "L2 prefetch hits", 372 "Counter": "0,1,2,3", 373 "EventCode": "0x24", 374 "EventName": "L2_RQSTS.PREFETCH_HIT", 375 "SampleAfterValue": "200000", 376 "UMask": "0x40" 377 }, 378 { 379 "BriefDescription": "L2 prefetch misses", 380 "Counter": "0,1,2,3", 381 "EventCode": "0x24", 382 "EventName": "L2_RQSTS.PREFETCH_MISS", 383 "SampleAfterValue": "200000", 384 "UMask": "0x80" 385 }, 386 { 387 "BriefDescription": "All L2 requests", 388 "Counter": "0,1,2,3", 389 "EventCode": "0x24", 390 "EventName": "L2_RQSTS.REFERENCES", 391 "SampleAfterValue": "200000", 392 "UMask": "0xff" 393 }, 394 { 395 "BriefDescription": "L2 RFO requests", 396 "Counter": "0,1,2,3", 397 "EventCode": "0x24", 398 "EventName": "L2_RQSTS.RFOS", 399 "SampleAfterValue": "200000", 400 "UMask": "0xc" 401 }, 402 { 403 "BriefDescription": "L2 RFO hits", 404 "Counter": "0,1,2,3", 405 "EventCode": "0x24", 406 "EventName": "L2_RQSTS.RFO_HIT", 407 "SampleAfterValue": "200000", 408 "UMask": "0x4" 409 }, 410 { 411 "BriefDescription": "L2 RFO misses", 412 "Counter": "0,1,2,3", 413 "EventCode": "0x24", 414 "EventName": "L2_RQSTS.RFO_MISS", 415 "SampleAfterValue": "200000", 416 "UMask": "0x8" 417 }, 418 { 419 "BriefDescription": "All L2 transactions", 420 "Counter": "0,1,2,3", 421 "EventCode": "0xF0", 422 "EventName": "L2_TRANSACTIONS.ANY", 423 "SampleAfterValue": "200000", 424 "UMask": "0x80" 425 }, 426 { 427 "BriefDescription": "L2 fill transactions", 428 "Counter": "0,1,2,3", 429 "EventCode": "0xF0", 430 "EventName": "L2_TRANSACTIONS.FILL", 431 "SampleAfterValue": "200000", 432 "UMask": "0x20" 433 }, 434 { 435 "BriefDescription": "L2 instruction fetch transactions", 436 "Counter": "0,1,2,3", 437 "EventCode": "0xF0", 438 "EventName": "L2_TRANSACTIONS.IFETCH", 439 "SampleAfterValue": "200000", 440 "UMask": "0x4" 441 }, 442 { 443 "BriefDescription": "L1D writeback to L2 transactions", 444 "Counter": "0,1,2,3", 445 "EventCode": "0xF0", 446 "EventName": "L2_TRANSACTIONS.L1D_WB", 447 "SampleAfterValue": "200000", 448 "UMask": "0x10" 449 }, 450 { 451 "BriefDescription": "L2 Load transactions", 452 "Counter": "0,1,2,3", 453 "EventCode": "0xF0", 454 "EventName": "L2_TRANSACTIONS.LOAD", 455 "SampleAfterValue": "200000", 456 "UMask": "0x1" 457 }, 458 { 459 "BriefDescription": "L2 prefetch transactions", 460 "Counter": "0,1,2,3", 461 "EventCode": "0xF0", 462 "EventName": "L2_TRANSACTIONS.PREFETCH", 463 "SampleAfterValue": "200000", 464 "UMask": "0x8" 465 }, 466 { 467 "BriefDescription": "L2 RFO transactions", 468 "Counter": "0,1,2,3", 469 "EventCode": "0xF0", 470 "EventName": "L2_TRANSACTIONS.RFO", 471 "SampleAfterValue": "200000", 472 "UMask": "0x2" 473 }, 474 { 475 "BriefDescription": "L2 writeback to LLC transactions", 476 "Counter": "0,1,2,3", 477 "EventCode": "0xF0", 478 "EventName": "L2_TRANSACTIONS.WB", 479 "SampleAfterValue": "200000", 480 "UMask": "0x40" 481 }, 482 { 483 "BriefDescription": "L2 demand lock RFOs in E state", 484 "Counter": "0,1,2,3", 485 "EventCode": "0x27", 486 "EventName": "L2_WRITE.LOCK.E_STATE", 487 "SampleAfterValue": "100000", 488 "UMask": "0x40" 489 }, 490 { 491 "BriefDescription": "All demand L2 lock RFOs that hit the cache", 492 "Counter": "0,1,2,3", 493 "EventCode": "0x27", 494 "EventName": "L2_WRITE.LOCK.HIT", 495 "SampleAfterValue": "100000", 496 "UMask": "0xe0" 497 }, 498 { 499 "BriefDescription": "L2 demand lock RFOs in I state (misses)", 500 "Counter": "0,1,2,3", 501 "EventCode": "0x27", 502 "EventName": "L2_WRITE.LOCK.I_STATE", 503 "SampleAfterValue": "100000", 504 "UMask": "0x10" 505 }, 506 { 507 "BriefDescription": "All demand L2 lock RFOs", 508 "Counter": "0,1,2,3", 509 "EventCode": "0x27", 510 "EventName": "L2_WRITE.LOCK.MESI", 511 "SampleAfterValue": "100000", 512 "UMask": "0xf0" 513 }, 514 { 515 "BriefDescription": "L2 demand lock RFOs in M state", 516 "Counter": "0,1,2,3", 517 "EventCode": "0x27", 518 "EventName": "L2_WRITE.LOCK.M_STATE", 519 "SampleAfterValue": "100000", 520 "UMask": "0x80" 521 }, 522 { 523 "BriefDescription": "L2 demand lock RFOs in S state", 524 "Counter": "0,1,2,3", 525 "EventCode": "0x27", 526 "EventName": "L2_WRITE.LOCK.S_STATE", 527 "SampleAfterValue": "100000", 528 "UMask": "0x20" 529 }, 530 { 531 "BriefDescription": "All L2 demand store RFOs that hit the cache", 532 "Counter": "0,1,2,3", 533 "EventCode": "0x27", 534 "EventName": "L2_WRITE.RFO.HIT", 535 "SampleAfterValue": "100000", 536 "UMask": "0xe" 537 }, 538 { 539 "BriefDescription": "L2 demand store RFOs in I state (misses)", 540 "Counter": "0,1,2,3", 541 "EventCode": "0x27", 542 "EventName": "L2_WRITE.RFO.I_STATE", 543 "SampleAfterValue": "100000", 544 "UMask": "0x1" 545 }, 546 { 547 "BriefDescription": "All L2 demand store RFOs", 548 "Counter": "0,1,2,3", 549 "EventCode": "0x27", 550 "EventName": "L2_WRITE.RFO.MESI", 551 "SampleAfterValue": "100000", 552 "UMask": "0xf" 553 }, 554 { 555 "BriefDescription": "L2 demand store RFOs in M state", 556 "Counter": "0,1,2,3", 557 "EventCode": "0x27", 558 "EventName": "L2_WRITE.RFO.M_STATE", 559 "SampleAfterValue": "100000", 560 "UMask": "0x8" 561 }, 562 { 563 "BriefDescription": "L2 demand store RFOs in S state", 564 "Counter": "0,1,2,3", 565 "EventCode": "0x27", 566 "EventName": "L2_WRITE.RFO.S_STATE", 567 "SampleAfterValue": "100000", 568 "UMask": "0x2" 569 }, 570 { 571 "BriefDescription": "Longest latency cache miss", 572 "Counter": "0,1,2,3", 573 "EventCode": "0x2E", 574 "EventName": "LONGEST_LAT_CACHE.MISS", 575 "SampleAfterValue": "100000", 576 "UMask": "0x41" 577 }, 578 { 579 "BriefDescription": "Longest latency cache reference", 580 "Counter": "0,1,2,3", 581 "EventCode": "0x2E", 582 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 583 "SampleAfterValue": "200000", 584 "UMask": "0x4f" 585 }, 586 { 587 "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)", 588 "Counter": "3", 589 "EventCode": "0xB", 590 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", 591 "MSRIndex": "0x3F6", 592 "PEBS": "2", 593 "SampleAfterValue": "2000000", 594 "UMask": "0x10" 595 }, 596 { 597 "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)", 598 "Counter": "3", 599 "EventCode": "0xB", 600 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", 601 "MSRIndex": "0x3F6", 602 "MSRValue": "0x400", 603 "PEBS": "2", 604 "SampleAfterValue": "100", 605 "UMask": "0x10" 606 }, 607 { 608 "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)", 609 "Counter": "3", 610 "EventCode": "0xB", 611 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", 612 "MSRIndex": "0x3F6", 613 "MSRValue": "0x80", 614 "PEBS": "2", 615 "SampleAfterValue": "1000", 616 "UMask": "0x10" 617 }, 618 { 619 "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)", 620 "Counter": "3", 621 "EventCode": "0xB", 622 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", 623 "MSRIndex": "0x3F6", 624 "MSRValue": "0x10", 625 "PEBS": "2", 626 "SampleAfterValue": "10000", 627 "UMask": "0x10" 628 }, 629 { 630 "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)", 631 "Counter": "3", 632 "EventCode": "0xB", 633 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", 634 "MSRIndex": "0x3F6", 635 "MSRValue": "0x4000", 636 "PEBS": "2", 637 "SampleAfterValue": "5", 638 "UMask": "0x10" 639 }, 640 { 641 "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)", 642 "Counter": "3", 643 "EventCode": "0xB", 644 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", 645 "MSRIndex": "0x3F6", 646 "MSRValue": "0x800", 647 "PEBS": "2", 648 "SampleAfterValue": "50", 649 "UMask": "0x10" 650 }, 651 { 652 "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)", 653 "Counter": "3", 654 "EventCode": "0xB", 655 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", 656 "MSRIndex": "0x3F6", 657 "MSRValue": "0x100", 658 "PEBS": "2", 659 "SampleAfterValue": "500", 660 "UMask": "0x10" 661 }, 662 { 663 "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)", 664 "Counter": "3", 665 "EventCode": "0xB", 666 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", 667 "MSRIndex": "0x3F6", 668 "MSRValue": "0x20", 669 "PEBS": "2", 670 "SampleAfterValue": "5000", 671 "UMask": "0x10" 672 }, 673 { 674 "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)", 675 "Counter": "3", 676 "EventCode": "0xB", 677 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", 678 "MSRIndex": "0x3F6", 679 "MSRValue": "0x8000", 680 "PEBS": "2", 681 "SampleAfterValue": "3", 682 "UMask": "0x10" 683 }, 684 { 685 "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)", 686 "Counter": "3", 687 "EventCode": "0xB", 688 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", 689 "MSRIndex": "0x3F6", 690 "MSRValue": "0x4", 691 "PEBS": "2", 692 "SampleAfterValue": "50000", 693 "UMask": "0x10" 694 }, 695 { 696 "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)", 697 "Counter": "3", 698 "EventCode": "0xB", 699 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", 700 "MSRIndex": "0x3F6", 701 "MSRValue": "0x1000", 702 "PEBS": "2", 703 "SampleAfterValue": "20", 704 "UMask": "0x10" 705 }, 706 { 707 "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)", 708 "Counter": "3", 709 "EventCode": "0xB", 710 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", 711 "MSRIndex": "0x3F6", 712 "MSRValue": "0x200", 713 "PEBS": "2", 714 "SampleAfterValue": "200", 715 "UMask": "0x10" 716 }, 717 { 718 "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)", 719 "Counter": "3", 720 "EventCode": "0xB", 721 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", 722 "MSRIndex": "0x3F6", 723 "MSRValue": "0x40", 724 "PEBS": "2", 725 "SampleAfterValue": "2000", 726 "UMask": "0x10" 727 }, 728 { 729 "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)", 730 "Counter": "3", 731 "EventCode": "0xB", 732 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", 733 "MSRIndex": "0x3F6", 734 "MSRValue": "0x8", 735 "PEBS": "2", 736 "SampleAfterValue": "20000", 737 "UMask": "0x10" 738 }, 739 { 740 "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)", 741 "Counter": "3", 742 "EventCode": "0xB", 743 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", 744 "MSRIndex": "0x3F6", 745 "MSRValue": "0x2000", 746 "PEBS": "2", 747 "SampleAfterValue": "10", 748 "UMask": "0x10" 749 }, 750 { 751 "BriefDescription": "Instructions retired which contains a load (Precise Event)", 752 "Counter": "0,1,2,3", 753 "EventCode": "0xB", 754 "EventName": "MEM_INST_RETIRED.LOADS", 755 "PEBS": "1", 756 "SampleAfterValue": "2000000", 757 "UMask": "0x1" 758 }, 759 { 760 "BriefDescription": "Instructions retired which contains a store (Precise Event)", 761 "Counter": "0,1,2,3", 762 "EventCode": "0xB", 763 "EventName": "MEM_INST_RETIRED.STORES", 764 "PEBS": "1", 765 "SampleAfterValue": "2000000", 766 "UMask": "0x2" 767 }, 768 { 769 "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)", 770 "Counter": "0,1,2,3", 771 "EventCode": "0xCB", 772 "EventName": "MEM_LOAD_RETIRED.HIT_LFB", 773 "PEBS": "1", 774 "SampleAfterValue": "200000", 775 "UMask": "0x40" 776 }, 777 { 778 "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)", 779 "Counter": "0,1,2,3", 780 "EventCode": "0xCB", 781 "EventName": "MEM_LOAD_RETIRED.L1D_HIT", 782 "PEBS": "1", 783 "SampleAfterValue": "2000000", 784 "UMask": "0x1" 785 }, 786 { 787 "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)", 788 "Counter": "0,1,2,3", 789 "EventCode": "0xCB", 790 "EventName": "MEM_LOAD_RETIRED.L2_HIT", 791 "PEBS": "1", 792 "SampleAfterValue": "200000", 793 "UMask": "0x2" 794 }, 795 { 796 "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)", 797 "Counter": "0,1,2,3", 798 "EventCode": "0xCB", 799 "EventName": "MEM_LOAD_RETIRED.LLC_MISS", 800 "PEBS": "1", 801 "SampleAfterValue": "10000", 802 "UMask": "0x10" 803 }, 804 { 805 "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)", 806 "Counter": "0,1,2,3", 807 "EventCode": "0xCB", 808 "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", 809 "PEBS": "1", 810 "SampleAfterValue": "40000", 811 "UMask": "0x4" 812 }, 813 { 814 "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)", 815 "Counter": "0,1,2,3", 816 "EventCode": "0xCB", 817 "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", 818 "PEBS": "1", 819 "SampleAfterValue": "40000", 820 "UMask": "0x8" 821 }, 822 { 823 "BriefDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)", 824 "Counter": "0,1,2,3", 825 "EventCode": "0xF", 826 "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM", 827 "PEBS": "1", 828 "SampleAfterValue": "10000", 829 "UMask": "0x10" 830 }, 831 { 832 "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)", 833 "Counter": "0,1,2,3", 834 "EventCode": "0xF", 835 "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM", 836 "PEBS": "1", 837 "SampleAfterValue": "40000", 838 "UMask": "0x2" 839 }, 840 { 841 "BriefDescription": "Load instructions retired remote cache HIT data source (Precise Event)", 842 "Counter": "0,1,2,3", 843 "EventCode": "0xF", 844 "EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT", 845 "PEBS": "1", 846 "SampleAfterValue": "20000", 847 "UMask": "0x8" 848 }, 849 { 850 "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)", 851 "Counter": "0,1,2,3", 852 "EventCode": "0xF", 853 "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", 854 "PEBS": "1", 855 "SampleAfterValue": "10000", 856 "UMask": "0x20" 857 }, 858 { 859 "BriefDescription": "Load instructions retired IO (Precise Event)", 860 "Counter": "0,1,2,3", 861 "EventCode": "0xF", 862 "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", 863 "PEBS": "1", 864 "SampleAfterValue": "4000", 865 "UMask": "0x80" 866 }, 867 { 868 "BriefDescription": "All offcore requests", 869 "Counter": "0,1,2,3", 870 "EventCode": "0xB0", 871 "EventName": "OFFCORE_REQUESTS.ANY", 872 "SampleAfterValue": "100000", 873 "UMask": "0x80" 874 }, 875 { 876 "BriefDescription": "Offcore read requests", 877 "Counter": "0,1,2,3", 878 "EventCode": "0xB0", 879 "EventName": "OFFCORE_REQUESTS.ANY.READ", 880 "SampleAfterValue": "100000", 881 "UMask": "0x8" 882 }, 883 { 884 "BriefDescription": "Offcore RFO requests", 885 "Counter": "0,1,2,3", 886 "EventCode": "0xB0", 887 "EventName": "OFFCORE_REQUESTS.ANY.RFO", 888 "SampleAfterValue": "100000", 889 "UMask": "0x10" 890 }, 891 { 892 "BriefDescription": "Offcore demand code read requests", 893 "Counter": "0,1,2,3", 894 "EventCode": "0xB0", 895 "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE", 896 "SampleAfterValue": "100000", 897 "UMask": "0x2" 898 }, 899 { 900 "BriefDescription": "Offcore demand data read requests", 901 "Counter": "0,1,2,3", 902 "EventCode": "0xB0", 903 "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA", 904 "SampleAfterValue": "100000", 905 "UMask": "0x1" 906 }, 907 { 908 "BriefDescription": "Offcore demand RFO requests", 909 "Counter": "0,1,2,3", 910 "EventCode": "0xB0", 911 "EventName": "OFFCORE_REQUESTS.DEMAND.RFO", 912 "SampleAfterValue": "100000", 913 "UMask": "0x4" 914 }, 915 { 916 "BriefDescription": "Offcore L1 data cache writebacks", 917 "Counter": "0,1,2,3", 918 "EventCode": "0xB0", 919 "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", 920 "SampleAfterValue": "100000", 921 "UMask": "0x40" 922 }, 923 { 924 "BriefDescription": "Offcore uncached memory accesses", 925 "Counter": "0,1,2,3", 926 "EventCode": "0xB0", 927 "EventName": "OFFCORE_REQUESTS.UNCACHED_MEM", 928 "SampleAfterValue": "100000", 929 "UMask": "0x20" 930 }, 931 { 932 "BriefDescription": "Outstanding offcore reads", 933 "Counter": "0", 934 "EventCode": "0x60", 935 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", 936 "SampleAfterValue": "2000000", 937 "UMask": "0x8" 938 }, 939 { 940 "BriefDescription": "Cycles offcore reads busy", 941 "Counter": "0", 942 "CounterMask": "1", 943 "EventCode": "0x60", 944 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY", 945 "SampleAfterValue": "2000000", 946 "UMask": "0x8" 947 }, 948 { 949 "BriefDescription": "Outstanding offcore demand code reads", 950 "Counter": "0", 951 "EventCode": "0x60", 952 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", 953 "SampleAfterValue": "2000000", 954 "UMask": "0x2" 955 }, 956 { 957 "BriefDescription": "Cycles offcore demand code read busy", 958 "Counter": "0", 959 "CounterMask": "1", 960 "EventCode": "0x60", 961 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY", 962 "SampleAfterValue": "2000000", 963 "UMask": "0x2" 964 }, 965 { 966 "BriefDescription": "Outstanding offcore demand data reads", 967 "Counter": "0", 968 "EventCode": "0x60", 969 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", 970 "SampleAfterValue": "2000000", 971 "UMask": "0x1" 972 }, 973 { 974 "BriefDescription": "Cycles offcore demand data read busy", 975 "Counter": "0", 976 "CounterMask": "1", 977 "EventCode": "0x60", 978 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY", 979 "SampleAfterValue": "2000000", 980 "UMask": "0x1" 981 }, 982 { 983 "BriefDescription": "Outstanding offcore demand RFOs", 984 "Counter": "0", 985 "EventCode": "0x60", 986 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", 987 "SampleAfterValue": "2000000", 988 "UMask": "0x4" 989 }, 990 { 991 "BriefDescription": "Cycles offcore demand RFOs busy", 992 "Counter": "0", 993 "CounterMask": "1", 994 "EventCode": "0x60", 995 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", 996 "SampleAfterValue": "2000000", 997 "UMask": "0x4" 998 }, 999 { 1000 "BriefDescription": "Offcore requests blocked due to Super Queue full", 1001 "Counter": "0,1,2,3", 1002 "EventCode": "0xB2", 1003 "EventName": "OFFCORE_REQUESTS_SQ_FULL", 1004 "SampleAfterValue": "100000", 1005 "UMask": "0x1" 1006 }, 1007 { 1008 "BriefDescription": "Offcore data reads satisfied by any cache or DRAM", 1009 "Counter": "0,1,2,3", 1010 "EventCode": "0xB7, 0xBB", 1011 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", 1012 "MSRIndex": "0x1a6,0x1a7", 1013 "MSRValue": "0x7F11", 1014 "SampleAfterValue": "100000", 1015 "UMask": "0x1" 1016 }, 1017 { 1018 "BriefDescription": "All offcore data reads", 1019 "Counter": "0,1,2,3", 1020 "EventCode": "0xB7, 0xBB", 1021 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", 1022 "MSRIndex": "0x1a6,0x1a7", 1023 "MSRValue": "0xFF11", 1024 "SampleAfterValue": "100000", 1025 "UMask": "0x1" 1026 }, 1027 { 1028 "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", 1029 "Counter": "0,1,2,3", 1030 "EventCode": "0xB7, 0xBB", 1031 "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", 1032 "MSRIndex": "0x1a6,0x1a7", 1033 "MSRValue": "0x8011", 1034 "SampleAfterValue": "100000", 1035 "UMask": "0x1" 1036 }, 1037 { 1038 "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", 1039 "Counter": "0,1,2,3", 1040 "EventCode": "0xB7, 0xBB", 1041 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", 1042 "MSRIndex": "0x1a6,0x1a7", 1043 "MSRValue": "0x111", 1044 "SampleAfterValue": "100000", 1045 "UMask": "0x1" 1046 }, 1047 { 1048 "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", 1049 "Counter": "0,1,2,3", 1050 "EventCode": "0xB7, 0xBB", 1051 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", 1052 "MSRIndex": "0x1a6,0x1a7", 1053 "MSRValue": "0x211", 1054 "SampleAfterValue": "100000", 1055 "UMask": "0x1" 1056 }, 1057 { 1058 "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", 1059 "Counter": "0,1,2,3", 1060 "EventCode": "0xB7, 0xBB", 1061 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", 1062 "MSRIndex": "0x1a6,0x1a7", 1063 "MSRValue": "0x411", 1064 "SampleAfterValue": "100000", 1065 "UMask": "0x1" 1066 }, 1067 { 1068 "BriefDescription": "Offcore data reads satisfied by the LLC", 1069 "Counter": "0,1,2,3", 1070 "EventCode": "0xB7, 0xBB", 1071 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", 1072 "MSRIndex": "0x1a6,0x1a7", 1073 "MSRValue": "0x711", 1074 "SampleAfterValue": "100000", 1075 "UMask": "0x1" 1076 }, 1077 { 1078 "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM", 1079 "Counter": "0,1,2,3", 1080 "EventCode": "0xB7, 0xBB", 1081 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", 1082 "MSRIndex": "0x1a6,0x1a7", 1083 "MSRValue": "0x2711", 1084 "SampleAfterValue": "100000", 1085 "UMask": "0x1" 1086 }, 1087 { 1088 "BriefDescription": "Offcore data reads satisfied by a remote cache", 1089 "Counter": "0,1,2,3", 1090 "EventCode": "0xB7, 0xBB", 1091 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", 1092 "MSRIndex": "0x1a6,0x1a7", 1093 "MSRValue": "0x1811", 1094 "SampleAfterValue": "100000", 1095 "UMask": "0x1" 1096 }, 1097 { 1098 "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", 1099 "Counter": "0,1,2,3", 1100 "EventCode": "0xB7, 0xBB", 1101 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", 1102 "MSRIndex": "0x1a6,0x1a7", 1103 "MSRValue": "0x5811", 1104 "SampleAfterValue": "100000", 1105 "UMask": "0x1" 1106 }, 1107 { 1108 "BriefDescription": "Offcore data reads that HIT in a remote cache", 1109 "Counter": "0,1,2,3", 1110 "EventCode": "0xB7, 0xBB", 1111 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", 1112 "MSRIndex": "0x1a6,0x1a7", 1113 "MSRValue": "0x1011", 1114 "SampleAfterValue": "100000", 1115 "UMask": "0x1" 1116 }, 1117 { 1118 "BriefDescription": "Offcore data reads that HITM in a remote cache", 1119 "Counter": "0,1,2,3", 1120 "EventCode": "0xB7, 0xBB", 1121 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", 1122 "MSRIndex": "0x1a6,0x1a7", 1123 "MSRValue": "0x811", 1124 "SampleAfterValue": "100000", 1125 "UMask": "0x1" 1126 }, 1127 { 1128 "BriefDescription": "Offcore code reads satisfied by any cache or DRAM", 1129 "Counter": "0,1,2,3", 1130 "EventCode": "0xB7, 0xBB", 1131 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", 1132 "MSRIndex": "0x1a6,0x1a7", 1133 "MSRValue": "0x7F44", 1134 "SampleAfterValue": "100000", 1135 "UMask": "0x1" 1136 }, 1137 { 1138 "BriefDescription": "All offcore code reads", 1139 "Counter": "0,1,2,3", 1140 "EventCode": "0xB7, 0xBB", 1141 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", 1142 "MSRIndex": "0x1a6,0x1a7", 1143 "MSRValue": "0xFF44", 1144 "SampleAfterValue": "100000", 1145 "UMask": "0x1" 1146 }, 1147 { 1148 "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", 1149 "Counter": "0,1,2,3", 1150 "EventCode": "0xB7, 0xBB", 1151 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", 1152 "MSRIndex": "0x1a6,0x1a7", 1153 "MSRValue": "0x8044", 1154 "SampleAfterValue": "100000", 1155 "UMask": "0x1" 1156 }, 1157 { 1158 "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", 1159 "Counter": "0,1,2,3", 1160 "EventCode": "0xB7, 0xBB", 1161 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", 1162 "MSRIndex": "0x1a6,0x1a7", 1163 "MSRValue": "0x144", 1164 "SampleAfterValue": "100000", 1165 "UMask": "0x1" 1166 }, 1167 { 1168 "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", 1169 "Counter": "0,1,2,3", 1170 "EventCode": "0xB7, 0xBB", 1171 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1172 "MSRIndex": "0x1a6,0x1a7", 1173 "MSRValue": "0x244", 1174 "SampleAfterValue": "100000", 1175 "UMask": "0x1" 1176 }, 1177 { 1178 "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", 1179 "Counter": "0,1,2,3", 1180 "EventCode": "0xB7, 0xBB", 1181 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1182 "MSRIndex": "0x1a6,0x1a7", 1183 "MSRValue": "0x444", 1184 "SampleAfterValue": "100000", 1185 "UMask": "0x1" 1186 }, 1187 { 1188 "BriefDescription": "Offcore code reads satisfied by the LLC", 1189 "Counter": "0,1,2,3", 1190 "EventCode": "0xB7, 0xBB", 1191 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", 1192 "MSRIndex": "0x1a6,0x1a7", 1193 "MSRValue": "0x744", 1194 "SampleAfterValue": "100000", 1195 "UMask": "0x1" 1196 }, 1197 { 1198 "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM", 1199 "Counter": "0,1,2,3", 1200 "EventCode": "0xB7, 0xBB", 1201 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", 1202 "MSRIndex": "0x1a6,0x1a7", 1203 "MSRValue": "0x2744", 1204 "SampleAfterValue": "100000", 1205 "UMask": "0x1" 1206 }, 1207 { 1208 "BriefDescription": "Offcore code reads satisfied by a remote cache", 1209 "Counter": "0,1,2,3", 1210 "EventCode": "0xB7, 0xBB", 1211 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", 1212 "MSRIndex": "0x1a6,0x1a7", 1213 "MSRValue": "0x1844", 1214 "SampleAfterValue": "100000", 1215 "UMask": "0x1" 1216 }, 1217 { 1218 "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", 1219 "Counter": "0,1,2,3", 1220 "EventCode": "0xB7, 0xBB", 1221 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", 1222 "MSRIndex": "0x1a6,0x1a7", 1223 "MSRValue": "0x5844", 1224 "SampleAfterValue": "100000", 1225 "UMask": "0x1" 1226 }, 1227 { 1228 "BriefDescription": "Offcore code reads that HIT in a remote cache", 1229 "Counter": "0,1,2,3", 1230 "EventCode": "0xB7, 0xBB", 1231 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", 1232 "MSRIndex": "0x1a6,0x1a7", 1233 "MSRValue": "0x1044", 1234 "SampleAfterValue": "100000", 1235 "UMask": "0x1" 1236 }, 1237 { 1238 "BriefDescription": "Offcore code reads that HITM in a remote cache", 1239 "Counter": "0,1,2,3", 1240 "EventCode": "0xB7, 0xBB", 1241 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", 1242 "MSRIndex": "0x1a6,0x1a7", 1243 "MSRValue": "0x844", 1244 "SampleAfterValue": "100000", 1245 "UMask": "0x1" 1246 }, 1247 { 1248 "BriefDescription": "Offcore requests satisfied by any cache or DRAM", 1249 "Counter": "0,1,2,3", 1250 "EventCode": "0xB7, 0xBB", 1251 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", 1252 "MSRIndex": "0x1a6,0x1a7", 1253 "MSRValue": "0x7FFF", 1254 "SampleAfterValue": "100000", 1255 "UMask": "0x1" 1256 }, 1257 { 1258 "BriefDescription": "All offcore requests", 1259 "Counter": "0,1,2,3", 1260 "EventCode": "0xB7, 0xBB", 1261 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", 1262 "MSRIndex": "0x1a6,0x1a7", 1263 "MSRValue": "0xFFFF", 1264 "SampleAfterValue": "100000", 1265 "UMask": "0x1" 1266 }, 1267 { 1268 "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", 1269 "Counter": "0,1,2,3", 1270 "EventCode": "0xB7, 0xBB", 1271 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", 1272 "MSRIndex": "0x1a6,0x1a7", 1273 "MSRValue": "0x80FF", 1274 "SampleAfterValue": "100000", 1275 "UMask": "0x1" 1276 }, 1277 { 1278 "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", 1279 "Counter": "0,1,2,3", 1280 "EventCode": "0xB7, 0xBB", 1281 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", 1282 "MSRIndex": "0x1a6,0x1a7", 1283 "MSRValue": "0x1FF", 1284 "SampleAfterValue": "100000", 1285 "UMask": "0x1" 1286 }, 1287 { 1288 "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", 1289 "Counter": "0,1,2,3", 1290 "EventCode": "0xB7, 0xBB", 1291 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", 1292 "MSRIndex": "0x1a6,0x1a7", 1293 "MSRValue": "0x2FF", 1294 "SampleAfterValue": "100000", 1295 "UMask": "0x1" 1296 }, 1297 { 1298 "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", 1299 "Counter": "0,1,2,3", 1300 "EventCode": "0xB7, 0xBB", 1301 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", 1302 "MSRIndex": "0x1a6,0x1a7", 1303 "MSRValue": "0x4FF", 1304 "SampleAfterValue": "100000", 1305 "UMask": "0x1" 1306 }, 1307 { 1308 "BriefDescription": "Offcore requests satisfied by the LLC", 1309 "Counter": "0,1,2,3", 1310 "EventCode": "0xB7, 0xBB", 1311 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", 1312 "MSRIndex": "0x1a6,0x1a7", 1313 "MSRValue": "0x7FF", 1314 "SampleAfterValue": "100000", 1315 "UMask": "0x1" 1316 }, 1317 { 1318 "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM", 1319 "Counter": "0,1,2,3", 1320 "EventCode": "0xB7, 0xBB", 1321 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", 1322 "MSRIndex": "0x1a6,0x1a7", 1323 "MSRValue": "0x27FF", 1324 "SampleAfterValue": "100000", 1325 "UMask": "0x1" 1326 }, 1327 { 1328 "BriefDescription": "Offcore requests satisfied by a remote cache", 1329 "Counter": "0,1,2,3", 1330 "EventCode": "0xB7, 0xBB", 1331 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", 1332 "MSRIndex": "0x1a6,0x1a7", 1333 "MSRValue": "0x18FF", 1334 "SampleAfterValue": "100000", 1335 "UMask": "0x1" 1336 }, 1337 { 1338 "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM", 1339 "Counter": "0,1,2,3", 1340 "EventCode": "0xB7, 0xBB", 1341 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", 1342 "MSRIndex": "0x1a6,0x1a7", 1343 "MSRValue": "0x58FF", 1344 "SampleAfterValue": "100000", 1345 "UMask": "0x1" 1346 }, 1347 { 1348 "BriefDescription": "Offcore requests that HIT in a remote cache", 1349 "Counter": "0,1,2,3", 1350 "EventCode": "0xB7, 0xBB", 1351 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", 1352 "MSRIndex": "0x1a6,0x1a7", 1353 "MSRValue": "0x10FF", 1354 "SampleAfterValue": "100000", 1355 "UMask": "0x1" 1356 }, 1357 { 1358 "BriefDescription": "Offcore requests that HITM in a remote cache", 1359 "Counter": "0,1,2,3", 1360 "EventCode": "0xB7, 0xBB", 1361 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", 1362 "MSRIndex": "0x1a6,0x1a7", 1363 "MSRValue": "0x8FF", 1364 "SampleAfterValue": "100000", 1365 "UMask": "0x1" 1366 }, 1367 { 1368 "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM", 1369 "Counter": "0,1,2,3", 1370 "EventCode": "0xB7, 0xBB", 1371 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", 1372 "MSRIndex": "0x1a6,0x1a7", 1373 "MSRValue": "0x7F22", 1374 "SampleAfterValue": "100000", 1375 "UMask": "0x1" 1376 }, 1377 { 1378 "BriefDescription": "All offcore RFO requests", 1379 "Counter": "0,1,2,3", 1380 "EventCode": "0xB7, 0xBB", 1381 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", 1382 "MSRIndex": "0x1a6,0x1a7", 1383 "MSRValue": "0xFF22", 1384 "SampleAfterValue": "100000", 1385 "UMask": "0x1" 1386 }, 1387 { 1388 "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", 1389 "Counter": "0,1,2,3", 1390 "EventCode": "0xB7, 0xBB", 1391 "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", 1392 "MSRIndex": "0x1a6,0x1a7", 1393 "MSRValue": "0x8022", 1394 "SampleAfterValue": "100000", 1395 "UMask": "0x1" 1396 }, 1397 { 1398 "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", 1399 "Counter": "0,1,2,3", 1400 "EventCode": "0xB7, 0xBB", 1401 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", 1402 "MSRIndex": "0x1a6,0x1a7", 1403 "MSRValue": "0x122", 1404 "SampleAfterValue": "100000", 1405 "UMask": "0x1" 1406 }, 1407 { 1408 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", 1409 "Counter": "0,1,2,3", 1410 "EventCode": "0xB7, 0xBB", 1411 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", 1412 "MSRIndex": "0x1a6,0x1a7", 1413 "MSRValue": "0x222", 1414 "SampleAfterValue": "100000", 1415 "UMask": "0x1" 1416 }, 1417 { 1418 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", 1419 "Counter": "0,1,2,3", 1420 "EventCode": "0xB7, 0xBB", 1421 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", 1422 "MSRIndex": "0x1a6,0x1a7", 1423 "MSRValue": "0x422", 1424 "SampleAfterValue": "100000", 1425 "UMask": "0x1" 1426 }, 1427 { 1428 "BriefDescription": "Offcore RFO requests satisfied by the LLC", 1429 "Counter": "0,1,2,3", 1430 "EventCode": "0xB7, 0xBB", 1431 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", 1432 "MSRIndex": "0x1a6,0x1a7", 1433 "MSRValue": "0x722", 1434 "SampleAfterValue": "100000", 1435 "UMask": "0x1" 1436 }, 1437 { 1438 "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", 1439 "Counter": "0,1,2,3", 1440 "EventCode": "0xB7, 0xBB", 1441 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", 1442 "MSRIndex": "0x1a6,0x1a7", 1443 "MSRValue": "0x2722", 1444 "SampleAfterValue": "100000", 1445 "UMask": "0x1" 1446 }, 1447 { 1448 "BriefDescription": "Offcore RFO requests satisfied by a remote cache", 1449 "Counter": "0,1,2,3", 1450 "EventCode": "0xB7, 0xBB", 1451 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", 1452 "MSRIndex": "0x1a6,0x1a7", 1453 "MSRValue": "0x1822", 1454 "SampleAfterValue": "100000", 1455 "UMask": "0x1" 1456 }, 1457 { 1458 "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", 1459 "Counter": "0,1,2,3", 1460 "EventCode": "0xB7, 0xBB", 1461 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", 1462 "MSRIndex": "0x1a6,0x1a7", 1463 "MSRValue": "0x5822", 1464 "SampleAfterValue": "100000", 1465 "UMask": "0x1" 1466 }, 1467 { 1468 "BriefDescription": "Offcore RFO requests that HIT in a remote cache", 1469 "Counter": "0,1,2,3", 1470 "EventCode": "0xB7, 0xBB", 1471 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", 1472 "MSRIndex": "0x1a6,0x1a7", 1473 "MSRValue": "0x1022", 1474 "SampleAfterValue": "100000", 1475 "UMask": "0x1" 1476 }, 1477 { 1478 "BriefDescription": "Offcore RFO requests that HITM in a remote cache", 1479 "Counter": "0,1,2,3", 1480 "EventCode": "0xB7, 0xBB", 1481 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", 1482 "MSRIndex": "0x1a6,0x1a7", 1483 "MSRValue": "0x822", 1484 "SampleAfterValue": "100000", 1485 "UMask": "0x1" 1486 }, 1487 { 1488 "BriefDescription": "Offcore writebacks to any cache or DRAM.", 1489 "Counter": "0,1,2,3", 1490 "EventCode": "0xB7, 0xBB", 1491 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", 1492 "MSRIndex": "0x1a6,0x1a7", 1493 "MSRValue": "0x7F08", 1494 "SampleAfterValue": "100000", 1495 "UMask": "0x1" 1496 }, 1497 { 1498 "BriefDescription": "All offcore writebacks", 1499 "Counter": "0,1,2,3", 1500 "EventCode": "0xB7, 0xBB", 1501 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", 1502 "MSRIndex": "0x1a6,0x1a7", 1503 "MSRValue": "0xFF08", 1504 "SampleAfterValue": "100000", 1505 "UMask": "0x1" 1506 }, 1507 { 1508 "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", 1509 "Counter": "0,1,2,3", 1510 "EventCode": "0xB7, 0xBB", 1511 "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", 1512 "MSRIndex": "0x1a6,0x1a7", 1513 "MSRValue": "0x8008", 1514 "SampleAfterValue": "100000", 1515 "UMask": "0x1" 1516 }, 1517 { 1518 "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core", 1519 "Counter": "0,1,2,3", 1520 "EventCode": "0xB7, 0xBB", 1521 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", 1522 "MSRIndex": "0x1a6,0x1a7", 1523 "MSRValue": "0x108", 1524 "SampleAfterValue": "100000", 1525 "UMask": "0x1" 1526 }, 1527 { 1528 "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core", 1529 "Counter": "0,1,2,3", 1530 "EventCode": "0xB7, 0xBB", 1531 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", 1532 "MSRIndex": "0x1a6,0x1a7", 1533 "MSRValue": "0x408", 1534 "SampleAfterValue": "100000", 1535 "UMask": "0x1" 1536 }, 1537 { 1538 "BriefDescription": "Offcore writebacks to the LLC", 1539 "Counter": "0,1,2,3", 1540 "EventCode": "0xB7, 0xBB", 1541 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", 1542 "MSRIndex": "0x1a6,0x1a7", 1543 "MSRValue": "0x708", 1544 "SampleAfterValue": "100000", 1545 "UMask": "0x1" 1546 }, 1547 { 1548 "BriefDescription": "Offcore writebacks to the LLC or local DRAM", 1549 "Counter": "0,1,2,3", 1550 "EventCode": "0xB7, 0xBB", 1551 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", 1552 "MSRIndex": "0x1a6,0x1a7", 1553 "MSRValue": "0x2708", 1554 "SampleAfterValue": "100000", 1555 "UMask": "0x1" 1556 }, 1557 { 1558 "BriefDescription": "Offcore writebacks to a remote cache", 1559 "Counter": "0,1,2,3", 1560 "EventCode": "0xB7, 0xBB", 1561 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", 1562 "MSRIndex": "0x1a6,0x1a7", 1563 "MSRValue": "0x1808", 1564 "SampleAfterValue": "100000", 1565 "UMask": "0x1" 1566 }, 1567 { 1568 "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM", 1569 "Counter": "0,1,2,3", 1570 "EventCode": "0xB7, 0xBB", 1571 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", 1572 "MSRIndex": "0x1a6,0x1a7", 1573 "MSRValue": "0x5808", 1574 "SampleAfterValue": "100000", 1575 "UMask": "0x1" 1576 }, 1577 { 1578 "BriefDescription": "Offcore writebacks that HIT in a remote cache", 1579 "Counter": "0,1,2,3", 1580 "EventCode": "0xB7, 0xBB", 1581 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", 1582 "MSRIndex": "0x1a6,0x1a7", 1583 "MSRValue": "0x1008", 1584 "SampleAfterValue": "100000", 1585 "UMask": "0x1" 1586 }, 1587 { 1588 "BriefDescription": "Offcore writebacks that HITM in a remote cache", 1589 "Counter": "0,1,2,3", 1590 "EventCode": "0xB7, 0xBB", 1591 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", 1592 "MSRIndex": "0x1a6,0x1a7", 1593 "MSRValue": "0x808", 1594 "SampleAfterValue": "100000", 1595 "UMask": "0x1" 1596 }, 1597 { 1598 "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", 1599 "Counter": "0,1,2,3", 1600 "EventCode": "0xB7, 0xBB", 1601 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", 1602 "MSRIndex": "0x1a6,0x1a7", 1603 "MSRValue": "0x7F77", 1604 "SampleAfterValue": "100000", 1605 "UMask": "0x1" 1606 }, 1607 { 1608 "BriefDescription": "All offcore code or data read requests", 1609 "Counter": "0,1,2,3", 1610 "EventCode": "0xB7, 0xBB", 1611 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", 1612 "MSRIndex": "0x1a6,0x1a7", 1613 "MSRValue": "0xFF77", 1614 "SampleAfterValue": "100000", 1615 "UMask": "0x1" 1616 }, 1617 { 1618 "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", 1619 "Counter": "0,1,2,3", 1620 "EventCode": "0xB7, 0xBB", 1621 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", 1622 "MSRIndex": "0x1a6,0x1a7", 1623 "MSRValue": "0x8077", 1624 "SampleAfterValue": "100000", 1625 "UMask": "0x1" 1626 }, 1627 { 1628 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", 1629 "Counter": "0,1,2,3", 1630 "EventCode": "0xB7, 0xBB", 1631 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", 1632 "MSRIndex": "0x1a6,0x1a7", 1633 "MSRValue": "0x177", 1634 "SampleAfterValue": "100000", 1635 "UMask": "0x1" 1636 }, 1637 { 1638 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", 1639 "Counter": "0,1,2,3", 1640 "EventCode": "0xB7, 0xBB", 1641 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1642 "MSRIndex": "0x1a6,0x1a7", 1643 "MSRValue": "0x277", 1644 "SampleAfterValue": "100000", 1645 "UMask": "0x1" 1646 }, 1647 { 1648 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", 1649 "Counter": "0,1,2,3", 1650 "EventCode": "0xB7, 0xBB", 1651 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1652 "MSRIndex": "0x1a6,0x1a7", 1653 "MSRValue": "0x477", 1654 "SampleAfterValue": "100000", 1655 "UMask": "0x1" 1656 }, 1657 { 1658 "BriefDescription": "Offcore code or data read requests satisfied by the LLC", 1659 "Counter": "0,1,2,3", 1660 "EventCode": "0xB7, 0xBB", 1661 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", 1662 "MSRIndex": "0x1a6,0x1a7", 1663 "MSRValue": "0x777", 1664 "SampleAfterValue": "100000", 1665 "UMask": "0x1" 1666 }, 1667 { 1668 "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", 1669 "Counter": "0,1,2,3", 1670 "EventCode": "0xB7, 0xBB", 1671 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", 1672 "MSRIndex": "0x1a6,0x1a7", 1673 "MSRValue": "0x2777", 1674 "SampleAfterValue": "100000", 1675 "UMask": "0x1" 1676 }, 1677 { 1678 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache", 1679 "Counter": "0,1,2,3", 1680 "EventCode": "0xB7, 0xBB", 1681 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", 1682 "MSRIndex": "0x1a6,0x1a7", 1683 "MSRValue": "0x1877", 1684 "SampleAfterValue": "100000", 1685 "UMask": "0x1" 1686 }, 1687 { 1688 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", 1689 "Counter": "0,1,2,3", 1690 "EventCode": "0xB7, 0xBB", 1691 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", 1692 "MSRIndex": "0x1a6,0x1a7", 1693 "MSRValue": "0x5877", 1694 "SampleAfterValue": "100000", 1695 "UMask": "0x1" 1696 }, 1697 { 1698 "BriefDescription": "Offcore code or data read requests that HIT in a remote cache", 1699 "Counter": "0,1,2,3", 1700 "EventCode": "0xB7, 0xBB", 1701 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", 1702 "MSRIndex": "0x1a6,0x1a7", 1703 "MSRValue": "0x1077", 1704 "SampleAfterValue": "100000", 1705 "UMask": "0x1" 1706 }, 1707 { 1708 "BriefDescription": "Offcore code or data read requests that HITM in a remote cache", 1709 "Counter": "0,1,2,3", 1710 "EventCode": "0xB7, 0xBB", 1711 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", 1712 "MSRIndex": "0x1a6,0x1a7", 1713 "MSRValue": "0x877", 1714 "SampleAfterValue": "100000", 1715 "UMask": "0x1" 1716 }, 1717 { 1718 "BriefDescription": "Offcore request = all data, response = any cache_dram", 1719 "Counter": "0,1,2,3", 1720 "EventCode": "0xB7, 0xBB", 1721 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", 1722 "MSRIndex": "0x1a6,0x1a7", 1723 "MSRValue": "0x7F33", 1724 "SampleAfterValue": "100000", 1725 "UMask": "0x1" 1726 }, 1727 { 1728 "BriefDescription": "Offcore request = all data, response = any location", 1729 "Counter": "0,1,2,3", 1730 "EventCode": "0xB7, 0xBB", 1731 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", 1732 "MSRIndex": "0x1a6,0x1a7", 1733 "MSRValue": "0xFF33", 1734 "SampleAfterValue": "100000", 1735 "UMask": "0x1" 1736 }, 1737 { 1738 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit", 1739 "Counter": "0,1,2,3", 1740 "EventCode": "0xB7, 0xBB", 1741 "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", 1742 "MSRIndex": "0x1a6,0x1a7", 1743 "MSRValue": "0x8033", 1744 "SampleAfterValue": "100000", 1745 "UMask": "0x1" 1746 }, 1747 { 1748 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core", 1749 "Counter": "0,1,2,3", 1750 "EventCode": "0xB7, 0xBB", 1751 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", 1752 "MSRIndex": "0x1a6,0x1a7", 1753 "MSRValue": "0x133", 1754 "SampleAfterValue": "100000", 1755 "UMask": "0x1" 1756 }, 1757 { 1758 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core", 1759 "Counter": "0,1,2,3", 1760 "EventCode": "0xB7, 0xBB", 1761 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", 1762 "MSRIndex": "0x1a6,0x1a7", 1763 "MSRValue": "0x233", 1764 "SampleAfterValue": "100000", 1765 "UMask": "0x1" 1766 }, 1767 { 1768 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core", 1769 "Counter": "0,1,2,3", 1770 "EventCode": "0xB7, 0xBB", 1771 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", 1772 "MSRIndex": "0x1a6,0x1a7", 1773 "MSRValue": "0x433", 1774 "SampleAfterValue": "100000", 1775 "UMask": "0x1" 1776 }, 1777 { 1778 "BriefDescription": "Offcore request = all data, response = local cache", 1779 "Counter": "0,1,2,3", 1780 "EventCode": "0xB7, 0xBB", 1781 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", 1782 "MSRIndex": "0x1a6,0x1a7", 1783 "MSRValue": "0x733", 1784 "SampleAfterValue": "100000", 1785 "UMask": "0x1" 1786 }, 1787 { 1788 "BriefDescription": "Offcore request = all data, response = local cache or dram", 1789 "Counter": "0,1,2,3", 1790 "EventCode": "0xB7, 0xBB", 1791 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", 1792 "MSRIndex": "0x1a6,0x1a7", 1793 "MSRValue": "0x2733", 1794 "SampleAfterValue": "100000", 1795 "UMask": "0x1" 1796 }, 1797 { 1798 "BriefDescription": "Offcore request = all data, response = remote cache", 1799 "Counter": "0,1,2,3", 1800 "EventCode": "0xB7, 0xBB", 1801 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", 1802 "MSRIndex": "0x1a6,0x1a7", 1803 "MSRValue": "0x1833", 1804 "SampleAfterValue": "100000", 1805 "UMask": "0x1" 1806 }, 1807 { 1808 "BriefDescription": "Offcore request = all data, response = remote cache or dram", 1809 "Counter": "0,1,2,3", 1810 "EventCode": "0xB7, 0xBB", 1811 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", 1812 "MSRIndex": "0x1a6,0x1a7", 1813 "MSRValue": "0x5833", 1814 "SampleAfterValue": "100000", 1815 "UMask": "0x1" 1816 }, 1817 { 1818 "BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache", 1819 "Counter": "0,1,2,3", 1820 "EventCode": "0xB7, 0xBB", 1821 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", 1822 "MSRIndex": "0x1a6,0x1a7", 1823 "MSRValue": "0x1033", 1824 "SampleAfterValue": "100000", 1825 "UMask": "0x1" 1826 }, 1827 { 1828 "BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache", 1829 "Counter": "0,1,2,3", 1830 "EventCode": "0xB7, 0xBB", 1831 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", 1832 "MSRIndex": "0x1a6,0x1a7", 1833 "MSRValue": "0x833", 1834 "SampleAfterValue": "100000", 1835 "UMask": "0x1" 1836 }, 1837 { 1838 "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM", 1839 "Counter": "0,1,2,3", 1840 "EventCode": "0xB7, 0xBB", 1841 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", 1842 "MSRIndex": "0x1a6,0x1a7", 1843 "MSRValue": "0x7F03", 1844 "SampleAfterValue": "100000", 1845 "UMask": "0x1" 1846 }, 1847 { 1848 "BriefDescription": "All offcore demand data requests", 1849 "Counter": "0,1,2,3", 1850 "EventCode": "0xB7, 0xBB", 1851 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", 1852 "MSRIndex": "0x1a6,0x1a7", 1853 "MSRValue": "0xFF03", 1854 "SampleAfterValue": "100000", 1855 "UMask": "0x1" 1856 }, 1857 { 1858 "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", 1859 "Counter": "0,1,2,3", 1860 "EventCode": "0xB7, 0xBB", 1861 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", 1862 "MSRIndex": "0x1a6,0x1a7", 1863 "MSRValue": "0x8003", 1864 "SampleAfterValue": "100000", 1865 "UMask": "0x1" 1866 }, 1867 { 1868 "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", 1869 "Counter": "0,1,2,3", 1870 "EventCode": "0xB7, 0xBB", 1871 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", 1872 "MSRIndex": "0x1a6,0x1a7", 1873 "MSRValue": "0x103", 1874 "SampleAfterValue": "100000", 1875 "UMask": "0x1" 1876 }, 1877 { 1878 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", 1879 "Counter": "0,1,2,3", 1880 "EventCode": "0xB7, 0xBB", 1881 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", 1882 "MSRIndex": "0x1a6,0x1a7", 1883 "MSRValue": "0x203", 1884 "SampleAfterValue": "100000", 1885 "UMask": "0x1" 1886 }, 1887 { 1888 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", 1889 "Counter": "0,1,2,3", 1890 "EventCode": "0xB7, 0xBB", 1891 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", 1892 "MSRIndex": "0x1a6,0x1a7", 1893 "MSRValue": "0x403", 1894 "SampleAfterValue": "100000", 1895 "UMask": "0x1" 1896 }, 1897 { 1898 "BriefDescription": "Offcore demand data requests satisfied by the LLC", 1899 "Counter": "0,1,2,3", 1900 "EventCode": "0xB7, 0xBB", 1901 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", 1902 "MSRIndex": "0x1a6,0x1a7", 1903 "MSRValue": "0x703", 1904 "SampleAfterValue": "100000", 1905 "UMask": "0x1" 1906 }, 1907 { 1908 "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", 1909 "Counter": "0,1,2,3", 1910 "EventCode": "0xB7, 0xBB", 1911 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", 1912 "MSRIndex": "0x1a6,0x1a7", 1913 "MSRValue": "0x2703", 1914 "SampleAfterValue": "100000", 1915 "UMask": "0x1" 1916 }, 1917 { 1918 "BriefDescription": "Offcore demand data requests satisfied by a remote cache", 1919 "Counter": "0,1,2,3", 1920 "EventCode": "0xB7, 0xBB", 1921 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", 1922 "MSRIndex": "0x1a6,0x1a7", 1923 "MSRValue": "0x1803", 1924 "SampleAfterValue": "100000", 1925 "UMask": "0x1" 1926 }, 1927 { 1928 "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", 1929 "Counter": "0,1,2,3", 1930 "EventCode": "0xB7, 0xBB", 1931 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", 1932 "MSRIndex": "0x1a6,0x1a7", 1933 "MSRValue": "0x5803", 1934 "SampleAfterValue": "100000", 1935 "UMask": "0x1" 1936 }, 1937 { 1938 "BriefDescription": "Offcore demand data requests that HIT in a remote cache", 1939 "Counter": "0,1,2,3", 1940 "EventCode": "0xB7, 0xBB", 1941 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", 1942 "MSRIndex": "0x1a6,0x1a7", 1943 "MSRValue": "0x1003", 1944 "SampleAfterValue": "100000", 1945 "UMask": "0x1" 1946 }, 1947 { 1948 "BriefDescription": "Offcore demand data requests that HITM in a remote cache", 1949 "Counter": "0,1,2,3", 1950 "EventCode": "0xB7, 0xBB", 1951 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", 1952 "MSRIndex": "0x1a6,0x1a7", 1953 "MSRValue": "0x803", 1954 "SampleAfterValue": "100000", 1955 "UMask": "0x1" 1956 }, 1957 { 1958 "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.", 1959 "Counter": "0,1,2,3", 1960 "EventCode": "0xB7, 0xBB", 1961 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", 1962 "MSRIndex": "0x1a6,0x1a7", 1963 "MSRValue": "0x7F01", 1964 "SampleAfterValue": "100000", 1965 "UMask": "0x1" 1966 }, 1967 { 1968 "BriefDescription": "All offcore demand data reads", 1969 "Counter": "0,1,2,3", 1970 "EventCode": "0xB7, 0xBB", 1971 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", 1972 "MSRIndex": "0x1a6,0x1a7", 1973 "MSRValue": "0xFF01", 1974 "SampleAfterValue": "100000", 1975 "UMask": "0x1" 1976 }, 1977 { 1978 "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", 1979 "Counter": "0,1,2,3", 1980 "EventCode": "0xB7, 0xBB", 1981 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", 1982 "MSRIndex": "0x1a6,0x1a7", 1983 "MSRValue": "0x8001", 1984 "SampleAfterValue": "100000", 1985 "UMask": "0x1" 1986 }, 1987 { 1988 "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", 1989 "Counter": "0,1,2,3", 1990 "EventCode": "0xB7, 0xBB", 1991 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", 1992 "MSRIndex": "0x1a6,0x1a7", 1993 "MSRValue": "0x101", 1994 "SampleAfterValue": "100000", 1995 "UMask": "0x1" 1996 }, 1997 { 1998 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", 1999 "Counter": "0,1,2,3", 2000 "EventCode": "0xB7, 0xBB", 2001 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 2002 "MSRIndex": "0x1a6,0x1a7", 2003 "MSRValue": "0x201", 2004 "SampleAfterValue": "100000", 2005 "UMask": "0x1" 2006 }, 2007 { 2008 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", 2009 "Counter": "0,1,2,3", 2010 "EventCode": "0xB7, 0xBB", 2011 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 2012 "MSRIndex": "0x1a6,0x1a7", 2013 "MSRValue": "0x401", 2014 "SampleAfterValue": "100000", 2015 "UMask": "0x1" 2016 }, 2017 { 2018 "BriefDescription": "Offcore demand data reads satisfied by the LLC", 2019 "Counter": "0,1,2,3", 2020 "EventCode": "0xB7, 0xBB", 2021 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", 2022 "MSRIndex": "0x1a6,0x1a7", 2023 "MSRValue": "0x701", 2024 "SampleAfterValue": "100000", 2025 "UMask": "0x1" 2026 }, 2027 { 2028 "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", 2029 "Counter": "0,1,2,3", 2030 "EventCode": "0xB7, 0xBB", 2031 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", 2032 "MSRIndex": "0x1a6,0x1a7", 2033 "MSRValue": "0x2701", 2034 "SampleAfterValue": "100000", 2035 "UMask": "0x1" 2036 }, 2037 { 2038 "BriefDescription": "Offcore demand data reads satisfied by a remote cache", 2039 "Counter": "0,1,2,3", 2040 "EventCode": "0xB7, 0xBB", 2041 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", 2042 "MSRIndex": "0x1a6,0x1a7", 2043 "MSRValue": "0x1801", 2044 "SampleAfterValue": "100000", 2045 "UMask": "0x1" 2046 }, 2047 { 2048 "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", 2049 "Counter": "0,1,2,3", 2050 "EventCode": "0xB7, 0xBB", 2051 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", 2052 "MSRIndex": "0x1a6,0x1a7", 2053 "MSRValue": "0x5801", 2054 "SampleAfterValue": "100000", 2055 "UMask": "0x1" 2056 }, 2057 { 2058 "BriefDescription": "Offcore demand data reads that HIT in a remote cache", 2059 "Counter": "0,1,2,3", 2060 "EventCode": "0xB7, 0xBB", 2061 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", 2062 "MSRIndex": "0x1a6,0x1a7", 2063 "MSRValue": "0x1001", 2064 "SampleAfterValue": "100000", 2065 "UMask": "0x1" 2066 }, 2067 { 2068 "BriefDescription": "Offcore demand data reads that HITM in a remote cache", 2069 "Counter": "0,1,2,3", 2070 "EventCode": "0xB7, 0xBB", 2071 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", 2072 "MSRIndex": "0x1a6,0x1a7", 2073 "MSRValue": "0x801", 2074 "SampleAfterValue": "100000", 2075 "UMask": "0x1" 2076 }, 2077 { 2078 "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.", 2079 "Counter": "0,1,2,3", 2080 "EventCode": "0xB7, 0xBB", 2081 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", 2082 "MSRIndex": "0x1a6,0x1a7", 2083 "MSRValue": "0x7F04", 2084 "SampleAfterValue": "100000", 2085 "UMask": "0x1" 2086 }, 2087 { 2088 "BriefDescription": "All offcore demand code reads", 2089 "Counter": "0,1,2,3", 2090 "EventCode": "0xB7, 0xBB", 2091 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", 2092 "MSRIndex": "0x1a6,0x1a7", 2093 "MSRValue": "0xFF04", 2094 "SampleAfterValue": "100000", 2095 "UMask": "0x1" 2096 }, 2097 { 2098 "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", 2099 "Counter": "0,1,2,3", 2100 "EventCode": "0xB7, 0xBB", 2101 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", 2102 "MSRIndex": "0x1a6,0x1a7", 2103 "MSRValue": "0x8004", 2104 "SampleAfterValue": "100000", 2105 "UMask": "0x1" 2106 }, 2107 { 2108 "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", 2109 "Counter": "0,1,2,3", 2110 "EventCode": "0xB7, 0xBB", 2111 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", 2112 "MSRIndex": "0x1a6,0x1a7", 2113 "MSRValue": "0x104", 2114 "SampleAfterValue": "100000", 2115 "UMask": "0x1" 2116 }, 2117 { 2118 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", 2119 "Counter": "0,1,2,3", 2120 "EventCode": "0xB7, 0xBB", 2121 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", 2122 "MSRIndex": "0x1a6,0x1a7", 2123 "MSRValue": "0x204", 2124 "SampleAfterValue": "100000", 2125 "UMask": "0x1" 2126 }, 2127 { 2128 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", 2129 "Counter": "0,1,2,3", 2130 "EventCode": "0xB7, 0xBB", 2131 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", 2132 "MSRIndex": "0x1a6,0x1a7", 2133 "MSRValue": "0x404", 2134 "SampleAfterValue": "100000", 2135 "UMask": "0x1" 2136 }, 2137 { 2138 "BriefDescription": "Offcore demand code reads satisfied by the LLC", 2139 "Counter": "0,1,2,3", 2140 "EventCode": "0xB7, 0xBB", 2141 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", 2142 "MSRIndex": "0x1a6,0x1a7", 2143 "MSRValue": "0x704", 2144 "SampleAfterValue": "100000", 2145 "UMask": "0x1" 2146 }, 2147 { 2148 "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", 2149 "Counter": "0,1,2,3", 2150 "EventCode": "0xB7, 0xBB", 2151 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", 2152 "MSRIndex": "0x1a6,0x1a7", 2153 "MSRValue": "0x2704", 2154 "SampleAfterValue": "100000", 2155 "UMask": "0x1" 2156 }, 2157 { 2158 "BriefDescription": "Offcore demand code reads satisfied by a remote cache", 2159 "Counter": "0,1,2,3", 2160 "EventCode": "0xB7, 0xBB", 2161 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", 2162 "MSRIndex": "0x1a6,0x1a7", 2163 "MSRValue": "0x1804", 2164 "SampleAfterValue": "100000", 2165 "UMask": "0x1" 2166 }, 2167 { 2168 "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", 2169 "Counter": "0,1,2,3", 2170 "EventCode": "0xB7, 0xBB", 2171 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", 2172 "MSRIndex": "0x1a6,0x1a7", 2173 "MSRValue": "0x5804", 2174 "SampleAfterValue": "100000", 2175 "UMask": "0x1" 2176 }, 2177 { 2178 "BriefDescription": "Offcore demand code reads that HIT in a remote cache", 2179 "Counter": "0,1,2,3", 2180 "EventCode": "0xB7, 0xBB", 2181 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", 2182 "MSRIndex": "0x1a6,0x1a7", 2183 "MSRValue": "0x1004", 2184 "SampleAfterValue": "100000", 2185 "UMask": "0x1" 2186 }, 2187 { 2188 "BriefDescription": "Offcore demand code reads that HITM in a remote cache", 2189 "Counter": "0,1,2,3", 2190 "EventCode": "0xB7, 0xBB", 2191 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", 2192 "MSRIndex": "0x1a6,0x1a7", 2193 "MSRValue": "0x804", 2194 "SampleAfterValue": "100000", 2195 "UMask": "0x1" 2196 }, 2197 { 2198 "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", 2199 "Counter": "0,1,2,3", 2200 "EventCode": "0xB7, 0xBB", 2201 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", 2202 "MSRIndex": "0x1a6,0x1a7", 2203 "MSRValue": "0x7F02", 2204 "SampleAfterValue": "100000", 2205 "UMask": "0x1" 2206 }, 2207 { 2208 "BriefDescription": "All offcore demand RFO requests", 2209 "Counter": "0,1,2,3", 2210 "EventCode": "0xB7, 0xBB", 2211 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", 2212 "MSRIndex": "0x1a6,0x1a7", 2213 "MSRValue": "0xFF02", 2214 "SampleAfterValue": "100000", 2215 "UMask": "0x1" 2216 }, 2217 { 2218 "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", 2219 "Counter": "0,1,2,3", 2220 "EventCode": "0xB7, 0xBB", 2221 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", 2222 "MSRIndex": "0x1a6,0x1a7", 2223 "MSRValue": "0x8002", 2224 "SampleAfterValue": "100000", 2225 "UMask": "0x1" 2226 }, 2227 { 2228 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", 2229 "Counter": "0,1,2,3", 2230 "EventCode": "0xB7, 0xBB", 2231 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", 2232 "MSRIndex": "0x1a6,0x1a7", 2233 "MSRValue": "0x102", 2234 "SampleAfterValue": "100000", 2235 "UMask": "0x1" 2236 }, 2237 { 2238 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", 2239 "Counter": "0,1,2,3", 2240 "EventCode": "0xB7, 0xBB", 2241 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", 2242 "MSRIndex": "0x1a6,0x1a7", 2243 "MSRValue": "0x202", 2244 "SampleAfterValue": "100000", 2245 "UMask": "0x1" 2246 }, 2247 { 2248 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", 2249 "Counter": "0,1,2,3", 2250 "EventCode": "0xB7, 0xBB", 2251 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", 2252 "MSRIndex": "0x1a6,0x1a7", 2253 "MSRValue": "0x402", 2254 "SampleAfterValue": "100000", 2255 "UMask": "0x1" 2256 }, 2257 { 2258 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC", 2259 "Counter": "0,1,2,3", 2260 "EventCode": "0xB7, 0xBB", 2261 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", 2262 "MSRIndex": "0x1a6,0x1a7", 2263 "MSRValue": "0x702", 2264 "SampleAfterValue": "100000", 2265 "UMask": "0x1" 2266 }, 2267 { 2268 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", 2269 "Counter": "0,1,2,3", 2270 "EventCode": "0xB7, 0xBB", 2271 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", 2272 "MSRIndex": "0x1a6,0x1a7", 2273 "MSRValue": "0x2702", 2274 "SampleAfterValue": "100000", 2275 "UMask": "0x1" 2276 }, 2277 { 2278 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache", 2279 "Counter": "0,1,2,3", 2280 "EventCode": "0xB7, 0xBB", 2281 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", 2282 "MSRIndex": "0x1a6,0x1a7", 2283 "MSRValue": "0x1802", 2284 "SampleAfterValue": "100000", 2285 "UMask": "0x1" 2286 }, 2287 { 2288 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", 2289 "Counter": "0,1,2,3", 2290 "EventCode": "0xB7, 0xBB", 2291 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", 2292 "MSRIndex": "0x1a6,0x1a7", 2293 "MSRValue": "0x5802", 2294 "SampleAfterValue": "100000", 2295 "UMask": "0x1" 2296 }, 2297 { 2298 "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache", 2299 "Counter": "0,1,2,3", 2300 "EventCode": "0xB7, 0xBB", 2301 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", 2302 "MSRIndex": "0x1a6,0x1a7", 2303 "MSRValue": "0x1002", 2304 "SampleAfterValue": "100000", 2305 "UMask": "0x1" 2306 }, 2307 { 2308 "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache", 2309 "Counter": "0,1,2,3", 2310 "EventCode": "0xB7, 0xBB", 2311 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", 2312 "MSRIndex": "0x1a6,0x1a7", 2313 "MSRValue": "0x802", 2314 "SampleAfterValue": "100000", 2315 "UMask": "0x1" 2316 }, 2317 { 2318 "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.", 2319 "Counter": "0,1,2,3", 2320 "EventCode": "0xB7, 0xBB", 2321 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", 2322 "MSRIndex": "0x1a6,0x1a7", 2323 "MSRValue": "0x7F80", 2324 "SampleAfterValue": "100000", 2325 "UMask": "0x1" 2326 }, 2327 { 2328 "BriefDescription": "All offcore other requests", 2329 "Counter": "0,1,2,3", 2330 "EventCode": "0xB7, 0xBB", 2331 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", 2332 "MSRIndex": "0x1a6,0x1a7", 2333 "MSRValue": "0xFF80", 2334 "SampleAfterValue": "100000", 2335 "UMask": "0x1" 2336 }, 2337 { 2338 "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", 2339 "Counter": "0,1,2,3", 2340 "EventCode": "0xB7, 0xBB", 2341 "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", 2342 "MSRIndex": "0x1a6,0x1a7", 2343 "MSRValue": "0x8080", 2344 "SampleAfterValue": "100000", 2345 "UMask": "0x1" 2346 }, 2347 { 2348 "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", 2349 "Counter": "0,1,2,3", 2350 "EventCode": "0xB7, 0xBB", 2351 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", 2352 "MSRIndex": "0x1a6,0x1a7", 2353 "MSRValue": "0x180", 2354 "SampleAfterValue": "100000", 2355 "UMask": "0x1" 2356 }, 2357 { 2358 "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", 2359 "Counter": "0,1,2,3", 2360 "EventCode": "0xB7, 0xBB", 2361 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", 2362 "MSRIndex": "0x1a6,0x1a7", 2363 "MSRValue": "0x280", 2364 "SampleAfterValue": "100000", 2365 "UMask": "0x1" 2366 }, 2367 { 2368 "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", 2369 "Counter": "0,1,2,3", 2370 "EventCode": "0xB7, 0xBB", 2371 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", 2372 "MSRIndex": "0x1a6,0x1a7", 2373 "MSRValue": "0x480", 2374 "SampleAfterValue": "100000", 2375 "UMask": "0x1" 2376 }, 2377 { 2378 "BriefDescription": "Offcore other requests satisfied by the LLC", 2379 "Counter": "0,1,2,3", 2380 "EventCode": "0xB7, 0xBB", 2381 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", 2382 "MSRIndex": "0x1a6,0x1a7", 2383 "MSRValue": "0x780", 2384 "SampleAfterValue": "100000", 2385 "UMask": "0x1" 2386 }, 2387 { 2388 "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM", 2389 "Counter": "0,1,2,3", 2390 "EventCode": "0xB7, 0xBB", 2391 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", 2392 "MSRIndex": "0x1a6,0x1a7", 2393 "MSRValue": "0x2780", 2394 "SampleAfterValue": "100000", 2395 "UMask": "0x1" 2396 }, 2397 { 2398 "BriefDescription": "Offcore other requests satisfied by a remote cache", 2399 "Counter": "0,1,2,3", 2400 "EventCode": "0xB7, 0xBB", 2401 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", 2402 "MSRIndex": "0x1a6,0x1a7", 2403 "MSRValue": "0x1880", 2404 "SampleAfterValue": "100000", 2405 "UMask": "0x1" 2406 }, 2407 { 2408 "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM", 2409 "Counter": "0,1,2,3", 2410 "EventCode": "0xB7, 0xBB", 2411 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", 2412 "MSRIndex": "0x1a6,0x1a7", 2413 "MSRValue": "0x5880", 2414 "SampleAfterValue": "100000", 2415 "UMask": "0x1" 2416 }, 2417 { 2418 "BriefDescription": "Offcore other requests that HIT in a remote cache", 2419 "Counter": "0,1,2,3", 2420 "EventCode": "0xB7, 0xBB", 2421 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", 2422 "MSRIndex": "0x1a6,0x1a7", 2423 "MSRValue": "0x1080", 2424 "SampleAfterValue": "100000", 2425 "UMask": "0x1" 2426 }, 2427 { 2428 "BriefDescription": "Offcore other requests that HITM in a remote cache", 2429 "Counter": "0,1,2,3", 2430 "EventCode": "0xB7, 0xBB", 2431 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", 2432 "MSRIndex": "0x1a6,0x1a7", 2433 "MSRValue": "0x880", 2434 "SampleAfterValue": "100000", 2435 "UMask": "0x1" 2436 }, 2437 { 2438 "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM", 2439 "Counter": "0,1,2,3", 2440 "EventCode": "0xB7, 0xBB", 2441 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", 2442 "MSRIndex": "0x1a6,0x1a7", 2443 "MSRValue": "0x7F50", 2444 "SampleAfterValue": "100000", 2445 "UMask": "0x1" 2446 }, 2447 { 2448 "BriefDescription": "All offcore prefetch data requests", 2449 "Counter": "0,1,2,3", 2450 "EventCode": "0xB7, 0xBB", 2451 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", 2452 "MSRIndex": "0x1a6,0x1a7", 2453 "MSRValue": "0xFF50", 2454 "SampleAfterValue": "100000", 2455 "UMask": "0x1" 2456 }, 2457 { 2458 "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.", 2459 "Counter": "0,1,2,3", 2460 "EventCode": "0xB7, 0xBB", 2461 "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", 2462 "MSRIndex": "0x1a6,0x1a7", 2463 "MSRValue": "0x8050", 2464 "SampleAfterValue": "100000", 2465 "UMask": "0x1" 2466 }, 2467 { 2468 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core", 2469 "Counter": "0,1,2,3", 2470 "EventCode": "0xB7, 0xBB", 2471 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", 2472 "MSRIndex": "0x1a6,0x1a7", 2473 "MSRValue": "0x150", 2474 "SampleAfterValue": "100000", 2475 "UMask": "0x1" 2476 }, 2477 { 2478 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core", 2479 "Counter": "0,1,2,3", 2480 "EventCode": "0xB7, 0xBB", 2481 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", 2482 "MSRIndex": "0x1a6,0x1a7", 2483 "MSRValue": "0x250", 2484 "SampleAfterValue": "100000", 2485 "UMask": "0x1" 2486 }, 2487 { 2488 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core", 2489 "Counter": "0,1,2,3", 2490 "EventCode": "0xB7, 0xBB", 2491 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", 2492 "MSRIndex": "0x1a6,0x1a7", 2493 "MSRValue": "0x450", 2494 "SampleAfterValue": "100000", 2495 "UMask": "0x1" 2496 }, 2497 { 2498 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC", 2499 "Counter": "0,1,2,3", 2500 "EventCode": "0xB7, 0xBB", 2501 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", 2502 "MSRIndex": "0x1a6,0x1a7", 2503 "MSRValue": "0x750", 2504 "SampleAfterValue": "100000", 2505 "UMask": "0x1" 2506 }, 2507 { 2508 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM", 2509 "Counter": "0,1,2,3", 2510 "EventCode": "0xB7, 0xBB", 2511 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", 2512 "MSRIndex": "0x1a6,0x1a7", 2513 "MSRValue": "0x2750", 2514 "SampleAfterValue": "100000", 2515 "UMask": "0x1" 2516 }, 2517 { 2518 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache", 2519 "Counter": "0,1,2,3", 2520 "EventCode": "0xB7, 0xBB", 2521 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", 2522 "MSRIndex": "0x1a6,0x1a7", 2523 "MSRValue": "0x1850", 2524 "SampleAfterValue": "100000", 2525 "UMask": "0x1" 2526 }, 2527 { 2528 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM", 2529 "Counter": "0,1,2,3", 2530 "EventCode": "0xB7, 0xBB", 2531 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", 2532 "MSRIndex": "0x1a6,0x1a7", 2533 "MSRValue": "0x5850", 2534 "SampleAfterValue": "100000", 2535 "UMask": "0x1" 2536 }, 2537 { 2538 "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache", 2539 "Counter": "0,1,2,3", 2540 "EventCode": "0xB7, 0xBB", 2541 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", 2542 "MSRIndex": "0x1a6,0x1a7", 2543 "MSRValue": "0x1050", 2544 "SampleAfterValue": "100000", 2545 "UMask": "0x1" 2546 }, 2547 { 2548 "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache", 2549 "Counter": "0,1,2,3", 2550 "EventCode": "0xB7, 0xBB", 2551 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", 2552 "MSRIndex": "0x1a6,0x1a7", 2553 "MSRValue": "0x850", 2554 "SampleAfterValue": "100000", 2555 "UMask": "0x1" 2556 }, 2557 { 2558 "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.", 2559 "Counter": "0,1,2,3", 2560 "EventCode": "0xB7, 0xBB", 2561 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", 2562 "MSRIndex": "0x1a6,0x1a7", 2563 "MSRValue": "0x7F10", 2564 "SampleAfterValue": "100000", 2565 "UMask": "0x1" 2566 }, 2567 { 2568 "BriefDescription": "All offcore prefetch data reads", 2569 "Counter": "0,1,2,3", 2570 "EventCode": "0xB7, 0xBB", 2571 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", 2572 "MSRIndex": "0x1a6,0x1a7", 2573 "MSRValue": "0xFF10", 2574 "SampleAfterValue": "100000", 2575 "UMask": "0x1" 2576 }, 2577 { 2578 "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit", 2579 "Counter": "0,1,2,3", 2580 "EventCode": "0xB7, 0xBB", 2581 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", 2582 "MSRIndex": "0x1a6,0x1a7", 2583 "MSRValue": "0x8010", 2584 "SampleAfterValue": "100000", 2585 "UMask": "0x1" 2586 }, 2587 { 2588 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core", 2589 "Counter": "0,1,2,3", 2590 "EventCode": "0xB7, 0xBB", 2591 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", 2592 "MSRIndex": "0x1a6,0x1a7", 2593 "MSRValue": "0x110", 2594 "SampleAfterValue": "100000", 2595 "UMask": "0x1" 2596 }, 2597 { 2598 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core", 2599 "Counter": "0,1,2,3", 2600 "EventCode": "0xB7, 0xBB", 2601 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 2602 "MSRIndex": "0x1a6,0x1a7", 2603 "MSRValue": "0x210", 2604 "SampleAfterValue": "100000", 2605 "UMask": "0x1" 2606 }, 2607 { 2608 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core", 2609 "Counter": "0,1,2,3", 2610 "EventCode": "0xB7, 0xBB", 2611 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 2612 "MSRIndex": "0x1a6,0x1a7", 2613 "MSRValue": "0x410", 2614 "SampleAfterValue": "100000", 2615 "UMask": "0x1" 2616 }, 2617 { 2618 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC", 2619 "Counter": "0,1,2,3", 2620 "EventCode": "0xB7, 0xBB", 2621 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", 2622 "MSRIndex": "0x1a6,0x1a7", 2623 "MSRValue": "0x710", 2624 "SampleAfterValue": "100000", 2625 "UMask": "0x1" 2626 }, 2627 { 2628 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM", 2629 "Counter": "0,1,2,3", 2630 "EventCode": "0xB7, 0xBB", 2631 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", 2632 "MSRIndex": "0x1a6,0x1a7", 2633 "MSRValue": "0x2710", 2634 "SampleAfterValue": "100000", 2635 "UMask": "0x1" 2636 }, 2637 { 2638 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache", 2639 "Counter": "0,1,2,3", 2640 "EventCode": "0xB7, 0xBB", 2641 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", 2642 "MSRIndex": "0x1a6,0x1a7", 2643 "MSRValue": "0x1810", 2644 "SampleAfterValue": "100000", 2645 "UMask": "0x1" 2646 }, 2647 { 2648 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM", 2649 "Counter": "0,1,2,3", 2650 "EventCode": "0xB7, 0xBB", 2651 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", 2652 "MSRIndex": "0x1a6,0x1a7", 2653 "MSRValue": "0x5810", 2654 "SampleAfterValue": "100000", 2655 "UMask": "0x1" 2656 }, 2657 { 2658 "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache", 2659 "Counter": "0,1,2,3", 2660 "EventCode": "0xB7, 0xBB", 2661 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", 2662 "MSRIndex": "0x1a6,0x1a7", 2663 "MSRValue": "0x1010", 2664 "SampleAfterValue": "100000", 2665 "UMask": "0x1" 2666 }, 2667 { 2668 "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache", 2669 "Counter": "0,1,2,3", 2670 "EventCode": "0xB7, 0xBB", 2671 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", 2672 "MSRIndex": "0x1a6,0x1a7", 2673 "MSRValue": "0x810", 2674 "SampleAfterValue": "100000", 2675 "UMask": "0x1" 2676 }, 2677 { 2678 "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.", 2679 "Counter": "0,1,2,3", 2680 "EventCode": "0xB7, 0xBB", 2681 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", 2682 "MSRIndex": "0x1a6,0x1a7", 2683 "MSRValue": "0x7F40", 2684 "SampleAfterValue": "100000", 2685 "UMask": "0x1" 2686 }, 2687 { 2688 "BriefDescription": "All offcore prefetch code reads", 2689 "Counter": "0,1,2,3", 2690 "EventCode": "0xB7, 0xBB", 2691 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", 2692 "MSRIndex": "0x1a6,0x1a7", 2693 "MSRValue": "0xFF40", 2694 "SampleAfterValue": "100000", 2695 "UMask": "0x1" 2696 }, 2697 { 2698 "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit", 2699 "Counter": "0,1,2,3", 2700 "EventCode": "0xB7, 0xBB", 2701 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", 2702 "MSRIndex": "0x1a6,0x1a7", 2703 "MSRValue": "0x8040", 2704 "SampleAfterValue": "100000", 2705 "UMask": "0x1" 2706 }, 2707 { 2708 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core", 2709 "Counter": "0,1,2,3", 2710 "EventCode": "0xB7, 0xBB", 2711 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", 2712 "MSRIndex": "0x1a6,0x1a7", 2713 "MSRValue": "0x140", 2714 "SampleAfterValue": "100000", 2715 "UMask": "0x1" 2716 }, 2717 { 2718 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core", 2719 "Counter": "0,1,2,3", 2720 "EventCode": "0xB7, 0xBB", 2721 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", 2722 "MSRIndex": "0x1a6,0x1a7", 2723 "MSRValue": "0x240", 2724 "SampleAfterValue": "100000", 2725 "UMask": "0x1" 2726 }, 2727 { 2728 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core", 2729 "Counter": "0,1,2,3", 2730 "EventCode": "0xB7, 0xBB", 2731 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", 2732 "MSRIndex": "0x1a6,0x1a7", 2733 "MSRValue": "0x440", 2734 "SampleAfterValue": "100000", 2735 "UMask": "0x1" 2736 }, 2737 { 2738 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC", 2739 "Counter": "0,1,2,3", 2740 "EventCode": "0xB7, 0xBB", 2741 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", 2742 "MSRIndex": "0x1a6,0x1a7", 2743 "MSRValue": "0x740", 2744 "SampleAfterValue": "100000", 2745 "UMask": "0x1" 2746 }, 2747 { 2748 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM", 2749 "Counter": "0,1,2,3", 2750 "EventCode": "0xB7, 0xBB", 2751 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", 2752 "MSRIndex": "0x1a6,0x1a7", 2753 "MSRValue": "0x2740", 2754 "SampleAfterValue": "100000", 2755 "UMask": "0x1" 2756 }, 2757 { 2758 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache", 2759 "Counter": "0,1,2,3", 2760 "EventCode": "0xB7, 0xBB", 2761 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", 2762 "MSRIndex": "0x1a6,0x1a7", 2763 "MSRValue": "0x1840", 2764 "SampleAfterValue": "100000", 2765 "UMask": "0x1" 2766 }, 2767 { 2768 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM", 2769 "Counter": "0,1,2,3", 2770 "EventCode": "0xB7, 0xBB", 2771 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", 2772 "MSRIndex": "0x1a6,0x1a7", 2773 "MSRValue": "0x5840", 2774 "SampleAfterValue": "100000", 2775 "UMask": "0x1" 2776 }, 2777 { 2778 "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache", 2779 "Counter": "0,1,2,3", 2780 "EventCode": "0xB7, 0xBB", 2781 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", 2782 "MSRIndex": "0x1a6,0x1a7", 2783 "MSRValue": "0x1040", 2784 "SampleAfterValue": "100000", 2785 "UMask": "0x1" 2786 }, 2787 { 2788 "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache", 2789 "Counter": "0,1,2,3", 2790 "EventCode": "0xB7, 0xBB", 2791 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", 2792 "MSRIndex": "0x1a6,0x1a7", 2793 "MSRValue": "0x840", 2794 "SampleAfterValue": "100000", 2795 "UMask": "0x1" 2796 }, 2797 { 2798 "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.", 2799 "Counter": "0,1,2,3", 2800 "EventCode": "0xB7, 0xBB", 2801 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", 2802 "MSRIndex": "0x1a6,0x1a7", 2803 "MSRValue": "0x7F20", 2804 "SampleAfterValue": "100000", 2805 "UMask": "0x1" 2806 }, 2807 { 2808 "BriefDescription": "All offcore prefetch RFO requests", 2809 "Counter": "0,1,2,3", 2810 "EventCode": "0xB7, 0xBB", 2811 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", 2812 "MSRIndex": "0x1a6,0x1a7", 2813 "MSRValue": "0xFF20", 2814 "SampleAfterValue": "100000", 2815 "UMask": "0x1" 2816 }, 2817 { 2818 "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit", 2819 "Counter": "0,1,2,3", 2820 "EventCode": "0xB7, 0xBB", 2821 "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", 2822 "MSRIndex": "0x1a6,0x1a7", 2823 "MSRValue": "0x8020", 2824 "SampleAfterValue": "100000", 2825 "UMask": "0x1" 2826 }, 2827 { 2828 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core", 2829 "Counter": "0,1,2,3", 2830 "EventCode": "0xB7, 0xBB", 2831 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", 2832 "MSRIndex": "0x1a6,0x1a7", 2833 "MSRValue": "0x120", 2834 "SampleAfterValue": "100000", 2835 "UMask": "0x1" 2836 }, 2837 { 2838 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core", 2839 "Counter": "0,1,2,3", 2840 "EventCode": "0xB7, 0xBB", 2841 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", 2842 "MSRIndex": "0x1a6,0x1a7", 2843 "MSRValue": "0x220", 2844 "SampleAfterValue": "100000", 2845 "UMask": "0x1" 2846 }, 2847 { 2848 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core", 2849 "Counter": "0,1,2,3", 2850 "EventCode": "0xB7, 0xBB", 2851 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", 2852 "MSRIndex": "0x1a6,0x1a7", 2853 "MSRValue": "0x420", 2854 "SampleAfterValue": "100000", 2855 "UMask": "0x1" 2856 }, 2857 { 2858 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC", 2859 "Counter": "0,1,2,3", 2860 "EventCode": "0xB7, 0xBB", 2861 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", 2862 "MSRIndex": "0x1a6,0x1a7", 2863 "MSRValue": "0x720", 2864 "SampleAfterValue": "100000", 2865 "UMask": "0x1" 2866 }, 2867 { 2868 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM", 2869 "Counter": "0,1,2,3", 2870 "EventCode": "0xB7, 0xBB", 2871 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", 2872 "MSRIndex": "0x1a6,0x1a7", 2873 "MSRValue": "0x2720", 2874 "SampleAfterValue": "100000", 2875 "UMask": "0x1" 2876 }, 2877 { 2878 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache", 2879 "Counter": "0,1,2,3", 2880 "EventCode": "0xB7, 0xBB", 2881 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", 2882 "MSRIndex": "0x1a6,0x1a7", 2883 "MSRValue": "0x1820", 2884 "SampleAfterValue": "100000", 2885 "UMask": "0x1" 2886 }, 2887 { 2888 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM", 2889 "Counter": "0,1,2,3", 2890 "EventCode": "0xB7, 0xBB", 2891 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", 2892 "MSRIndex": "0x1a6,0x1a7", 2893 "MSRValue": "0x5820", 2894 "SampleAfterValue": "100000", 2895 "UMask": "0x1" 2896 }, 2897 { 2898 "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache", 2899 "Counter": "0,1,2,3", 2900 "EventCode": "0xB7, 0xBB", 2901 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", 2902 "MSRIndex": "0x1a6,0x1a7", 2903 "MSRValue": "0x1020", 2904 "SampleAfterValue": "100000", 2905 "UMask": "0x1" 2906 }, 2907 { 2908 "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache", 2909 "Counter": "0,1,2,3", 2910 "EventCode": "0xB7, 0xBB", 2911 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", 2912 "MSRIndex": "0x1a6,0x1a7", 2913 "MSRValue": "0x820", 2914 "SampleAfterValue": "100000", 2915 "UMask": "0x1" 2916 }, 2917 { 2918 "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.", 2919 "Counter": "0,1,2,3", 2920 "EventCode": "0xB7, 0xBB", 2921 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", 2922 "MSRIndex": "0x1a6,0x1a7", 2923 "MSRValue": "0x7F70", 2924 "SampleAfterValue": "100000", 2925 "UMask": "0x1" 2926 }, 2927 { 2928 "BriefDescription": "All offcore prefetch requests", 2929 "Counter": "0,1,2,3", 2930 "EventCode": "0xB7, 0xBB", 2931 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", 2932 "MSRIndex": "0x1a6,0x1a7", 2933 "MSRValue": "0xFF70", 2934 "SampleAfterValue": "100000", 2935 "UMask": "0x1" 2936 }, 2937 { 2938 "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit", 2939 "Counter": "0,1,2,3", 2940 "EventCode": "0xB7, 0xBB", 2941 "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", 2942 "MSRIndex": "0x1a6,0x1a7", 2943 "MSRValue": "0x8070", 2944 "SampleAfterValue": "100000", 2945 "UMask": "0x1" 2946 }, 2947 { 2948 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core", 2949 "Counter": "0,1,2,3", 2950 "EventCode": "0xB7, 0xBB", 2951 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", 2952 "MSRIndex": "0x1a6,0x1a7", 2953 "MSRValue": "0x170", 2954 "SampleAfterValue": "100000", 2955 "UMask": "0x1" 2956 }, 2957 { 2958 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", 2959 "Counter": "0,1,2,3", 2960 "EventCode": "0xB7, 0xBB", 2961 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", 2962 "MSRIndex": "0x1a6,0x1a7", 2963 "MSRValue": "0x270", 2964 "SampleAfterValue": "100000", 2965 "UMask": "0x1" 2966 }, 2967 { 2968 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", 2969 "Counter": "0,1,2,3", 2970 "EventCode": "0xB7, 0xBB", 2971 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", 2972 "MSRIndex": "0x1a6,0x1a7", 2973 "MSRValue": "0x470", 2974 "SampleAfterValue": "100000", 2975 "UMask": "0x1" 2976 }, 2977 { 2978 "BriefDescription": "Offcore prefetch requests satisfied by the LLC", 2979 "Counter": "0,1,2,3", 2980 "EventCode": "0xB7, 0xBB", 2981 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", 2982 "MSRIndex": "0x1a6,0x1a7", 2983 "MSRValue": "0x770", 2984 "SampleAfterValue": "100000", 2985 "UMask": "0x1" 2986 }, 2987 { 2988 "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM", 2989 "Counter": "0,1,2,3", 2990 "EventCode": "0xB7, 0xBB", 2991 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", 2992 "MSRIndex": "0x1a6,0x1a7", 2993 "MSRValue": "0x2770", 2994 "SampleAfterValue": "100000", 2995 "UMask": "0x1" 2996 }, 2997 { 2998 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache", 2999 "Counter": "0,1,2,3", 3000 "EventCode": "0xB7, 0xBB", 3001 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", 3002 "MSRIndex": "0x1a6,0x1a7", 3003 "MSRValue": "0x1870", 3004 "SampleAfterValue": "100000", 3005 "UMask": "0x1" 3006 }, 3007 { 3008 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM", 3009 "Counter": "0,1,2,3", 3010 "EventCode": "0xB7, 0xBB", 3011 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", 3012 "MSRIndex": "0x1a6,0x1a7", 3013 "MSRValue": "0x5870", 3014 "SampleAfterValue": "100000", 3015 "UMask": "0x1" 3016 }, 3017 { 3018 "BriefDescription": "Offcore prefetch requests that HIT in a remote cache", 3019 "Counter": "0,1,2,3", 3020 "EventCode": "0xB7, 0xBB", 3021 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", 3022 "MSRIndex": "0x1a6,0x1a7", 3023 "MSRValue": "0x1070", 3024 "SampleAfterValue": "100000", 3025 "UMask": "0x1" 3026 }, 3027 { 3028 "BriefDescription": "Offcore prefetch requests that HITM in a remote cache", 3029 "Counter": "0,1,2,3", 3030 "EventCode": "0xB7, 0xBB", 3031 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", 3032 "MSRIndex": "0x1a6,0x1a7", 3033 "MSRValue": "0x870", 3034 "SampleAfterValue": "100000", 3035 "UMask": "0x1" 3036 }, 3037 { 3038 "BriefDescription": "Super Queue LRU hints sent to LLC", 3039 "Counter": "0,1,2,3", 3040 "EventCode": "0xF4", 3041 "EventName": "SQ_MISC.LRU_HINTS", 3042 "SampleAfterValue": "2000000", 3043 "UMask": "0x4" 3044 }, 3045 { 3046 "BriefDescription": "Super Queue lock splits across a cache line", 3047 "Counter": "0,1,2,3", 3048 "EventCode": "0xF4", 3049 "EventName": "SQ_MISC.SPLIT_LOCK", 3050 "SampleAfterValue": "2000000", 3051 "UMask": "0x10" 3052 }, 3053 { 3054 "BriefDescription": "Loads delayed with at-Retirement block code", 3055 "Counter": "0,1,2,3", 3056 "EventCode": "0x6", 3057 "EventName": "STORE_BLOCKS.AT_RET", 3058 "SampleAfterValue": "200000", 3059 "UMask": "0x4" 3060 }, 3061 { 3062 "BriefDescription": "Cacheable loads delayed with L1D block code", 3063 "Counter": "0,1,2,3", 3064 "EventCode": "0x6", 3065 "EventName": "STORE_BLOCKS.L1D_BLOCK", 3066 "SampleAfterValue": "200000", 3067 "UMask": "0x8" 3068 } 3069]
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