FILE
cache.json
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linux-6.19.14/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json
1[ 2 { 3 "BriefDescription": "Cycles L1D locked", 4 "Counter": "0,1", 5 "EventCode": "0x63", 6 "EventName": "CACHE_LOCK_CYCLES.L1D", 7 "SampleAfterValue": "2000000", 8 "UMask": "0x2" 9 }, 10 { 11 "BriefDescription": "Cycles L1D and L2 locked", 12 "Counter": "0,1", 13 "EventCode": "0x63", 14 "EventName": "CACHE_LOCK_CYCLES.L1D_L2", 15 "SampleAfterValue": "2000000", 16 "UMask": "0x1" 17 }, 18 { 19 "BriefDescription": "L1D cache lines replaced in M state", 20 "Counter": "0,1", 21 "EventCode": "0x51", 22 "EventName": "L1D.M_EVICT", 23 "SampleAfterValue": "2000000", 24 "UMask": "0x4" 25 }, 26 { 27 "BriefDescription": "L1D cache lines allocated in the M state", 28 "Counter": "0,1", 29 "EventCode": "0x51", 30 "EventName": "L1D.M_REPL", 31 "SampleAfterValue": "2000000", 32 "UMask": "0x2" 33 }, 34 { 35 "BriefDescription": "L1D snoop eviction of cache lines in M state", 36 "Counter": "0,1", 37 "EventCode": "0x51", 38 "EventName": "L1D.M_SNOOP_EVICT", 39 "SampleAfterValue": "2000000", 40 "UMask": "0x8" 41 }, 42 { 43 "BriefDescription": "L1 data cache lines allocated", 44 "Counter": "0,1", 45 "EventCode": "0x51", 46 "EventName": "L1D.REPL", 47 "SampleAfterValue": "2000000", 48 "UMask": "0x1" 49 }, 50 { 51 "BriefDescription": "L1D prefetch load lock accepted in fill buffer", 52 "Counter": "0,1", 53 "EventCode": "0x52", 54 "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", 55 "SampleAfterValue": "2000000", 56 "UMask": "0x1" 57 }, 58 { 59 "BriefDescription": "L1D hardware prefetch misses", 60 "Counter": "0,1", 61 "EventCode": "0x4E", 62 "EventName": "L1D_PREFETCH.MISS", 63 "SampleAfterValue": "200000", 64 "UMask": "0x2" 65 }, 66 { 67 "BriefDescription": "L1D hardware prefetch requests", 68 "Counter": "0,1", 69 "EventCode": "0x4E", 70 "EventName": "L1D_PREFETCH.REQUESTS", 71 "SampleAfterValue": "200000", 72 "UMask": "0x1" 73 }, 74 { 75 "BriefDescription": "L1D hardware prefetch requests triggered", 76 "Counter": "0,1", 77 "EventCode": "0x4E", 78 "EventName": "L1D_PREFETCH.TRIGGERS", 79 "SampleAfterValue": "200000", 80 "UMask": "0x4" 81 }, 82 { 83 "BriefDescription": "L1 writebacks to L2 in E state", 84 "Counter": "0,1,2,3", 85 "EventCode": "0x28", 86 "EventName": "L1D_WB_L2.E_STATE", 87 "SampleAfterValue": "100000", 88 "UMask": "0x4" 89 }, 90 { 91 "BriefDescription": "L1 writebacks to L2 in I state (misses)", 92 "Counter": "0,1,2,3", 93 "EventCode": "0x28", 94 "EventName": "L1D_WB_L2.I_STATE", 95 "SampleAfterValue": "100000", 96 "UMask": "0x1" 97 }, 98 { 99 "BriefDescription": "All L1 writebacks to L2", 100 "Counter": "0,1,2,3", 101 "EventCode": "0x28", 102 "EventName": "L1D_WB_L2.MESI", 103 "SampleAfterValue": "100000", 104 "UMask": "0xf" 105 }, 106 { 107 "BriefDescription": "L1 writebacks to L2 in M state", 108 "Counter": "0,1,2,3", 109 "EventCode": "0x28", 110 "EventName": "L1D_WB_L2.M_STATE", 111 "SampleAfterValue": "100000", 112 "UMask": "0x8" 113 }, 114 { 115 "BriefDescription": "L1 writebacks to L2 in S state", 116 "Counter": "0,1,2,3", 117 "EventCode": "0x28", 118 "EventName": "L1D_WB_L2.S_STATE", 119 "SampleAfterValue": "100000", 120 "UMask": "0x2" 121 }, 122 { 123 "BriefDescription": "L1I instruction fetch stall cycles", 124 "Counter": "0,1,2,3", 125 "EventCode": "0x80", 126 "EventName": "L1I.CYCLES_STALLED", 127 "SampleAfterValue": "2000000", 128 "UMask": "0x4" 129 }, 130 { 131 "BriefDescription": "L1I instruction fetch hits", 132 "Counter": "0,1,2,3", 133 "EventCode": "0x80", 134 "EventName": "L1I.HITS", 135 "SampleAfterValue": "2000000", 136 "UMask": "0x1" 137 }, 138 { 139 "BriefDescription": "L1I instruction fetch misses", 140 "Counter": "0,1,2,3", 141 "EventCode": "0x80", 142 "EventName": "L1I.MISSES", 143 "SampleAfterValue": "2000000", 144 "UMask": "0x2" 145 }, 146 { 147 "BriefDescription": "L1I Instruction fetches", 148 "Counter": "0,1,2,3", 149 "EventCode": "0x80", 150 "EventName": "L1I.READS", 151 "SampleAfterValue": "2000000", 152 "UMask": "0x3" 153 }, 154 { 155 "BriefDescription": "All L2 data requests", 156 "Counter": "0,1,2,3", 157 "EventCode": "0x26", 158 "EventName": "L2_DATA_RQSTS.ANY", 159 "SampleAfterValue": "200000", 160 "UMask": "0xff" 161 }, 162 { 163 "BriefDescription": "L2 data demand loads in E state", 164 "Counter": "0,1,2,3", 165 "EventCode": "0x26", 166 "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", 167 "SampleAfterValue": "200000", 168 "UMask": "0x4" 169 }, 170 { 171 "BriefDescription": "L2 data demand loads in I state (misses)", 172 "Counter": "0,1,2,3", 173 "EventCode": "0x26", 174 "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", 175 "SampleAfterValue": "200000", 176 "UMask": "0x1" 177 }, 178 { 179 "BriefDescription": "L2 data demand requests", 180 "Counter": "0,1,2,3", 181 "EventCode": "0x26", 182 "EventName": "L2_DATA_RQSTS.DEMAND.MESI", 183 "SampleAfterValue": "200000", 184 "UMask": "0xf" 185 }, 186 { 187 "BriefDescription": "L2 data demand loads in M state", 188 "Counter": "0,1,2,3", 189 "EventCode": "0x26", 190 "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", 191 "SampleAfterValue": "200000", 192 "UMask": "0x8" 193 }, 194 { 195 "BriefDescription": "L2 data demand loads in S state", 196 "Counter": "0,1,2,3", 197 "EventCode": "0x26", 198 "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", 199 "SampleAfterValue": "200000", 200 "UMask": "0x2" 201 }, 202 { 203 "BriefDescription": "L2 data prefetches in E state", 204 "Counter": "0,1,2,3", 205 "EventCode": "0x26", 206 "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", 207 "SampleAfterValue": "200000", 208 "UMask": "0x40" 209 }, 210 { 211 "BriefDescription": "L2 data prefetches in the I state (misses)", 212 "Counter": "0,1,2,3", 213 "EventCode": "0x26", 214 "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", 215 "SampleAfterValue": "200000", 216 "UMask": "0x10" 217 }, 218 { 219 "BriefDescription": "All L2 data prefetches", 220 "Counter": "0,1,2,3", 221 "EventCode": "0x26", 222 "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", 223 "SampleAfterValue": "200000", 224 "UMask": "0xf0" 225 }, 226 { 227 "BriefDescription": "L2 data prefetches in M state", 228 "Counter": "0,1,2,3", 229 "EventCode": "0x26", 230 "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", 231 "SampleAfterValue": "200000", 232 "UMask": "0x80" 233 }, 234 { 235 "BriefDescription": "L2 data prefetches in the S state", 236 "Counter": "0,1,2,3", 237 "EventCode": "0x26", 238 "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", 239 "SampleAfterValue": "200000", 240 "UMask": "0x20" 241 }, 242 { 243 "BriefDescription": "L2 lines allocated", 244 "Counter": "0,1,2,3", 245 "EventCode": "0xF1", 246 "EventName": "L2_LINES_IN.ANY", 247 "SampleAfterValue": "100000", 248 "UMask": "0x7" 249 }, 250 { 251 "BriefDescription": "L2 lines allocated in the E state", 252 "Counter": "0,1,2,3", 253 "EventCode": "0xF1", 254 "EventName": "L2_LINES_IN.E_STATE", 255 "SampleAfterValue": "100000", 256 "UMask": "0x4" 257 }, 258 { 259 "BriefDescription": "L2 lines allocated in the S state", 260 "Counter": "0,1,2,3", 261 "EventCode": "0xF1", 262 "EventName": "L2_LINES_IN.S_STATE", 263 "SampleAfterValue": "100000", 264 "UMask": "0x2" 265 }, 266 { 267 "BriefDescription": "L2 lines evicted", 268 "Counter": "0,1,2,3", 269 "EventCode": "0xF2", 270 "EventName": "L2_LINES_OUT.ANY", 271 "SampleAfterValue": "100000", 272 "UMask": "0xf" 273 }, 274 { 275 "BriefDescription": "L2 lines evicted by a demand request", 276 "Counter": "0,1,2,3", 277 "EventCode": "0xF2", 278 "EventName": "L2_LINES_OUT.DEMAND_CLEAN", 279 "SampleAfterValue": "100000", 280 "UMask": "0x1" 281 }, 282 { 283 "BriefDescription": "L2 modified lines evicted by a demand request", 284 "Counter": "0,1,2,3", 285 "EventCode": "0xF2", 286 "EventName": "L2_LINES_OUT.DEMAND_DIRTY", 287 "SampleAfterValue": "100000", 288 "UMask": "0x2" 289 }, 290 { 291 "BriefDescription": "L2 lines evicted by a prefetch request", 292 "Counter": "0,1,2,3", 293 "EventCode": "0xF2", 294 "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", 295 "SampleAfterValue": "100000", 296 "UMask": "0x4" 297 }, 298 { 299 "BriefDescription": "L2 modified lines evicted by a prefetch request", 300 "Counter": "0,1,2,3", 301 "EventCode": "0xF2", 302 "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", 303 "SampleAfterValue": "100000", 304 "UMask": "0x8" 305 }, 306 { 307 "BriefDescription": "L2 instruction fetches", 308 "Counter": "0,1,2,3", 309 "EventCode": "0x24", 310 "EventName": "L2_RQSTS.IFETCHES", 311 "SampleAfterValue": "200000", 312 "UMask": "0x30" 313 }, 314 { 315 "BriefDescription": "L2 instruction fetch hits", 316 "Counter": "0,1,2,3", 317 "EventCode": "0x24", 318 "EventName": "L2_RQSTS.IFETCH_HIT", 319 "SampleAfterValue": "200000", 320 "UMask": "0x10" 321 }, 322 { 323 "BriefDescription": "L2 instruction fetch misses", 324 "Counter": "0,1,2,3", 325 "EventCode": "0x24", 326 "EventName": "L2_RQSTS.IFETCH_MISS", 327 "SampleAfterValue": "200000", 328 "UMask": "0x20" 329 }, 330 { 331 "BriefDescription": "L2 load hits", 332 "Counter": "0,1,2,3", 333 "EventCode": "0x24", 334 "EventName": "L2_RQSTS.LD_HIT", 335 "SampleAfterValue": "200000", 336 "UMask": "0x1" 337 }, 338 { 339 "BriefDescription": "L2 load misses", 340 "Counter": "0,1,2,3", 341 "EventCode": "0x24", 342 "EventName": "L2_RQSTS.LD_MISS", 343 "SampleAfterValue": "200000", 344 "UMask": "0x2" 345 }, 346 { 347 "BriefDescription": "L2 requests", 348 "Counter": "0,1,2,3", 349 "EventCode": "0x24", 350 "EventName": "L2_RQSTS.LOADS", 351 "SampleAfterValue": "200000", 352 "UMask": "0x3" 353 }, 354 { 355 "BriefDescription": "All L2 misses", 356 "Counter": "0,1,2,3", 357 "EventCode": "0x24", 358 "EventName": "L2_RQSTS.MISS", 359 "SampleAfterValue": "200000", 360 "UMask": "0xaa" 361 }, 362 { 363 "BriefDescription": "All L2 prefetches", 364 "Counter": "0,1,2,3", 365 "EventCode": "0x24", 366 "EventName": "L2_RQSTS.PREFETCHES", 367 "SampleAfterValue": "200000", 368 "UMask": "0xc0" 369 }, 370 { 371 "BriefDescription": "L2 prefetch hits", 372 "Counter": "0,1,2,3", 373 "EventCode": "0x24", 374 "EventName": "L2_RQSTS.PREFETCH_HIT", 375 "SampleAfterValue": "200000", 376 "UMask": "0x40" 377 }, 378 { 379 "BriefDescription": "L2 prefetch misses", 380 "Counter": "0,1,2,3", 381 "EventCode": "0x24", 382 "EventName": "L2_RQSTS.PREFETCH_MISS", 383 "SampleAfterValue": "200000", 384 "UMask": "0x80" 385 }, 386 { 387 "BriefDescription": "All L2 requests", 388 "Counter": "0,1,2,3", 389 "EventCode": "0x24", 390 "EventName": "L2_RQSTS.REFERENCES", 391 "SampleAfterValue": "200000", 392 "UMask": "0xff" 393 }, 394 { 395 "BriefDescription": "L2 RFO requests", 396 "Counter": "0,1,2,3", 397 "EventCode": "0x24", 398 "EventName": "L2_RQSTS.RFOS", 399 "SampleAfterValue": "200000", 400 "UMask": "0xc" 401 }, 402 { 403 "BriefDescription": "L2 RFO hits", 404 "Counter": "0,1,2,3", 405 "EventCode": "0x24", 406 "EventName": "L2_RQSTS.RFO_HIT", 407 "SampleAfterValue": "200000", 408 "UMask": "0x4" 409 }, 410 { 411 "BriefDescription": "L2 RFO misses", 412 "Counter": "0,1,2,3", 413 "EventCode": "0x24", 414 "EventName": "L2_RQSTS.RFO_MISS", 415 "SampleAfterValue": "200000", 416 "UMask": "0x8" 417 }, 418 { 419 "BriefDescription": "All L2 transactions", 420 "Counter": "0,1,2,3", 421 "EventCode": "0xF0", 422 "EventName": "L2_TRANSACTIONS.ANY", 423 "SampleAfterValue": "200000", 424 "UMask": "0x80" 425 }, 426 { 427 "BriefDescription": "L2 fill transactions", 428 "Counter": "0,1,2,3", 429 "EventCode": "0xF0", 430 "EventName": "L2_TRANSACTIONS.FILL", 431 "SampleAfterValue": "200000", 432 "UMask": "0x20" 433 }, 434 { 435 "BriefDescription": "L2 instruction fetch transactions", 436 "Counter": "0,1,2,3", 437 "EventCode": "0xF0", 438 "EventName": "L2_TRANSACTIONS.IFETCH", 439 "SampleAfterValue": "200000", 440 "UMask": "0x4" 441 }, 442 { 443 "BriefDescription": "L1D writeback to L2 transactions", 444 "Counter": "0,1,2,3", 445 "EventCode": "0xF0", 446 "EventName": "L2_TRANSACTIONS.L1D_WB", 447 "SampleAfterValue": "200000", 448 "UMask": "0x10" 449 }, 450 { 451 "BriefDescription": "L2 Load transactions", 452 "Counter": "0,1,2,3", 453 "EventCode": "0xF0", 454 "EventName": "L2_TRANSACTIONS.LOAD", 455 "SampleAfterValue": "200000", 456 "UMask": "0x1" 457 }, 458 { 459 "BriefDescription": "L2 prefetch transactions", 460 "Counter": "0,1,2,3", 461 "EventCode": "0xF0", 462 "EventName": "L2_TRANSACTIONS.PREFETCH", 463 "SampleAfterValue": "200000", 464 "UMask": "0x8" 465 }, 466 { 467 "BriefDescription": "L2 RFO transactions", 468 "Counter": "0,1,2,3", 469 "EventCode": "0xF0", 470 "EventName": "L2_TRANSACTIONS.RFO", 471 "SampleAfterValue": "200000", 472 "UMask": "0x2" 473 }, 474 { 475 "BriefDescription": "L2 writeback to LLC transactions", 476 "Counter": "0,1,2,3", 477 "EventCode": "0xF0", 478 "EventName": "L2_TRANSACTIONS.WB", 479 "SampleAfterValue": "200000", 480 "UMask": "0x40" 481 }, 482 { 483 "BriefDescription": "L2 demand lock RFOs in E state", 484 "Counter": "0,1,2,3", 485 "EventCode": "0x27", 486 "EventName": "L2_WRITE.LOCK.E_STATE", 487 "SampleAfterValue": "100000", 488 "UMask": "0x40" 489 }, 490 { 491 "BriefDescription": "All demand L2 lock RFOs that hit the cache", 492 "Counter": "0,1,2,3", 493 "EventCode": "0x27", 494 "EventName": "L2_WRITE.LOCK.HIT", 495 "SampleAfterValue": "100000", 496 "UMask": "0xe0" 497 }, 498 { 499 "BriefDescription": "L2 demand lock RFOs in I state (misses)", 500 "Counter": "0,1,2,3", 501 "EventCode": "0x27", 502 "EventName": "L2_WRITE.LOCK.I_STATE", 503 "SampleAfterValue": "100000", 504 "UMask": "0x10" 505 }, 506 { 507 "BriefDescription": "All demand L2 lock RFOs", 508 "Counter": "0,1,2,3", 509 "EventCode": "0x27", 510 "EventName": "L2_WRITE.LOCK.MESI", 511 "SampleAfterValue": "100000", 512 "UMask": "0xf0" 513 }, 514 { 515 "BriefDescription": "L2 demand lock RFOs in M state", 516 "Counter": "0,1,2,3", 517 "EventCode": "0x27", 518 "EventName": "L2_WRITE.LOCK.M_STATE", 519 "SampleAfterValue": "100000", 520 "UMask": "0x80" 521 }, 522 { 523 "BriefDescription": "L2 demand lock RFOs in S state", 524 "Counter": "0,1,2,3", 525 "EventCode": "0x27", 526 "EventName": "L2_WRITE.LOCK.S_STATE", 527 "SampleAfterValue": "100000", 528 "UMask": "0x20" 529 }, 530 { 531 "BriefDescription": "All L2 demand store RFOs that hit the cache", 532 "Counter": "0,1,2,3", 533 "EventCode": "0x27", 534 "EventName": "L2_WRITE.RFO.HIT", 535 "SampleAfterValue": "100000", 536 "UMask": "0xe" 537 }, 538 { 539 "BriefDescription": "L2 demand store RFOs in I state (misses)", 540 "Counter": "0,1,2,3", 541 "EventCode": "0x27", 542 "EventName": "L2_WRITE.RFO.I_STATE", 543 "SampleAfterValue": "100000", 544 "UMask": "0x1" 545 }, 546 { 547 "BriefDescription": "All L2 demand store RFOs", 548 "Counter": "0,1,2,3", 549 "EventCode": "0x27", 550 "EventName": "L2_WRITE.RFO.MESI", 551 "SampleAfterValue": "100000", 552 "UMask": "0xf" 553 }, 554 { 555 "BriefDescription": "L2 demand store RFOs in M state", 556 "Counter": "0,1,2,3", 557 "EventCode": "0x27", 558 "EventName": "L2_WRITE.RFO.M_STATE", 559 "SampleAfterValue": "100000", 560 "UMask": "0x8" 561 }, 562 { 563 "BriefDescription": "L2 demand store RFOs in S state", 564 "Counter": "0,1,2,3", 565 "EventCode": "0x27", 566 "EventName": "L2_WRITE.RFO.S_STATE", 567 "SampleAfterValue": "100000", 568 "UMask": "0x2" 569 }, 570 { 571 "BriefDescription": "Longest latency cache miss", 572 "Counter": "0,1,2,3", 573 "EventCode": "0x2E", 574 "EventName": "LONGEST_LAT_CACHE.MISS", 575 "SampleAfterValue": "100000", 576 "UMask": "0x41" 577 }, 578 { 579 "BriefDescription": "Longest latency cache reference", 580 "Counter": "0,1,2,3", 581 "EventCode": "0x2E", 582 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 583 "SampleAfterValue": "200000", 584 "UMask": "0x4f" 585 }, 586 { 587 "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)", 588 "Counter": "3", 589 "EventCode": "0xB", 590 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", 591 "MSRIndex": "0x3F6", 592 "PEBS": "2", 593 "SampleAfterValue": "2000000", 594 "UMask": "0x10" 595 }, 596 { 597 "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)", 598 "Counter": "3", 599 "EventCode": "0xB", 600 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", 601 "MSRIndex": "0x3F6", 602 "MSRValue": "0x400", 603 "PEBS": "2", 604 "SampleAfterValue": "100", 605 "UMask": "0x10" 606 }, 607 { 608 "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)", 609 "Counter": "3", 610 "EventCode": "0xB", 611 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", 612 "MSRIndex": "0x3F6", 613 "MSRValue": "0x80", 614 "PEBS": "2", 615 "SampleAfterValue": "1000", 616 "UMask": "0x10" 617 }, 618 { 619 "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)", 620 "Counter": "3", 621 "EventCode": "0xB", 622 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", 623 "MSRIndex": "0x3F6", 624 "MSRValue": "0x10", 625 "PEBS": "2", 626 "SampleAfterValue": "10000", 627 "UMask": "0x10" 628 }, 629 { 630 "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)", 631 "Counter": "3", 632 "EventCode": "0xB", 633 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", 634 "MSRIndex": "0x3F6", 635 "MSRValue": "0x4000", 636 "PEBS": "2", 637 "SampleAfterValue": "5", 638 "UMask": "0x10" 639 }, 640 { 641 "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)", 642 "Counter": "3", 643 "EventCode": "0xB", 644 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", 645 "MSRIndex": "0x3F6", 646 "MSRValue": "0x800", 647 "PEBS": "2", 648 "SampleAfterValue": "50", 649 "UMask": "0x10" 650 }, 651 { 652 "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)", 653 "Counter": "3", 654 "EventCode": "0xB", 655 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", 656 "MSRIndex": "0x3F6", 657 "MSRValue": "0x100", 658 "PEBS": "2", 659 "SampleAfterValue": "500", 660 "UMask": "0x10" 661 }, 662 { 663 "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)", 664 "Counter": "3", 665 "EventCode": "0xB", 666 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", 667 "MSRIndex": "0x3F6", 668 "MSRValue": "0x20", 669 "PEBS": "2", 670 "SampleAfterValue": "5000", 671 "UMask": "0x10" 672 }, 673 { 674 "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)", 675 "Counter": "3", 676 "EventCode": "0xB", 677 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", 678 "MSRIndex": "0x3F6", 679 "MSRValue": "0x8000", 680 "PEBS": "2", 681 "SampleAfterValue": "3", 682 "UMask": "0x10" 683 }, 684 { 685 "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)", 686 "Counter": "3", 687 "EventCode": "0xB", 688 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", 689 "MSRIndex": "0x3F6", 690 "MSRValue": "0x4", 691 "PEBS": "2", 692 "SampleAfterValue": "50000", 693 "UMask": "0x10" 694 }, 695 { 696 "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)", 697 "Counter": "3", 698 "EventCode": "0xB", 699 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", 700 "MSRIndex": "0x3F6", 701 "MSRValue": "0x1000", 702 "PEBS": "2", 703 "SampleAfterValue": "20", 704 "UMask": "0x10" 705 }, 706 { 707 "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)", 708 "Counter": "3", 709 "EventCode": "0xB", 710 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", 711 "MSRIndex": "0x3F6", 712 "MSRValue": "0x200", 713 "PEBS": "2", 714 "SampleAfterValue": "200", 715 "UMask": "0x10" 716 }, 717 { 718 "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)", 719 "Counter": "3", 720 "EventCode": "0xB", 721 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", 722 "MSRIndex": "0x3F6", 723 "MSRValue": "0x40", 724 "PEBS": "2", 725 "SampleAfterValue": "2000", 726 "UMask": "0x10" 727 }, 728 { 729 "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)", 730 "Counter": "3", 731 "EventCode": "0xB", 732 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", 733 "MSRIndex": "0x3F6", 734 "MSRValue": "0x8", 735 "PEBS": "2", 736 "SampleAfterValue": "20000", 737 "UMask": "0x10" 738 }, 739 { 740 "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)", 741 "Counter": "3", 742 "EventCode": "0xB", 743 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", 744 "MSRIndex": "0x3F6", 745 "MSRValue": "0x2000", 746 "PEBS": "2", 747 "SampleAfterValue": "10", 748 "UMask": "0x10" 749 }, 750 { 751 "BriefDescription": "Instructions retired which contains a load (Precise Event)", 752 "Counter": "0,1,2,3", 753 "EventCode": "0xB", 754 "EventName": "MEM_INST_RETIRED.LOADS", 755 "PEBS": "1", 756 "SampleAfterValue": "2000000", 757 "UMask": "0x1" 758 }, 759 { 760 "BriefDescription": "Instructions retired which contains a store (Precise Event)", 761 "Counter": "0,1,2,3", 762 "EventCode": "0xB", 763 "EventName": "MEM_INST_RETIRED.STORES", 764 "PEBS": "1", 765 "SampleAfterValue": "2000000", 766 "UMask": "0x2" 767 }, 768 { 769 "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)", 770 "Counter": "0,1,2,3", 771 "EventCode": "0xCB", 772 "EventName": "MEM_LOAD_RETIRED.HIT_LFB", 773 "PEBS": "1", 774 "SampleAfterValue": "200000", 775 "UMask": "0x40" 776 }, 777 { 778 "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)", 779 "Counter": "0,1,2,3", 780 "EventCode": "0xCB", 781 "EventName": "MEM_LOAD_RETIRED.L1D_HIT", 782 "PEBS": "1", 783 "SampleAfterValue": "2000000", 784 "UMask": "0x1" 785 }, 786 { 787 "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)", 788 "Counter": "0,1,2,3", 789 "EventCode": "0xCB", 790 "EventName": "MEM_LOAD_RETIRED.L2_HIT", 791 "PEBS": "1", 792 "SampleAfterValue": "200000", 793 "UMask": "0x2" 794 }, 795 { 796 "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)", 797 "Counter": "0,1,2,3", 798 "EventCode": "0xCB", 799 "EventName": "MEM_LOAD_RETIRED.LLC_MISS", 800 "PEBS": "1", 801 "SampleAfterValue": "10000", 802 "UMask": "0x10" 803 }, 804 { 805 "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)", 806 "Counter": "0,1,2,3", 807 "EventCode": "0xCB", 808 "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", 809 "PEBS": "1", 810 "SampleAfterValue": "40000", 811 "UMask": "0x4" 812 }, 813 { 814 "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)", 815 "Counter": "0,1,2,3", 816 "EventCode": "0xCB", 817 "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", 818 "PEBS": "1", 819 "SampleAfterValue": "40000", 820 "UMask": "0x8" 821 }, 822 { 823 "BriefDescription": "All offcore requests", 824 "Counter": "0,1,2,3", 825 "EventCode": "0xB0", 826 "EventName": "OFFCORE_REQUESTS.ANY", 827 "SampleAfterValue": "100000", 828 "UMask": "0x80" 829 }, 830 { 831 "BriefDescription": "Offcore read requests", 832 "Counter": "0,1,2,3", 833 "EventCode": "0xB0", 834 "EventName": "OFFCORE_REQUESTS.ANY.READ", 835 "SampleAfterValue": "100000", 836 "UMask": "0x8" 837 }, 838 { 839 "BriefDescription": "Offcore RFO requests", 840 "Counter": "0,1,2,3", 841 "EventCode": "0xB0", 842 "EventName": "OFFCORE_REQUESTS.ANY.RFO", 843 "SampleAfterValue": "100000", 844 "UMask": "0x10" 845 }, 846 { 847 "BriefDescription": "Offcore demand code read requests", 848 "Counter": "0,1,2,3", 849 "EventCode": "0xB0", 850 "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE", 851 "SampleAfterValue": "100000", 852 "UMask": "0x2" 853 }, 854 { 855 "BriefDescription": "Offcore demand data read requests", 856 "Counter": "0,1,2,3", 857 "EventCode": "0xB0", 858 "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA", 859 "SampleAfterValue": "100000", 860 "UMask": "0x1" 861 }, 862 { 863 "BriefDescription": "Offcore demand RFO requests", 864 "Counter": "0,1,2,3", 865 "EventCode": "0xB0", 866 "EventName": "OFFCORE_REQUESTS.DEMAND.RFO", 867 "SampleAfterValue": "100000", 868 "UMask": "0x4" 869 }, 870 { 871 "BriefDescription": "Offcore L1 data cache writebacks", 872 "Counter": "0,1,2,3", 873 "EventCode": "0xB0", 874 "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", 875 "SampleAfterValue": "100000", 876 "UMask": "0x40" 877 }, 878 { 879 "BriefDescription": "Outstanding offcore reads", 880 "Counter": "0", 881 "EventCode": "0x60", 882 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", 883 "SampleAfterValue": "2000000", 884 "UMask": "0x8" 885 }, 886 { 887 "BriefDescription": "Cycles offcore reads busy", 888 "Counter": "0", 889 "CounterMask": "1", 890 "EventCode": "0x60", 891 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY", 892 "SampleAfterValue": "2000000", 893 "UMask": "0x8" 894 }, 895 { 896 "BriefDescription": "Outstanding offcore demand code reads", 897 "Counter": "0", 898 "EventCode": "0x60", 899 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", 900 "SampleAfterValue": "2000000", 901 "UMask": "0x2" 902 }, 903 { 904 "BriefDescription": "Cycles offcore demand code read busy", 905 "Counter": "0", 906 "CounterMask": "1", 907 "EventCode": "0x60", 908 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY", 909 "SampleAfterValue": "2000000", 910 "UMask": "0x2" 911 }, 912 { 913 "BriefDescription": "Outstanding offcore demand data reads", 914 "Counter": "0", 915 "EventCode": "0x60", 916 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", 917 "SampleAfterValue": "2000000", 918 "UMask": "0x1" 919 }, 920 { 921 "BriefDescription": "Cycles offcore demand data read busy", 922 "Counter": "0", 923 "CounterMask": "1", 924 "EventCode": "0x60", 925 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY", 926 "SampleAfterValue": "2000000", 927 "UMask": "0x1" 928 }, 929 { 930 "BriefDescription": "Outstanding offcore demand RFOs", 931 "Counter": "0", 932 "EventCode": "0x60", 933 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", 934 "SampleAfterValue": "2000000", 935 "UMask": "0x4" 936 }, 937 { 938 "BriefDescription": "Cycles offcore demand RFOs busy", 939 "Counter": "0", 940 "CounterMask": "1", 941 "EventCode": "0x60", 942 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", 943 "SampleAfterValue": "2000000", 944 "UMask": "0x4" 945 }, 946 { 947 "BriefDescription": "Offcore requests blocked due to Super Queue full", 948 "Counter": "0,1,2,3", 949 "EventCode": "0xB2", 950 "EventName": "OFFCORE_REQUESTS_SQ_FULL", 951 "SampleAfterValue": "100000", 952 "UMask": "0x1" 953 }, 954 { 955 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 956 "Counter": "0,1,2,3", 957 "EventCode": "0xB7, 0xBB", 958 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 959 "MSRIndex": "0x1a6,0x1a7", 960 "MSRValue": "0x5011", 961 "SampleAfterValue": "100000", 962 "UMask": "0x1" 963 }, 964 { 965 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAM", 966 "Counter": "0,1,2,3", 967 "EventCode": "0xB7, 0xBB", 968 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", 969 "MSRIndex": "0x1a6,0x1a7", 970 "MSRValue": "0x7f11", 971 "SampleAfterValue": "100000", 972 "UMask": "0x1" 973 }, 974 { 975 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_LOCATION", 976 "Counter": "0,1,2,3", 977 "EventCode": "0xB7, 0xBB", 978 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", 979 "MSRIndex": "0x1a6,0x1a7", 980 "MSRValue": "0xff11", 981 "SampleAfterValue": "100000", 982 "UMask": "0x1" 983 }, 984 { 985 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = IO_CSR_MMIO", 986 "Counter": "0,1,2,3", 987 "EventCode": "0xB7, 0xBB", 988 "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", 989 "MSRIndex": "0x1a6,0x1a7", 990 "MSRValue": "0x8011", 991 "SampleAfterValue": "100000", 992 "UMask": "0x1" 993 }, 994 { 995 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_NO_OTHER_CORE", 996 "Counter": "0,1,2,3", 997 "EventCode": "0xB7, 0xBB", 998 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", 999 "MSRIndex": "0x1a6,0x1a7", 1000 "MSRValue": "0x111", 1001 "SampleAfterValue": "100000", 1002 "UMask": "0x1" 1003 }, 1004 { 1005 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 1006 "Counter": "0,1,2,3", 1007 "EventCode": "0xB7, 0xBB", 1008 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", 1009 "MSRIndex": "0x1a6,0x1a7", 1010 "MSRValue": "0x211", 1011 "SampleAfterValue": "100000", 1012 "UMask": "0x1" 1013 }, 1014 { 1015 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 1016 "Counter": "0,1,2,3", 1017 "EventCode": "0xB7, 0xBB", 1018 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", 1019 "MSRIndex": "0x1a6,0x1a7", 1020 "MSRValue": "0x411", 1021 "SampleAfterValue": "100000", 1022 "UMask": "0x1" 1023 }, 1024 { 1025 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_CACHE", 1026 "Counter": "0,1,2,3", 1027 "EventCode": "0xB7, 0xBB", 1028 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", 1029 "MSRIndex": "0x1a6,0x1a7", 1030 "MSRValue": "0x711", 1031 "SampleAfterValue": "100000", 1032 "UMask": "0x1" 1033 }, 1034 { 1035 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1036 "Counter": "0,1,2,3", 1037 "EventCode": "0xB7, 0xBB", 1038 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1039 "MSRIndex": "0x1a6,0x1a7", 1040 "MSRValue": "0x1011", 1041 "SampleAfterValue": "100000", 1042 "UMask": "0x1" 1043 }, 1044 { 1045 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = REMOTE_CACHE_HITM", 1046 "Counter": "0,1,2,3", 1047 "EventCode": "0xB7, 0xBB", 1048 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", 1049 "MSRIndex": "0x1a6,0x1a7", 1050 "MSRValue": "0x811", 1051 "SampleAfterValue": "100000", 1052 "UMask": "0x1" 1053 }, 1054 { 1055 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 1056 "Counter": "0,1,2,3", 1057 "EventCode": "0xB7, 0xBB", 1058 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1059 "MSRIndex": "0x1a6,0x1a7", 1060 "MSRValue": "0x5044", 1061 "SampleAfterValue": "100000", 1062 "UMask": "0x1" 1063 }, 1064 { 1065 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_CACHE_DRAM", 1066 "Counter": "0,1,2,3", 1067 "EventCode": "0xB7, 0xBB", 1068 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", 1069 "MSRIndex": "0x1a6,0x1a7", 1070 "MSRValue": "0x7f44", 1071 "SampleAfterValue": "100000", 1072 "UMask": "0x1" 1073 }, 1074 { 1075 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_LOCATION", 1076 "Counter": "0,1,2,3", 1077 "EventCode": "0xB7, 0xBB", 1078 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", 1079 "MSRIndex": "0x1a6,0x1a7", 1080 "MSRValue": "0xff44", 1081 "SampleAfterValue": "100000", 1082 "UMask": "0x1" 1083 }, 1084 { 1085 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = IO_CSR_MMIO", 1086 "Counter": "0,1,2,3", 1087 "EventCode": "0xB7, 0xBB", 1088 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", 1089 "MSRIndex": "0x1a6,0x1a7", 1090 "MSRValue": "0x8044", 1091 "SampleAfterValue": "100000", 1092 "UMask": "0x1" 1093 }, 1094 { 1095 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", 1096 "Counter": "0,1,2,3", 1097 "EventCode": "0xB7, 0xBB", 1098 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", 1099 "MSRIndex": "0x1a6,0x1a7", 1100 "MSRValue": "0x144", 1101 "SampleAfterValue": "100000", 1102 "UMask": "0x1" 1103 }, 1104 { 1105 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 1106 "Counter": "0,1,2,3", 1107 "EventCode": "0xB7, 0xBB", 1108 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1109 "MSRIndex": "0x1a6,0x1a7", 1110 "MSRValue": "0x244", 1111 "SampleAfterValue": "100000", 1112 "UMask": "0x1" 1113 }, 1114 { 1115 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 1116 "Counter": "0,1,2,3", 1117 "EventCode": "0xB7, 0xBB", 1118 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1119 "MSRIndex": "0x1a6,0x1a7", 1120 "MSRValue": "0x444", 1121 "SampleAfterValue": "100000", 1122 "UMask": "0x1" 1123 }, 1124 { 1125 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_CACHE", 1126 "Counter": "0,1,2,3", 1127 "EventCode": "0xB7, 0xBB", 1128 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", 1129 "MSRIndex": "0x1a6,0x1a7", 1130 "MSRValue": "0x744", 1131 "SampleAfterValue": "100000", 1132 "UMask": "0x1" 1133 }, 1134 { 1135 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1136 "Counter": "0,1,2,3", 1137 "EventCode": "0xB7, 0xBB", 1138 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1139 "MSRIndex": "0x1a6,0x1a7", 1140 "MSRValue": "0x1044", 1141 "SampleAfterValue": "100000", 1142 "UMask": "0x1" 1143 }, 1144 { 1145 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = REMOTE_CACHE_HITM", 1146 "Counter": "0,1,2,3", 1147 "EventCode": "0xB7, 0xBB", 1148 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", 1149 "MSRIndex": "0x1a6,0x1a7", 1150 "MSRValue": "0x844", 1151 "SampleAfterValue": "100000", 1152 "UMask": "0x1" 1153 }, 1154 { 1155 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 1156 "Counter": "0,1,2,3", 1157 "EventCode": "0xB7, 0xBB", 1158 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1159 "MSRIndex": "0x1a6,0x1a7", 1160 "MSRValue": "0x50ff", 1161 "SampleAfterValue": "100000", 1162 "UMask": "0x1" 1163 }, 1164 { 1165 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_CACHE_DRAM", 1166 "Counter": "0,1,2,3", 1167 "EventCode": "0xB7, 0xBB", 1168 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", 1169 "MSRIndex": "0x1a6,0x1a7", 1170 "MSRValue": "0x7fff", 1171 "SampleAfterValue": "100000", 1172 "UMask": "0x1" 1173 }, 1174 { 1175 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_LOCATION", 1176 "Counter": "0,1,2,3", 1177 "EventCode": "0xB7, 0xBB", 1178 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", 1179 "MSRIndex": "0x1a6,0x1a7", 1180 "MSRValue": "0xffff", 1181 "SampleAfterValue": "100000", 1182 "UMask": "0x1" 1183 }, 1184 { 1185 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = IO_CSR_MMIO", 1186 "Counter": "0,1,2,3", 1187 "EventCode": "0xB7, 0xBB", 1188 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", 1189 "MSRIndex": "0x1a6,0x1a7", 1190 "MSRValue": "0x80ff", 1191 "SampleAfterValue": "100000", 1192 "UMask": "0x1" 1193 }, 1194 { 1195 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_NO_OTHER_CORE", 1196 "Counter": "0,1,2,3", 1197 "EventCode": "0xB7, 0xBB", 1198 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", 1199 "MSRIndex": "0x1a6,0x1a7", 1200 "MSRValue": "0x1ff", 1201 "SampleAfterValue": "100000", 1202 "UMask": "0x1" 1203 }, 1204 { 1205 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 1206 "Counter": "0,1,2,3", 1207 "EventCode": "0xB7, 0xBB", 1208 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", 1209 "MSRIndex": "0x1a6,0x1a7", 1210 "MSRValue": "0x2ff", 1211 "SampleAfterValue": "100000", 1212 "UMask": "0x1" 1213 }, 1214 { 1215 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 1216 "Counter": "0,1,2,3", 1217 "EventCode": "0xB7, 0xBB", 1218 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", 1219 "MSRIndex": "0x1a6,0x1a7", 1220 "MSRValue": "0x4ff", 1221 "SampleAfterValue": "100000", 1222 "UMask": "0x1" 1223 }, 1224 { 1225 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_CACHE", 1226 "Counter": "0,1,2,3", 1227 "EventCode": "0xB7, 0xBB", 1228 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", 1229 "MSRIndex": "0x1a6,0x1a7", 1230 "MSRValue": "0x7ff", 1231 "SampleAfterValue": "100000", 1232 "UMask": "0x1" 1233 }, 1234 { 1235 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1236 "Counter": "0,1,2,3", 1237 "EventCode": "0xB7, 0xBB", 1238 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1239 "MSRIndex": "0x1a6,0x1a7", 1240 "MSRValue": "0x10ff", 1241 "SampleAfterValue": "100000", 1242 "UMask": "0x1" 1243 }, 1244 { 1245 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = REMOTE_CACHE_HITM", 1246 "Counter": "0,1,2,3", 1247 "EventCode": "0xB7, 0xBB", 1248 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", 1249 "MSRIndex": "0x1a6,0x1a7", 1250 "MSRValue": "0x8ff", 1251 "SampleAfterValue": "100000", 1252 "UMask": "0x1" 1253 }, 1254 { 1255 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 1256 "Counter": "0,1,2,3", 1257 "EventCode": "0xB7, 0xBB", 1258 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1259 "MSRIndex": "0x1a6,0x1a7", 1260 "MSRValue": "0x5022", 1261 "SampleAfterValue": "100000", 1262 "UMask": "0x1" 1263 }, 1264 { 1265 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_CACHE_DRAM", 1266 "Counter": "0,1,2,3", 1267 "EventCode": "0xB7, 0xBB", 1268 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", 1269 "MSRIndex": "0x1a6,0x1a7", 1270 "MSRValue": "0x7f22", 1271 "SampleAfterValue": "100000", 1272 "UMask": "0x1" 1273 }, 1274 { 1275 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_LOCATION", 1276 "Counter": "0,1,2,3", 1277 "EventCode": "0xB7, 0xBB", 1278 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", 1279 "MSRIndex": "0x1a6,0x1a7", 1280 "MSRValue": "0xff22", 1281 "SampleAfterValue": "100000", 1282 "UMask": "0x1" 1283 }, 1284 { 1285 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = IO_CSR_MMIO", 1286 "Counter": "0,1,2,3", 1287 "EventCode": "0xB7, 0xBB", 1288 "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", 1289 "MSRIndex": "0x1a6,0x1a7", 1290 "MSRValue": "0x8022", 1291 "SampleAfterValue": "100000", 1292 "UMask": "0x1" 1293 }, 1294 { 1295 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE", 1296 "Counter": "0,1,2,3", 1297 "EventCode": "0xB7, 0xBB", 1298 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", 1299 "MSRIndex": "0x1a6,0x1a7", 1300 "MSRValue": "0x122", 1301 "SampleAfterValue": "100000", 1302 "UMask": "0x1" 1303 }, 1304 { 1305 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 1306 "Counter": "0,1,2,3", 1307 "EventCode": "0xB7, 0xBB", 1308 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", 1309 "MSRIndex": "0x1a6,0x1a7", 1310 "MSRValue": "0x222", 1311 "SampleAfterValue": "100000", 1312 "UMask": "0x1" 1313 }, 1314 { 1315 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 1316 "Counter": "0,1,2,3", 1317 "EventCode": "0xB7, 0xBB", 1318 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", 1319 "MSRIndex": "0x1a6,0x1a7", 1320 "MSRValue": "0x422", 1321 "SampleAfterValue": "100000", 1322 "UMask": "0x1" 1323 }, 1324 { 1325 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LOCAL_CACHE", 1326 "Counter": "0,1,2,3", 1327 "EventCode": "0xB7, 0xBB", 1328 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", 1329 "MSRIndex": "0x1a6,0x1a7", 1330 "MSRValue": "0x722", 1331 "SampleAfterValue": "100000", 1332 "UMask": "0x1" 1333 }, 1334 { 1335 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1336 "Counter": "0,1,2,3", 1337 "EventCode": "0xB7, 0xBB", 1338 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1339 "MSRIndex": "0x1a6,0x1a7", 1340 "MSRValue": "0x1022", 1341 "SampleAfterValue": "100000", 1342 "UMask": "0x1" 1343 }, 1344 { 1345 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = REMOTE_CACHE_HITM", 1346 "Counter": "0,1,2,3", 1347 "EventCode": "0xB7, 0xBB", 1348 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", 1349 "MSRIndex": "0x1a6,0x1a7", 1350 "MSRValue": "0x822", 1351 "SampleAfterValue": "100000", 1352 "UMask": "0x1" 1353 }, 1354 { 1355 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 1356 "Counter": "0,1,2,3", 1357 "EventCode": "0xB7, 0xBB", 1358 "EventName": "OFFCORE_RESPONSE.COREWB.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1359 "MSRIndex": "0x1a6,0x1a7", 1360 "MSRValue": "0x5008", 1361 "SampleAfterValue": "100000", 1362 "UMask": "0x1" 1363 }, 1364 { 1365 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_CACHE_DRAM", 1366 "Counter": "0,1,2,3", 1367 "EventCode": "0xB7, 0xBB", 1368 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", 1369 "MSRIndex": "0x1a6,0x1a7", 1370 "MSRValue": "0x7f08", 1371 "SampleAfterValue": "100000", 1372 "UMask": "0x1" 1373 }, 1374 { 1375 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_LOCATION", 1376 "Counter": "0,1,2,3", 1377 "EventCode": "0xB7, 0xBB", 1378 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", 1379 "MSRIndex": "0x1a6,0x1a7", 1380 "MSRValue": "0xff08", 1381 "SampleAfterValue": "100000", 1382 "UMask": "0x1" 1383 }, 1384 { 1385 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = IO_CSR_MMIO", 1386 "Counter": "0,1,2,3", 1387 "EventCode": "0xB7, 0xBB", 1388 "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", 1389 "MSRIndex": "0x1a6,0x1a7", 1390 "MSRValue": "0x8008", 1391 "SampleAfterValue": "100000", 1392 "UMask": "0x1" 1393 }, 1394 { 1395 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_NO_OTHER_CORE", 1396 "Counter": "0,1,2,3", 1397 "EventCode": "0xB7, 0xBB", 1398 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", 1399 "MSRIndex": "0x1a6,0x1a7", 1400 "MSRValue": "0x108", 1401 "SampleAfterValue": "100000", 1402 "UMask": "0x1" 1403 }, 1404 { 1405 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 1406 "Counter": "0,1,2,3", 1407 "EventCode": "0xB7, 0xBB", 1408 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HIT", 1409 "MSRIndex": "0x1a6,0x1a7", 1410 "MSRValue": "0x208", 1411 "SampleAfterValue": "100000", 1412 "UMask": "0x1" 1413 }, 1414 { 1415 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 1416 "Counter": "0,1,2,3", 1417 "EventCode": "0xB7, 0xBB", 1418 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", 1419 "MSRIndex": "0x1a6,0x1a7", 1420 "MSRValue": "0x408", 1421 "SampleAfterValue": "100000", 1422 "UMask": "0x1" 1423 }, 1424 { 1425 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LOCAL_CACHE", 1426 "Counter": "0,1,2,3", 1427 "EventCode": "0xB7, 0xBB", 1428 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", 1429 "MSRIndex": "0x1a6,0x1a7", 1430 "MSRValue": "0x708", 1431 "SampleAfterValue": "100000", 1432 "UMask": "0x1" 1433 }, 1434 { 1435 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1436 "Counter": "0,1,2,3", 1437 "EventCode": "0xB7, 0xBB", 1438 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1439 "MSRIndex": "0x1a6,0x1a7", 1440 "MSRValue": "0x1008", 1441 "SampleAfterValue": "100000", 1442 "UMask": "0x1" 1443 }, 1444 { 1445 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = REMOTE_CACHE_HITM", 1446 "Counter": "0,1,2,3", 1447 "EventCode": "0xB7, 0xBB", 1448 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", 1449 "MSRIndex": "0x1a6,0x1a7", 1450 "MSRValue": "0x808", 1451 "SampleAfterValue": "100000", 1452 "UMask": "0x1" 1453 }, 1454 { 1455 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 1456 "Counter": "0,1,2,3", 1457 "EventCode": "0xB7, 0xBB", 1458 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1459 "MSRIndex": "0x1a6,0x1a7", 1460 "MSRValue": "0x5077", 1461 "SampleAfterValue": "100000", 1462 "UMask": "0x1" 1463 }, 1464 { 1465 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_CACHE_DRAM", 1466 "Counter": "0,1,2,3", 1467 "EventCode": "0xB7, 0xBB", 1468 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", 1469 "MSRIndex": "0x1a6,0x1a7", 1470 "MSRValue": "0x7f77", 1471 "SampleAfterValue": "100000", 1472 "UMask": "0x1" 1473 }, 1474 { 1475 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_LOCATION", 1476 "Counter": "0,1,2,3", 1477 "EventCode": "0xB7, 0xBB", 1478 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", 1479 "MSRIndex": "0x1a6,0x1a7", 1480 "MSRValue": "0xff77", 1481 "SampleAfterValue": "100000", 1482 "UMask": "0x1" 1483 }, 1484 { 1485 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = IO_CSR_MMIO", 1486 "Counter": "0,1,2,3", 1487 "EventCode": "0xB7, 0xBB", 1488 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", 1489 "MSRIndex": "0x1a6,0x1a7", 1490 "MSRValue": "0x8077", 1491 "SampleAfterValue": "100000", 1492 "UMask": "0x1" 1493 }, 1494 { 1495 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", 1496 "Counter": "0,1,2,3", 1497 "EventCode": "0xB7, 0xBB", 1498 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", 1499 "MSRIndex": "0x1a6,0x1a7", 1500 "MSRValue": "0x177", 1501 "SampleAfterValue": "100000", 1502 "UMask": "0x1" 1503 }, 1504 { 1505 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 1506 "Counter": "0,1,2,3", 1507 "EventCode": "0xB7, 0xBB", 1508 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1509 "MSRIndex": "0x1a6,0x1a7", 1510 "MSRValue": "0x277", 1511 "SampleAfterValue": "100000", 1512 "UMask": "0x1" 1513 }, 1514 { 1515 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 1516 "Counter": "0,1,2,3", 1517 "EventCode": "0xB7, 0xBB", 1518 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1519 "MSRIndex": "0x1a6,0x1a7", 1520 "MSRValue": "0x477", 1521 "SampleAfterValue": "100000", 1522 "UMask": "0x1" 1523 }, 1524 { 1525 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LOCAL_CACHE", 1526 "Counter": "0,1,2,3", 1527 "EventCode": "0xB7, 0xBB", 1528 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", 1529 "MSRIndex": "0x1a6,0x1a7", 1530 "MSRValue": "0x777", 1531 "SampleAfterValue": "100000", 1532 "UMask": "0x1" 1533 }, 1534 { 1535 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1536 "Counter": "0,1,2,3", 1537 "EventCode": "0xB7, 0xBB", 1538 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1539 "MSRIndex": "0x1a6,0x1a7", 1540 "MSRValue": "0x1077", 1541 "SampleAfterValue": "100000", 1542 "UMask": "0x1" 1543 }, 1544 { 1545 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = REMOTE_CACHE_HITM", 1546 "Counter": "0,1,2,3", 1547 "EventCode": "0xB7, 0xBB", 1548 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", 1549 "MSRIndex": "0x1a6,0x1a7", 1550 "MSRValue": "0x877", 1551 "SampleAfterValue": "100000", 1552 "UMask": "0x1" 1553 }, 1554 { 1555 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 1556 "Counter": "0,1,2,3", 1557 "EventCode": "0xB7, 0xBB", 1558 "EventName": "OFFCORE_RESPONSE.DATA_IN.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1559 "MSRIndex": "0x1a6,0x1a7", 1560 "MSRValue": "0x5033", 1561 "SampleAfterValue": "100000", 1562 "UMask": "0x1" 1563 }, 1564 { 1565 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_CACHE_DRAM", 1566 "Counter": "0,1,2,3", 1567 "EventCode": "0xB7, 0xBB", 1568 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", 1569 "MSRIndex": "0x1a6,0x1a7", 1570 "MSRValue": "0x7f33", 1571 "SampleAfterValue": "100000", 1572 "UMask": "0x1" 1573 }, 1574 { 1575 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_LOCATION", 1576 "Counter": "0,1,2,3", 1577 "EventCode": "0xB7, 0xBB", 1578 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", 1579 "MSRIndex": "0x1a6,0x1a7", 1580 "MSRValue": "0xff33", 1581 "SampleAfterValue": "100000", 1582 "UMask": "0x1" 1583 }, 1584 { 1585 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = IO_CSR_MMIO", 1586 "Counter": "0,1,2,3", 1587 "EventCode": "0xB7, 0xBB", 1588 "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", 1589 "MSRIndex": "0x1a6,0x1a7", 1590 "MSRValue": "0x8033", 1591 "SampleAfterValue": "100000", 1592 "UMask": "0x1" 1593 }, 1594 { 1595 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_NO_OTHER_CORE", 1596 "Counter": "0,1,2,3", 1597 "EventCode": "0xB7, 0xBB", 1598 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", 1599 "MSRIndex": "0x1a6,0x1a7", 1600 "MSRValue": "0x133", 1601 "SampleAfterValue": "100000", 1602 "UMask": "0x1" 1603 }, 1604 { 1605 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 1606 "Counter": "0,1,2,3", 1607 "EventCode": "0xB7, 0xBB", 1608 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", 1609 "MSRIndex": "0x1a6,0x1a7", 1610 "MSRValue": "0x233", 1611 "SampleAfterValue": "100000", 1612 "UMask": "0x1" 1613 }, 1614 { 1615 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 1616 "Counter": "0,1,2,3", 1617 "EventCode": "0xB7, 0xBB", 1618 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", 1619 "MSRIndex": "0x1a6,0x1a7", 1620 "MSRValue": "0x433", 1621 "SampleAfterValue": "100000", 1622 "UMask": "0x1" 1623 }, 1624 { 1625 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LOCAL_CACHE", 1626 "Counter": "0,1,2,3", 1627 "EventCode": "0xB7, 0xBB", 1628 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", 1629 "MSRIndex": "0x1a6,0x1a7", 1630 "MSRValue": "0x733", 1631 "SampleAfterValue": "100000", 1632 "UMask": "0x1" 1633 }, 1634 { 1635 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1636 "Counter": "0,1,2,3", 1637 "EventCode": "0xB7, 0xBB", 1638 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1639 "MSRIndex": "0x1a6,0x1a7", 1640 "MSRValue": "0x1033", 1641 "SampleAfterValue": "100000", 1642 "UMask": "0x1" 1643 }, 1644 { 1645 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = REMOTE_CACHE_HITM", 1646 "Counter": "0,1,2,3", 1647 "EventCode": "0xB7, 0xBB", 1648 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", 1649 "MSRIndex": "0x1a6,0x1a7", 1650 "MSRValue": "0x833", 1651 "SampleAfterValue": "100000", 1652 "UMask": "0x1" 1653 }, 1654 { 1655 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 1656 "Counter": "0,1,2,3", 1657 "EventCode": "0xB7, 0xBB", 1658 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1659 "MSRIndex": "0x1a6,0x1a7", 1660 "MSRValue": "0x5003", 1661 "SampleAfterValue": "100000", 1662 "UMask": "0x1" 1663 }, 1664 { 1665 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_CACHE_DRAM", 1666 "Counter": "0,1,2,3", 1667 "EventCode": "0xB7, 0xBB", 1668 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", 1669 "MSRIndex": "0x1a6,0x1a7", 1670 "MSRValue": "0x7f03", 1671 "SampleAfterValue": "100000", 1672 "UMask": "0x1" 1673 }, 1674 { 1675 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_LOCATION", 1676 "Counter": "0,1,2,3", 1677 "EventCode": "0xB7, 0xBB", 1678 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", 1679 "MSRIndex": "0x1a6,0x1a7", 1680 "MSRValue": "0xff03", 1681 "SampleAfterValue": "100000", 1682 "UMask": "0x1" 1683 }, 1684 { 1685 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = IO_CSR_MMIO", 1686 "Counter": "0,1,2,3", 1687 "EventCode": "0xB7, 0xBB", 1688 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", 1689 "MSRIndex": "0x1a6,0x1a7", 1690 "MSRValue": "0x8003", 1691 "SampleAfterValue": "100000", 1692 "UMask": "0x1" 1693 }, 1694 { 1695 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE", 1696 "Counter": "0,1,2,3", 1697 "EventCode": "0xB7, 0xBB", 1698 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", 1699 "MSRIndex": "0x1a6,0x1a7", 1700 "MSRValue": "0x103", 1701 "SampleAfterValue": "100000", 1702 "UMask": "0x1" 1703 }, 1704 { 1705 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 1706 "Counter": "0,1,2,3", 1707 "EventCode": "0xB7, 0xBB", 1708 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", 1709 "MSRIndex": "0x1a6,0x1a7", 1710 "MSRValue": "0x203", 1711 "SampleAfterValue": "100000", 1712 "UMask": "0x1" 1713 }, 1714 { 1715 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 1716 "Counter": "0,1,2,3", 1717 "EventCode": "0xB7, 0xBB", 1718 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", 1719 "MSRIndex": "0x1a6,0x1a7", 1720 "MSRValue": "0x403", 1721 "SampleAfterValue": "100000", 1722 "UMask": "0x1" 1723 }, 1724 { 1725 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LOCAL_CACHE", 1726 "Counter": "0,1,2,3", 1727 "EventCode": "0xB7, 0xBB", 1728 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", 1729 "MSRIndex": "0x1a6,0x1a7", 1730 "MSRValue": "0x703", 1731 "SampleAfterValue": "100000", 1732 "UMask": "0x1" 1733 }, 1734 { 1735 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1736 "Counter": "0,1,2,3", 1737 "EventCode": "0xB7, 0xBB", 1738 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1739 "MSRIndex": "0x1a6,0x1a7", 1740 "MSRValue": "0x1003", 1741 "SampleAfterValue": "100000", 1742 "UMask": "0x1" 1743 }, 1744 { 1745 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = REMOTE_CACHE_HITM", 1746 "Counter": "0,1,2,3", 1747 "EventCode": "0xB7, 0xBB", 1748 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", 1749 "MSRIndex": "0x1a6,0x1a7", 1750 "MSRValue": "0x803", 1751 "SampleAfterValue": "100000", 1752 "UMask": "0x1" 1753 }, 1754 { 1755 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 1756 "Counter": "0,1,2,3", 1757 "EventCode": "0xB7, 0xBB", 1758 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1759 "MSRIndex": "0x1a6,0x1a7", 1760 "MSRValue": "0x5001", 1761 "SampleAfterValue": "100000", 1762 "UMask": "0x1" 1763 }, 1764 { 1765 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_CACHE_DRAM", 1766 "Counter": "0,1,2,3", 1767 "EventCode": "0xB7, 0xBB", 1768 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", 1769 "MSRIndex": "0x1a6,0x1a7", 1770 "MSRValue": "0x7f01", 1771 "SampleAfterValue": "100000", 1772 "UMask": "0x1" 1773 }, 1774 { 1775 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LOCATION", 1776 "Counter": "0,1,2,3", 1777 "EventCode": "0xB7, 0xBB", 1778 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", 1779 "MSRIndex": "0x1a6,0x1a7", 1780 "MSRValue": "0xff01", 1781 "SampleAfterValue": "100000", 1782 "UMask": "0x1" 1783 }, 1784 { 1785 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = IO_CSR_MMIO", 1786 "Counter": "0,1,2,3", 1787 "EventCode": "0xB7, 0xBB", 1788 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", 1789 "MSRIndex": "0x1a6,0x1a7", 1790 "MSRValue": "0x8001", 1791 "SampleAfterValue": "100000", 1792 "UMask": "0x1" 1793 }, 1794 { 1795 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE", 1796 "Counter": "0,1,2,3", 1797 "EventCode": "0xB7, 0xBB", 1798 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", 1799 "MSRIndex": "0x1a6,0x1a7", 1800 "MSRValue": "0x101", 1801 "SampleAfterValue": "100000", 1802 "UMask": "0x1" 1803 }, 1804 { 1805 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 1806 "Counter": "0,1,2,3", 1807 "EventCode": "0xB7, 0xBB", 1808 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 1809 "MSRIndex": "0x1a6,0x1a7", 1810 "MSRValue": "0x201", 1811 "SampleAfterValue": "100000", 1812 "UMask": "0x1" 1813 }, 1814 { 1815 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 1816 "Counter": "0,1,2,3", 1817 "EventCode": "0xB7, 0xBB", 1818 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 1819 "MSRIndex": "0x1a6,0x1a7", 1820 "MSRValue": "0x401", 1821 "SampleAfterValue": "100000", 1822 "UMask": "0x1" 1823 }, 1824 { 1825 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_CACHE", 1826 "Counter": "0,1,2,3", 1827 "EventCode": "0xB7, 0xBB", 1828 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", 1829 "MSRIndex": "0x1a6,0x1a7", 1830 "MSRValue": "0x701", 1831 "SampleAfterValue": "100000", 1832 "UMask": "0x1" 1833 }, 1834 { 1835 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1836 "Counter": "0,1,2,3", 1837 "EventCode": "0xB7, 0xBB", 1838 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1839 "MSRIndex": "0x1a6,0x1a7", 1840 "MSRValue": "0x1001", 1841 "SampleAfterValue": "100000", 1842 "UMask": "0x1" 1843 }, 1844 { 1845 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_CACHE_HITM", 1846 "Counter": "0,1,2,3", 1847 "EventCode": "0xB7, 0xBB", 1848 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", 1849 "MSRIndex": "0x1a6,0x1a7", 1850 "MSRValue": "0x801", 1851 "SampleAfterValue": "100000", 1852 "UMask": "0x1" 1853 }, 1854 { 1855 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 1856 "Counter": "0,1,2,3", 1857 "EventCode": "0xB7, 0xBB", 1858 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1859 "MSRIndex": "0x1a6,0x1a7", 1860 "MSRValue": "0x5004", 1861 "SampleAfterValue": "100000", 1862 "UMask": "0x1" 1863 }, 1864 { 1865 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_CACHE_DRAM", 1866 "Counter": "0,1,2,3", 1867 "EventCode": "0xB7, 0xBB", 1868 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", 1869 "MSRIndex": "0x1a6,0x1a7", 1870 "MSRValue": "0x7f04", 1871 "SampleAfterValue": "100000", 1872 "UMask": "0x1" 1873 }, 1874 { 1875 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LOCATION", 1876 "Counter": "0,1,2,3", 1877 "EventCode": "0xB7, 0xBB", 1878 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", 1879 "MSRIndex": "0x1a6,0x1a7", 1880 "MSRValue": "0xff04", 1881 "SampleAfterValue": "100000", 1882 "UMask": "0x1" 1883 }, 1884 { 1885 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = IO_CSR_MMIO", 1886 "Counter": "0,1,2,3", 1887 "EventCode": "0xB7, 0xBB", 1888 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", 1889 "MSRIndex": "0x1a6,0x1a7", 1890 "MSRValue": "0x8004", 1891 "SampleAfterValue": "100000", 1892 "UMask": "0x1" 1893 }, 1894 { 1895 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", 1896 "Counter": "0,1,2,3", 1897 "EventCode": "0xB7, 0xBB", 1898 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", 1899 "MSRIndex": "0x1a6,0x1a7", 1900 "MSRValue": "0x104", 1901 "SampleAfterValue": "100000", 1902 "UMask": "0x1" 1903 }, 1904 { 1905 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 1906 "Counter": "0,1,2,3", 1907 "EventCode": "0xB7, 0xBB", 1908 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1909 "MSRIndex": "0x1a6,0x1a7", 1910 "MSRValue": "0x204", 1911 "SampleAfterValue": "100000", 1912 "UMask": "0x1" 1913 }, 1914 { 1915 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 1916 "Counter": "0,1,2,3", 1917 "EventCode": "0xB7, 0xBB", 1918 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1919 "MSRIndex": "0x1a6,0x1a7", 1920 "MSRValue": "0x404", 1921 "SampleAfterValue": "100000", 1922 "UMask": "0x1" 1923 }, 1924 { 1925 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_CACHE", 1926 "Counter": "0,1,2,3", 1927 "EventCode": "0xB7, 0xBB", 1928 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", 1929 "MSRIndex": "0x1a6,0x1a7", 1930 "MSRValue": "0x704", 1931 "SampleAfterValue": "100000", 1932 "UMask": "0x1" 1933 }, 1934 { 1935 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 1936 "Counter": "0,1,2,3", 1937 "EventCode": "0xB7, 0xBB", 1938 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1939 "MSRIndex": "0x1a6,0x1a7", 1940 "MSRValue": "0x1004", 1941 "SampleAfterValue": "100000", 1942 "UMask": "0x1" 1943 }, 1944 { 1945 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_CACHE_HITM", 1946 "Counter": "0,1,2,3", 1947 "EventCode": "0xB7, 0xBB", 1948 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", 1949 "MSRIndex": "0x1a6,0x1a7", 1950 "MSRValue": "0x804", 1951 "SampleAfterValue": "100000", 1952 "UMask": "0x1" 1953 }, 1954 { 1955 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 1956 "Counter": "0,1,2,3", 1957 "EventCode": "0xB7, 0xBB", 1958 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 1959 "MSRIndex": "0x1a6,0x1a7", 1960 "MSRValue": "0x5002", 1961 "SampleAfterValue": "100000", 1962 "UMask": "0x1" 1963 }, 1964 { 1965 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_CACHE_DRAM", 1966 "Counter": "0,1,2,3", 1967 "EventCode": "0xB7, 0xBB", 1968 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", 1969 "MSRIndex": "0x1a6,0x1a7", 1970 "MSRValue": "0x7f02", 1971 "SampleAfterValue": "100000", 1972 "UMask": "0x1" 1973 }, 1974 { 1975 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_LOCATION", 1976 "Counter": "0,1,2,3", 1977 "EventCode": "0xB7, 0xBB", 1978 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", 1979 "MSRIndex": "0x1a6,0x1a7", 1980 "MSRValue": "0xff02", 1981 "SampleAfterValue": "100000", 1982 "UMask": "0x1" 1983 }, 1984 { 1985 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = IO_CSR_MMIO", 1986 "Counter": "0,1,2,3", 1987 "EventCode": "0xB7, 0xBB", 1988 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", 1989 "MSRIndex": "0x1a6,0x1a7", 1990 "MSRValue": "0x8002", 1991 "SampleAfterValue": "100000", 1992 "UMask": "0x1" 1993 }, 1994 { 1995 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE", 1996 "Counter": "0,1,2,3", 1997 "EventCode": "0xB7, 0xBB", 1998 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", 1999 "MSRIndex": "0x1a6,0x1a7", 2000 "MSRValue": "0x102", 2001 "SampleAfterValue": "100000", 2002 "UMask": "0x1" 2003 }, 2004 { 2005 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 2006 "Counter": "0,1,2,3", 2007 "EventCode": "0xB7, 0xBB", 2008 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", 2009 "MSRIndex": "0x1a6,0x1a7", 2010 "MSRValue": "0x202", 2011 "SampleAfterValue": "100000", 2012 "UMask": "0x1" 2013 }, 2014 { 2015 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 2016 "Counter": "0,1,2,3", 2017 "EventCode": "0xB7, 0xBB", 2018 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", 2019 "MSRIndex": "0x1a6,0x1a7", 2020 "MSRValue": "0x402", 2021 "SampleAfterValue": "100000", 2022 "UMask": "0x1" 2023 }, 2024 { 2025 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LOCAL_CACHE", 2026 "Counter": "0,1,2,3", 2027 "EventCode": "0xB7, 0xBB", 2028 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", 2029 "MSRIndex": "0x1a6,0x1a7", 2030 "MSRValue": "0x702", 2031 "SampleAfterValue": "100000", 2032 "UMask": "0x1" 2033 }, 2034 { 2035 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 2036 "Counter": "0,1,2,3", 2037 "EventCode": "0xB7, 0xBB", 2038 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2039 "MSRIndex": "0x1a6,0x1a7", 2040 "MSRValue": "0x1002", 2041 "SampleAfterValue": "100000", 2042 "UMask": "0x1" 2043 }, 2044 { 2045 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = REMOTE_CACHE_HITM", 2046 "Counter": "0,1,2,3", 2047 "EventCode": "0xB7, 0xBB", 2048 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", 2049 "MSRIndex": "0x1a6,0x1a7", 2050 "MSRValue": "0x802", 2051 "SampleAfterValue": "100000", 2052 "UMask": "0x1" 2053 }, 2054 { 2055 "BriefDescription": "REQUEST = OTHER and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 2056 "Counter": "0,1,2,3", 2057 "EventCode": "0xB7, 0xBB", 2058 "EventName": "OFFCORE_RESPONSE.OTHER.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2059 "MSRIndex": "0x1a6,0x1a7", 2060 "MSRValue": "0x5080", 2061 "SampleAfterValue": "100000", 2062 "UMask": "0x1" 2063 }, 2064 { 2065 "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_CACHE_DRAM", 2066 "Counter": "0,1,2,3", 2067 "EventCode": "0xB7, 0xBB", 2068 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", 2069 "MSRIndex": "0x1a6,0x1a7", 2070 "MSRValue": "0x7f80", 2071 "SampleAfterValue": "100000", 2072 "UMask": "0x1" 2073 }, 2074 { 2075 "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_LOCATION", 2076 "Counter": "0,1,2,3", 2077 "EventCode": "0xB7, 0xBB", 2078 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", 2079 "MSRIndex": "0x1a6,0x1a7", 2080 "MSRValue": "0xff80", 2081 "SampleAfterValue": "100000", 2082 "UMask": "0x1" 2083 }, 2084 { 2085 "BriefDescription": "REQUEST = OTHER and RESPONSE = IO_CSR_MMIO", 2086 "Counter": "0,1,2,3", 2087 "EventCode": "0xB7, 0xBB", 2088 "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", 2089 "MSRIndex": "0x1a6,0x1a7", 2090 "MSRValue": "0x8080", 2091 "SampleAfterValue": "100000", 2092 "UMask": "0x1" 2093 }, 2094 { 2095 "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_NO_OTHER_CORE", 2096 "Counter": "0,1,2,3", 2097 "EventCode": "0xB7, 0xBB", 2098 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", 2099 "MSRIndex": "0x1a6,0x1a7", 2100 "MSRValue": "0x180", 2101 "SampleAfterValue": "100000", 2102 "UMask": "0x1" 2103 }, 2104 { 2105 "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 2106 "Counter": "0,1,2,3", 2107 "EventCode": "0xB7, 0xBB", 2108 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", 2109 "MSRIndex": "0x1a6,0x1a7", 2110 "MSRValue": "0x280", 2111 "SampleAfterValue": "100000", 2112 "UMask": "0x1" 2113 }, 2114 { 2115 "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 2116 "Counter": "0,1,2,3", 2117 "EventCode": "0xB7, 0xBB", 2118 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", 2119 "MSRIndex": "0x1a6,0x1a7", 2120 "MSRValue": "0x480", 2121 "SampleAfterValue": "100000", 2122 "UMask": "0x1" 2123 }, 2124 { 2125 "BriefDescription": "REQUEST = OTHER and RESPONSE = LOCAL_CACHE", 2126 "Counter": "0,1,2,3", 2127 "EventCode": "0xB7, 0xBB", 2128 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", 2129 "MSRIndex": "0x1a6,0x1a7", 2130 "MSRValue": "0x780", 2131 "SampleAfterValue": "100000", 2132 "UMask": "0x1" 2133 }, 2134 { 2135 "BriefDescription": "REQUEST = OTHER and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 2136 "Counter": "0,1,2,3", 2137 "EventCode": "0xB7, 0xBB", 2138 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2139 "MSRIndex": "0x1a6,0x1a7", 2140 "MSRValue": "0x1080", 2141 "SampleAfterValue": "100000", 2142 "UMask": "0x1" 2143 }, 2144 { 2145 "BriefDescription": "REQUEST = OTHER and RESPONSE = REMOTE_CACHE_HITM", 2146 "Counter": "0,1,2,3", 2147 "EventCode": "0xB7, 0xBB", 2148 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", 2149 "MSRIndex": "0x1a6,0x1a7", 2150 "MSRValue": "0x880", 2151 "SampleAfterValue": "100000", 2152 "UMask": "0x1" 2153 }, 2154 { 2155 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 2156 "Counter": "0,1,2,3", 2157 "EventCode": "0xB7, 0xBB", 2158 "EventName": "OFFCORE_RESPONSE.PF_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2159 "MSRIndex": "0x1a6,0x1a7", 2160 "MSRValue": "0x5050", 2161 "SampleAfterValue": "100000", 2162 "UMask": "0x1" 2163 }, 2164 { 2165 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_CACHE_DRAM", 2166 "Counter": "0,1,2,3", 2167 "EventCode": "0xB7, 0xBB", 2168 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", 2169 "MSRIndex": "0x1a6,0x1a7", 2170 "MSRValue": "0x7f50", 2171 "SampleAfterValue": "100000", 2172 "UMask": "0x1" 2173 }, 2174 { 2175 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_LOCATION", 2176 "Counter": "0,1,2,3", 2177 "EventCode": "0xB7, 0xBB", 2178 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", 2179 "MSRIndex": "0x1a6,0x1a7", 2180 "MSRValue": "0xff50", 2181 "SampleAfterValue": "100000", 2182 "UMask": "0x1" 2183 }, 2184 { 2185 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = IO_CSR_MMIO", 2186 "Counter": "0,1,2,3", 2187 "EventCode": "0xB7, 0xBB", 2188 "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", 2189 "MSRIndex": "0x1a6,0x1a7", 2190 "MSRValue": "0x8050", 2191 "SampleAfterValue": "100000", 2192 "UMask": "0x1" 2193 }, 2194 { 2195 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE", 2196 "Counter": "0,1,2,3", 2197 "EventCode": "0xB7, 0xBB", 2198 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", 2199 "MSRIndex": "0x1a6,0x1a7", 2200 "MSRValue": "0x150", 2201 "SampleAfterValue": "100000", 2202 "UMask": "0x1" 2203 }, 2204 { 2205 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 2206 "Counter": "0,1,2,3", 2207 "EventCode": "0xB7, 0xBB", 2208 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", 2209 "MSRIndex": "0x1a6,0x1a7", 2210 "MSRValue": "0x250", 2211 "SampleAfterValue": "100000", 2212 "UMask": "0x1" 2213 }, 2214 { 2215 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 2216 "Counter": "0,1,2,3", 2217 "EventCode": "0xB7, 0xBB", 2218 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", 2219 "MSRIndex": "0x1a6,0x1a7", 2220 "MSRValue": "0x450", 2221 "SampleAfterValue": "100000", 2222 "UMask": "0x1" 2223 }, 2224 { 2225 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LOCAL_CACHE", 2226 "Counter": "0,1,2,3", 2227 "EventCode": "0xB7, 0xBB", 2228 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", 2229 "MSRIndex": "0x1a6,0x1a7", 2230 "MSRValue": "0x750", 2231 "SampleAfterValue": "100000", 2232 "UMask": "0x1" 2233 }, 2234 { 2235 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 2236 "Counter": "0,1,2,3", 2237 "EventCode": "0xB7, 0xBB", 2238 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2239 "MSRIndex": "0x1a6,0x1a7", 2240 "MSRValue": "0x1050", 2241 "SampleAfterValue": "100000", 2242 "UMask": "0x1" 2243 }, 2244 { 2245 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = REMOTE_CACHE_HITM", 2246 "Counter": "0,1,2,3", 2247 "EventCode": "0xB7, 0xBB", 2248 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", 2249 "MSRIndex": "0x1a6,0x1a7", 2250 "MSRValue": "0x850", 2251 "SampleAfterValue": "100000", 2252 "UMask": "0x1" 2253 }, 2254 { 2255 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 2256 "Counter": "0,1,2,3", 2257 "EventCode": "0xB7, 0xBB", 2258 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2259 "MSRIndex": "0x1a6,0x1a7", 2260 "MSRValue": "0x5010", 2261 "SampleAfterValue": "100000", 2262 "UMask": "0x1" 2263 }, 2264 { 2265 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_CACHE_DRAM", 2266 "Counter": "0,1,2,3", 2267 "EventCode": "0xB7, 0xBB", 2268 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", 2269 "MSRIndex": "0x1a6,0x1a7", 2270 "MSRValue": "0x7f10", 2271 "SampleAfterValue": "100000", 2272 "UMask": "0x1" 2273 }, 2274 { 2275 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_LOCATION", 2276 "Counter": "0,1,2,3", 2277 "EventCode": "0xB7, 0xBB", 2278 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", 2279 "MSRIndex": "0x1a6,0x1a7", 2280 "MSRValue": "0xff10", 2281 "SampleAfterValue": "100000", 2282 "UMask": "0x1" 2283 }, 2284 { 2285 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = IO_CSR_MMIO", 2286 "Counter": "0,1,2,3", 2287 "EventCode": "0xB7, 0xBB", 2288 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", 2289 "MSRIndex": "0x1a6,0x1a7", 2290 "MSRValue": "0x8010", 2291 "SampleAfterValue": "100000", 2292 "UMask": "0x1" 2293 }, 2294 { 2295 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE", 2296 "Counter": "0,1,2,3", 2297 "EventCode": "0xB7, 0xBB", 2298 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", 2299 "MSRIndex": "0x1a6,0x1a7", 2300 "MSRValue": "0x110", 2301 "SampleAfterValue": "100000", 2302 "UMask": "0x1" 2303 }, 2304 { 2305 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 2306 "Counter": "0,1,2,3", 2307 "EventCode": "0xB7, 0xBB", 2308 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 2309 "MSRIndex": "0x1a6,0x1a7", 2310 "MSRValue": "0x210", 2311 "SampleAfterValue": "100000", 2312 "UMask": "0x1" 2313 }, 2314 { 2315 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 2316 "Counter": "0,1,2,3", 2317 "EventCode": "0xB7, 0xBB", 2318 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 2319 "MSRIndex": "0x1a6,0x1a7", 2320 "MSRValue": "0x410", 2321 "SampleAfterValue": "100000", 2322 "UMask": "0x1" 2323 }, 2324 { 2325 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_CACHE", 2326 "Counter": "0,1,2,3", 2327 "EventCode": "0xB7, 0xBB", 2328 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", 2329 "MSRIndex": "0x1a6,0x1a7", 2330 "MSRValue": "0x710", 2331 "SampleAfterValue": "100000", 2332 "UMask": "0x1" 2333 }, 2334 { 2335 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 2336 "Counter": "0,1,2,3", 2337 "EventCode": "0xB7, 0xBB", 2338 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2339 "MSRIndex": "0x1a6,0x1a7", 2340 "MSRValue": "0x1010", 2341 "SampleAfterValue": "100000", 2342 "UMask": "0x1" 2343 }, 2344 { 2345 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = REMOTE_CACHE_HITM", 2346 "Counter": "0,1,2,3", 2347 "EventCode": "0xB7, 0xBB", 2348 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", 2349 "MSRIndex": "0x1a6,0x1a7", 2350 "MSRValue": "0x810", 2351 "SampleAfterValue": "100000", 2352 "UMask": "0x1" 2353 }, 2354 { 2355 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 2356 "Counter": "0,1,2,3", 2357 "EventCode": "0xB7, 0xBB", 2358 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2359 "MSRIndex": "0x1a6,0x1a7", 2360 "MSRValue": "0x5040", 2361 "SampleAfterValue": "100000", 2362 "UMask": "0x1" 2363 }, 2364 { 2365 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_CACHE_DRAM", 2366 "Counter": "0,1,2,3", 2367 "EventCode": "0xB7, 0xBB", 2368 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", 2369 "MSRIndex": "0x1a6,0x1a7", 2370 "MSRValue": "0x7f40", 2371 "SampleAfterValue": "100000", 2372 "UMask": "0x1" 2373 }, 2374 { 2375 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_LOCATION", 2376 "Counter": "0,1,2,3", 2377 "EventCode": "0xB7, 0xBB", 2378 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", 2379 "MSRIndex": "0x1a6,0x1a7", 2380 "MSRValue": "0xff40", 2381 "SampleAfterValue": "100000", 2382 "UMask": "0x1" 2383 }, 2384 { 2385 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = IO_CSR_MMIO", 2386 "Counter": "0,1,2,3", 2387 "EventCode": "0xB7, 0xBB", 2388 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", 2389 "MSRIndex": "0x1a6,0x1a7", 2390 "MSRValue": "0x8040", 2391 "SampleAfterValue": "100000", 2392 "UMask": "0x1" 2393 }, 2394 { 2395 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE", 2396 "Counter": "0,1,2,3", 2397 "EventCode": "0xB7, 0xBB", 2398 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", 2399 "MSRIndex": "0x1a6,0x1a7", 2400 "MSRValue": "0x140", 2401 "SampleAfterValue": "100000", 2402 "UMask": "0x1" 2403 }, 2404 { 2405 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 2406 "Counter": "0,1,2,3", 2407 "EventCode": "0xB7, 0xBB", 2408 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", 2409 "MSRIndex": "0x1a6,0x1a7", 2410 "MSRValue": "0x240", 2411 "SampleAfterValue": "100000", 2412 "UMask": "0x1" 2413 }, 2414 { 2415 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 2416 "Counter": "0,1,2,3", 2417 "EventCode": "0xB7, 0xBB", 2418 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", 2419 "MSRIndex": "0x1a6,0x1a7", 2420 "MSRValue": "0x440", 2421 "SampleAfterValue": "100000", 2422 "UMask": "0x1" 2423 }, 2424 { 2425 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_CACHE", 2426 "Counter": "0,1,2,3", 2427 "EventCode": "0xB7, 0xBB", 2428 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", 2429 "MSRIndex": "0x1a6,0x1a7", 2430 "MSRValue": "0x740", 2431 "SampleAfterValue": "100000", 2432 "UMask": "0x1" 2433 }, 2434 { 2435 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 2436 "Counter": "0,1,2,3", 2437 "EventCode": "0xB7, 0xBB", 2438 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2439 "MSRIndex": "0x1a6,0x1a7", 2440 "MSRValue": "0x1040", 2441 "SampleAfterValue": "100000", 2442 "UMask": "0x1" 2443 }, 2444 { 2445 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = REMOTE_CACHE_HITM", 2446 "Counter": "0,1,2,3", 2447 "EventCode": "0xB7, 0xBB", 2448 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", 2449 "MSRIndex": "0x1a6,0x1a7", 2450 "MSRValue": "0x840", 2451 "SampleAfterValue": "100000", 2452 "UMask": "0x1" 2453 }, 2454 { 2455 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 2456 "Counter": "0,1,2,3", 2457 "EventCode": "0xB7, 0xBB", 2458 "EventName": "OFFCORE_RESPONSE.PF_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2459 "MSRIndex": "0x1a6,0x1a7", 2460 "MSRValue": "0x5020", 2461 "SampleAfterValue": "100000", 2462 "UMask": "0x1" 2463 }, 2464 { 2465 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_CACHE_DRAM", 2466 "Counter": "0,1,2,3", 2467 "EventCode": "0xB7, 0xBB", 2468 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", 2469 "MSRIndex": "0x1a6,0x1a7", 2470 "MSRValue": "0x7f20", 2471 "SampleAfterValue": "100000", 2472 "UMask": "0x1" 2473 }, 2474 { 2475 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_LOCATION", 2476 "Counter": "0,1,2,3", 2477 "EventCode": "0xB7, 0xBB", 2478 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", 2479 "MSRIndex": "0x1a6,0x1a7", 2480 "MSRValue": "0xff20", 2481 "SampleAfterValue": "100000", 2482 "UMask": "0x1" 2483 }, 2484 { 2485 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = IO_CSR_MMIO", 2486 "Counter": "0,1,2,3", 2487 "EventCode": "0xB7, 0xBB", 2488 "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", 2489 "MSRIndex": "0x1a6,0x1a7", 2490 "MSRValue": "0x8020", 2491 "SampleAfterValue": "100000", 2492 "UMask": "0x1" 2493 }, 2494 { 2495 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", 2496 "Counter": "0,1,2,3", 2497 "EventCode": "0xB7, 0xBB", 2498 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", 2499 "MSRIndex": "0x1a6,0x1a7", 2500 "MSRValue": "0x120", 2501 "SampleAfterValue": "100000", 2502 "UMask": "0x1" 2503 }, 2504 { 2505 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 2506 "Counter": "0,1,2,3", 2507 "EventCode": "0xB7, 0xBB", 2508 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", 2509 "MSRIndex": "0x1a6,0x1a7", 2510 "MSRValue": "0x220", 2511 "SampleAfterValue": "100000", 2512 "UMask": "0x1" 2513 }, 2514 { 2515 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 2516 "Counter": "0,1,2,3", 2517 "EventCode": "0xB7, 0xBB", 2518 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", 2519 "MSRIndex": "0x1a6,0x1a7", 2520 "MSRValue": "0x420", 2521 "SampleAfterValue": "100000", 2522 "UMask": "0x1" 2523 }, 2524 { 2525 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_CACHE", 2526 "Counter": "0,1,2,3", 2527 "EventCode": "0xB7, 0xBB", 2528 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", 2529 "MSRIndex": "0x1a6,0x1a7", 2530 "MSRValue": "0x720", 2531 "SampleAfterValue": "100000", 2532 "UMask": "0x1" 2533 }, 2534 { 2535 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 2536 "Counter": "0,1,2,3", 2537 "EventCode": "0xB7, 0xBB", 2538 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2539 "MSRIndex": "0x1a6,0x1a7", 2540 "MSRValue": "0x1020", 2541 "SampleAfterValue": "100000", 2542 "UMask": "0x1" 2543 }, 2544 { 2545 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = REMOTE_CACHE_HITM", 2546 "Counter": "0,1,2,3", 2547 "EventCode": "0xB7, 0xBB", 2548 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", 2549 "MSRIndex": "0x1a6,0x1a7", 2550 "MSRValue": "0x820", 2551 "SampleAfterValue": "100000", 2552 "UMask": "0x1" 2553 }, 2554 { 2555 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", 2556 "Counter": "0,1,2,3", 2557 "EventCode": "0xB7, 0xBB", 2558 "EventName": "OFFCORE_RESPONSE.PREFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2559 "MSRIndex": "0x1a6,0x1a7", 2560 "MSRValue": "0x5070", 2561 "SampleAfterValue": "100000", 2562 "UMask": "0x1" 2563 }, 2564 { 2565 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_CACHE_DRAM", 2566 "Counter": "0,1,2,3", 2567 "EventCode": "0xB7, 0xBB", 2568 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", 2569 "MSRIndex": "0x1a6,0x1a7", 2570 "MSRValue": "0x7f70", 2571 "SampleAfterValue": "100000", 2572 "UMask": "0x1" 2573 }, 2574 { 2575 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_LOCATION", 2576 "Counter": "0,1,2,3", 2577 "EventCode": "0xB7, 0xBB", 2578 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", 2579 "MSRIndex": "0x1a6,0x1a7", 2580 "MSRValue": "0xff70", 2581 "SampleAfterValue": "100000", 2582 "UMask": "0x1" 2583 }, 2584 { 2585 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = IO_CSR_MMIO", 2586 "Counter": "0,1,2,3", 2587 "EventCode": "0xB7, 0xBB", 2588 "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", 2589 "MSRIndex": "0x1a6,0x1a7", 2590 "MSRValue": "0x8070", 2591 "SampleAfterValue": "100000", 2592 "UMask": "0x1" 2593 }, 2594 { 2595 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", 2596 "Counter": "0,1,2,3", 2597 "EventCode": "0xB7, 0xBB", 2598 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", 2599 "MSRIndex": "0x1a6,0x1a7", 2600 "MSRValue": "0x170", 2601 "SampleAfterValue": "100000", 2602 "UMask": "0x1" 2603 }, 2604 { 2605 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", 2606 "Counter": "0,1,2,3", 2607 "EventCode": "0xB7, 0xBB", 2608 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", 2609 "MSRIndex": "0x1a6,0x1a7", 2610 "MSRValue": "0x270", 2611 "SampleAfterValue": "100000", 2612 "UMask": "0x1" 2613 }, 2614 { 2615 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", 2616 "Counter": "0,1,2,3", 2617 "EventCode": "0xB7, 0xBB", 2618 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", 2619 "MSRIndex": "0x1a6,0x1a7", 2620 "MSRValue": "0x470", 2621 "SampleAfterValue": "100000", 2622 "UMask": "0x1" 2623 }, 2624 { 2625 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_CACHE", 2626 "Counter": "0,1,2,3", 2627 "EventCode": "0xB7, 0xBB", 2628 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", 2629 "MSRIndex": "0x1a6,0x1a7", 2630 "MSRValue": "0x770", 2631 "SampleAfterValue": "100000", 2632 "UMask": "0x1" 2633 }, 2634 { 2635 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", 2636 "Counter": "0,1,2,3", 2637 "EventCode": "0xB7, 0xBB", 2638 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", 2639 "MSRIndex": "0x1a6,0x1a7", 2640 "MSRValue": "0x1070", 2641 "SampleAfterValue": "100000", 2642 "UMask": "0x1" 2643 }, 2644 { 2645 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = REMOTE_CACHE_HITM", 2646 "Counter": "0,1,2,3", 2647 "EventCode": "0xB7, 0xBB", 2648 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", 2649 "MSRIndex": "0x1a6,0x1a7", 2650 "MSRValue": "0x870", 2651 "SampleAfterValue": "100000", 2652 "UMask": "0x1" 2653 }, 2654 { 2655 "BriefDescription": "Super Queue LRU hints sent to LLC", 2656 "Counter": "0,1,2,3", 2657 "EventCode": "0xF4", 2658 "EventName": "SQ_MISC.LRU_HINTS", 2659 "SampleAfterValue": "2000000", 2660 "UMask": "0x4" 2661 }, 2662 { 2663 "BriefDescription": "Super Queue lock splits across a cache line", 2664 "Counter": "0,1,2,3", 2665 "EventCode": "0xF4", 2666 "EventName": "SQ_MISC.SPLIT_LOCK", 2667 "SampleAfterValue": "2000000", 2668 "UMask": "0x10" 2669 }, 2670 { 2671 "BriefDescription": "Loads delayed with at-Retirement block code", 2672 "Counter": "0,1,2,3", 2673 "EventCode": "0x6", 2674 "EventName": "STORE_BLOCKS.AT_RET", 2675 "SampleAfterValue": "200000", 2676 "UMask": "0x4" 2677 }, 2678 { 2679 "BriefDescription": "Cacheable loads delayed with L1D block code", 2680 "Counter": "0,1,2,3", 2681 "EventCode": "0x6", 2682 "EventName": "STORE_BLOCKS.L1D_BLOCK", 2683 "SampleAfterValue": "200000", 2684 "UMask": "0x8" 2685 } 2686]
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