memory.json

  1[
  2    {
  3        "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
  4        "Counter": "0,1,2,3",
  5        "CounterMask": "6",
  6        "EventCode": "0xa3",
  7        "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
  8        "SampleAfterValue": "1000003",
  9        "UMask": "0x6"
 10    },
 11    {
 12        "BriefDescription": "Number of machine clears due to memory ordering conflicts.",
 13        "Counter": "0,1,2,3,4,5,6,7",
 14        "EventCode": "0xc3",
 15        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
 16        "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
 17        "SampleAfterValue": "100003",
 18        "UMask": "0x2"
 19    },
 20    {
 21        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
 22        "Counter": "0,1,2,3,4,5,6,7",
 23        "Data_LA": "1",
 24        "EventCode": "0xcd",
 25        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
 26        "MSRIndex": "0x3F6",
 27        "MSRValue": "0x80",
 28        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency.",
 29        "SampleAfterValue": "1009",
 30        "UMask": "0x1"
 31    },
 32    {
 33        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
 34        "Counter": "0,1,2,3,4,5,6,7",
 35        "Data_LA": "1",
 36        "EventCode": "0xcd",
 37        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
 38        "MSRIndex": "0x3F6",
 39        "MSRValue": "0x10",
 40        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency.",
 41        "SampleAfterValue": "20011",
 42        "UMask": "0x1"
 43    },
 44    {
 45        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
 46        "Counter": "0,1,2,3,4,5,6,7",
 47        "Data_LA": "1",
 48        "EventCode": "0xcd",
 49        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
 50        "MSRIndex": "0x3F6",
 51        "MSRValue": "0x100",
 52        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency.",
 53        "SampleAfterValue": "503",
 54        "UMask": "0x1"
 55    },
 56    {
 57        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
 58        "Counter": "0,1,2,3,4,5,6,7",
 59        "Data_LA": "1",
 60        "EventCode": "0xcd",
 61        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
 62        "MSRIndex": "0x3F6",
 63        "MSRValue": "0x20",
 64        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency.",
 65        "SampleAfterValue": "100007",
 66        "UMask": "0x1"
 67    },
 68    {
 69        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
 70        "Counter": "0,1,2,3,4,5,6,7",
 71        "Data_LA": "1",
 72        "EventCode": "0xcd",
 73        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
 74        "MSRIndex": "0x3F6",
 75        "MSRValue": "0x4",
 76        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency.",
 77        "SampleAfterValue": "100003",
 78        "UMask": "0x1"
 79    },
 80    {
 81        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
 82        "Counter": "0,1,2,3,4,5,6,7",
 83        "Data_LA": "1",
 84        "EventCode": "0xcd",
 85        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
 86        "MSRIndex": "0x3F6",
 87        "MSRValue": "0x200",
 88        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency.",
 89        "SampleAfterValue": "101",
 90        "UMask": "0x1"
 91    },
 92    {
 93        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
 94        "Counter": "0,1,2,3,4,5,6,7",
 95        "Data_LA": "1",
 96        "EventCode": "0xcd",
 97        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
 98        "MSRIndex": "0x3F6",
 99        "MSRValue": "0x40",
100        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency.",
101        "SampleAfterValue": "2003",
102        "UMask": "0x1"
103    },
104    {
105        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
106        "Counter": "0,1,2,3,4,5,6,7",
107        "Data_LA": "1",
108        "EventCode": "0xcd",
109        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
110        "MSRIndex": "0x3F6",
111        "MSRValue": "0x8",
112        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency.",
113        "SampleAfterValue": "50021",
114        "UMask": "0x1"
115    },
116    {
117        "BriefDescription": "Demand Data Read requests who miss L3 cache",
118        "Counter": "0,1,2,3",
119        "EventCode": "0xb0",
120        "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
121        "PublicDescription": "Demand Data Read requests who miss L3 cache.",
122        "SampleAfterValue": "100003",
123        "UMask": "0x10"
124    },
125    {
126        "BriefDescription": "Number of times an RTM execution aborted.",
127        "Counter": "0,1,2,3,4,5,6,7",
128        "EventCode": "0xc9",
129        "EventName": "RTM_RETIRED.ABORTED",
130        "PublicDescription": "Counts the number of times RTM abort was triggered.",
131        "SampleAfterValue": "100003",
132        "UMask": "0x4"
133    },
134    {
135        "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 3 categories (e.g. interrupt)",
136        "Counter": "0,1,2,3,4,5,6,7",
137        "EventCode": "0xc9",
138        "EventName": "RTM_RETIRED.ABORTED_EVENTS",
139        "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 3 categories (e.g. interrupt).",
140        "SampleAfterValue": "100003",
141        "UMask": "0x80"
142    },
143    {
144        "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
145        "Counter": "0,1,2,3,4,5,6,7",
146        "EventCode": "0xc9",
147        "EventName": "RTM_RETIRED.ABORTED_MEM",
148        "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
149        "SampleAfterValue": "100003",
150        "UMask": "0x8"
151    },
152    {
153        "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
154        "Counter": "0,1,2,3,4,5,6,7",
155        "EventCode": "0xc9",
156        "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
157        "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.",
158        "SampleAfterValue": "100003",
159        "UMask": "0x40"
160    },
161    {
162        "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
163        "Counter": "0,1,2,3,4,5,6,7",
164        "EventCode": "0xc9",
165        "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
166        "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.",
167        "SampleAfterValue": "100003",
168        "UMask": "0x20"
169    },
170    {
171        "BriefDescription": "Number of times an RTM execution successfully committed",
172        "Counter": "0,1,2,3,4,5,6,7",
173        "EventCode": "0xc9",
174        "EventName": "RTM_RETIRED.COMMIT",
175        "PublicDescription": "Counts the number of times RTM commit succeeded.",
176        "SampleAfterValue": "100003",
177        "UMask": "0x2"
178    },
179    {
180        "BriefDescription": "Number of times an RTM execution started.",
181        "Counter": "0,1,2,3,4,5,6,7",
182        "EventCode": "0xc9",
183        "EventName": "RTM_RETIRED.START",
184        "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.",
185        "SampleAfterValue": "100003",
186        "UMask": "0x1"
187    },
188    {
189        "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region",
190        "Counter": "0,1,2,3,4,5,6,7",
191        "EventCode": "0x5d",
192        "EventName": "TX_EXEC.MISC2",
193        "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.",
194        "SampleAfterValue": "100003",
195        "UMask": "0x2"
196    },
197    {
198        "BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded",
199        "Counter": "0,1,2,3,4,5,6,7",
200        "EventCode": "0x5d",
201        "EventName": "TX_EXEC.MISC3",
202        "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.",
203        "SampleAfterValue": "100003",
204        "UMask": "0x4"
205    },
206    {
207        "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads",
208        "Counter": "0,1,2,3",
209        "EventCode": "0x54",
210        "EventName": "TX_MEM.ABORT_CAPACITY_READ",
211        "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads",
212        "SampleAfterValue": "100003",
213        "UMask": "0x80"
214    },
215    {
216        "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.",
217        "Counter": "0,1,2,3",
218        "EventCode": "0x54",
219        "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
220        "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.",
221        "SampleAfterValue": "100003",
222        "UMask": "0x2"
223    },
224    {
225        "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
226        "Counter": "0,1,2,3",
227        "EventCode": "0x54",
228        "EventName": "TX_MEM.ABORT_CONFLICT",
229        "PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
230        "SampleAfterValue": "100003",
231        "UMask": "0x1"
232    }
233]