other.json

 1[
 2    {
 3        "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
 4        "Counter": "0,1,2,3",
 5        "EventCode": "0x28",
 6        "EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
 7        "PublicDescription": "Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
 8        "SampleAfterValue": "200003",
 9        "UMask": "0x7"
10    },
11    {
12        "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
13        "Counter": "0,1,2,3",
14        "EventCode": "0x28",
15        "EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
16        "PublicDescription": "Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
17        "SampleAfterValue": "200003",
18        "UMask": "0x18"
19    },
20    {
21        "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
22        "Counter": "0,1,2,3",
23        "EventCode": "0x28",
24        "EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
25        "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchitecture).  This includes high current AVX 512-bit instructions.",
26        "SampleAfterValue": "200003",
27        "UMask": "0x20"
28    },
29    {
30        "BriefDescription": "Core cycles the core was throttled due to a pending power level request.",
31        "Counter": "0,1,2,3",
32        "EventCode": "0x28",
33        "EventName": "CORE_POWER.THROTTLE",
34        "PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power level request.",
35        "SampleAfterValue": "200003",
36        "UMask": "0x40"
37    },
38    {
39        "BriefDescription": "Number of hardware interrupts received by the processor.",
40        "Counter": "0,1,2,3",
41        "EventCode": "0xCB",
42        "EventName": "HW_INTERRUPTS.RECEIVED",
43        "PublicDescription": "Counts the number of hardware interruptions received by the processor.",
44        "SampleAfterValue": "203",
45        "UMask": "0x1"
46    },
47    {
48        "BriefDescription": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
49        "Counter": "0,1,2,3",
50        "EventCode": "0x09",
51        "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
52        "SampleAfterValue": "2000003",
53        "UMask": "0x1"
54    }
55]