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floating-point.json
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linux-6.19.14/tools/perf/pmu-events/arch/x86/pantherlake/floating-point.json
1[ 2 { 3 "BriefDescription": "Cycles when floating-point divide unit is busy executing divide or square root operations.", 4 "Counter": "0,1,2,3,4,5,6,7,8,9", 5 "CounterMask": "1", 6 "EventCode": "0xb0", 7 "EventName": "ARITH.FPDIV_ACTIVE", 8 "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for floating-point operations only.", 9 "SampleAfterValue": "1000003", 10 "UMask": "0x1", 11 "Unit": "cpu_core" 12 }, 13 { 14 "BriefDescription": "Counts all microcode FP assists.", 15 "Counter": "0,1,2,3,4,5,6,7,8,9", 16 "EventCode": "0xc1", 17 "EventName": "ASSISTS.FP", 18 "PublicDescription": "Counts all microcode Floating Point assists.", 19 "SampleAfterValue": "100003", 20 "UMask": "0x2", 21 "Unit": "cpu_core" 22 }, 23 { 24 "BriefDescription": "ASSISTS.SSE_AVX_MIX", 25 "Counter": "0,1,2,3,4,5,6,7,8,9", 26 "EventCode": "0xc1", 27 "EventName": "ASSISTS.SSE_AVX_MIX", 28 "SampleAfterValue": "1000003", 29 "UMask": "0x10", 30 "Unit": "cpu_core" 31 }, 32 { 33 "BriefDescription": "Number of FP-arith-uops dispatched on 1st VEC port (port 0). FP-arith-uops are of type ADD* / SUB* / MUL / FMA* / DPP.", 34 "Counter": "0,1,2,3,4,5,6,7,8,9", 35 "EventCode": "0xb3", 36 "EventName": "FP_ARITH_DISPATCHED.V0", 37 "SampleAfterValue": "2000003", 38 "UMask": "0x1", 39 "Unit": "cpu_core" 40 }, 41 { 42 "BriefDescription": "Number of FP-arith-uops dispatched on 2nd VEC port (port 1)", 43 "Counter": "0,1,2,3,4,5,6,7,8,9", 44 "EventCode": "0xb3", 45 "EventName": "FP_ARITH_DISPATCHED.V1", 46 "SampleAfterValue": "2000003", 47 "UMask": "0x2", 48 "Unit": "cpu_core" 49 }, 50 { 51 "BriefDescription": "Number of FP-arith-uops dispatched on 3rd VEC port (port 5)", 52 "Counter": "0,1,2,3,4,5,6,7,8,9", 53 "EventCode": "0xb3", 54 "EventName": "FP_ARITH_DISPATCHED.V2", 55 "SampleAfterValue": "2000003", 56 "UMask": "0x4", 57 "Unit": "cpu_core" 58 }, 59 { 60 "BriefDescription": "Number of FP-arith-uops dispatched on 4th VEC port", 61 "Counter": "0,1,2,3,4,5,6,7,8,9", 62 "EventCode": "0xb3", 63 "EventName": "FP_ARITH_DISPATCHED.V3", 64 "SampleAfterValue": "2000003", 65 "UMask": "0x8", 66 "Unit": "cpu_core" 67 }, 68 { 69 "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 70 "Counter": "0,1,2,3,4,5,6,7,8,9", 71 "EventCode": "0xc7", 72 "EventName": "FP_ARITH_OPS_RETIRED.128B_PACKED_DOUBLE", 73 "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 74 "SampleAfterValue": "100003", 75 "UMask": "0x4", 76 "Unit": "cpu_core" 77 }, 78 { 79 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 80 "Counter": "0,1,2,3,4,5,6,7,8,9", 81 "EventCode": "0xc7", 82 "EventName": "FP_ARITH_OPS_RETIRED.128B_PACKED_SINGLE", 83 "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 84 "SampleAfterValue": "100003", 85 "UMask": "0x8", 86 "Unit": "cpu_core" 87 }, 88 { 89 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 90 "Counter": "0,1,2,3,4,5,6,7,8,9", 91 "EventCode": "0xc7", 92 "EventName": "FP_ARITH_OPS_RETIRED.256B_PACKED_DOUBLE", 93 "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 94 "SampleAfterValue": "100003", 95 "UMask": "0x10", 96 "Unit": "cpu_core" 97 }, 98 { 99 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 100 "Counter": "0,1,2,3,4,5,6,7,8,9", 101 "EventCode": "0xc7", 102 "EventName": "FP_ARITH_OPS_RETIRED.256B_PACKED_SINGLE", 103 "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 104 "SampleAfterValue": "100003", 105 "UMask": "0x20", 106 "Unit": "cpu_core" 107 }, 108 { 109 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", 110 "Counter": "0,1,2,3,4,5,6,7,8,9", 111 "EventCode": "0xc7", 112 "EventName": "FP_ARITH_OPS_RETIRED.4_FLOPS", 113 "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 114 "SampleAfterValue": "100003", 115 "UMask": "0x18", 116 "Unit": "cpu_core" 117 }, 118 { 119 "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", 120 "Counter": "0,1,2,3,4,5,6,7,8,9", 121 "EventCode": "0xc7", 122 "EventName": "FP_ARITH_OPS_RETIRED.SCALAR", 123 "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 124 "SampleAfterValue": "1000003", 125 "UMask": "0x3", 126 "Unit": "cpu_core" 127 }, 128 { 129 "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 130 "Counter": "0,1,2,3,4,5,6,7,8,9", 131 "EventCode": "0xc7", 132 "EventName": "FP_ARITH_OPS_RETIRED.SCALAR_DOUBLE", 133 "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 134 "SampleAfterValue": "100003", 135 "UMask": "0x1", 136 "Unit": "cpu_core" 137 }, 138 { 139 "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 140 "Counter": "0,1,2,3,4,5,6,7,8,9", 141 "EventCode": "0xc7", 142 "EventName": "FP_ARITH_OPS_RETIRED.SCALAR_SINGLE", 143 "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 144 "SampleAfterValue": "100003", 145 "UMask": "0x2", 146 "Unit": "cpu_core" 147 }, 148 { 149 "BriefDescription": "Number of any Vector retired FP arithmetic instructions", 150 "Counter": "0,1,2,3,4,5,6,7,8,9", 151 "EventCode": "0xc7", 152 "EventName": "FP_ARITH_OPS_RETIRED.VECTOR", 153 "PublicDescription": "Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 154 "SampleAfterValue": "1000003", 155 "UMask": "0x3c", 156 "Unit": "cpu_core" 157 }, 158 { 159 "BriefDescription": "FP_ARITH_OPS_RETIRED.VECTOR_128B", 160 "Counter": "0,1,2,3,4,5,6,7,8,9", 161 "EventCode": "0xc7", 162 "EventName": "FP_ARITH_OPS_RETIRED.VECTOR_128B", 163 "SampleAfterValue": "100003", 164 "UMask": "0xc", 165 "Unit": "cpu_core" 166 }, 167 { 168 "BriefDescription": "FP_ARITH_OPS_RETIRED.VECTOR_256B", 169 "Counter": "0,1,2,3,4,5,6,7,8,9", 170 "EventCode": "0xc7", 171 "EventName": "FP_ARITH_OPS_RETIRED.VECTOR_256B", 172 "SampleAfterValue": "100003", 173 "UMask": "0x30", 174 "Unit": "cpu_core" 175 }, 176 { 177 "BriefDescription": "Counts the number of all types of floating point operations per uop with all default weighting", 178 "Counter": "0,1,2,3,4,5,6,7", 179 "EventCode": "0xc8", 180 "EventName": "FP_FLOPS_RETIRED.ALL", 181 "PublicDescription": "Counts the number of all types of floating point operations per uop with all default weighting Available PDIST counters: 0,1", 182 "SampleAfterValue": "1000003", 183 "UMask": "0x3", 184 "Unit": "cpu_atom" 185 }, 186 { 187 "BriefDescription": "Counts the number of floating point operations that produce 32 bit single precision results", 188 "Counter": "0,1,2,3,4,5,6,7", 189 "EventCode": "0xc8", 190 "EventName": "FP_FLOPS_RETIRED.FP32", 191 "PublicDescription": "Counts the number of floating point operations that produce 32 bit single precision results Available PDIST counters: 0,1", 192 "SampleAfterValue": "1000003", 193 "UMask": "0x2", 194 "Unit": "cpu_atom" 195 }, 196 { 197 "BriefDescription": "Counts the number of floating point operations that produce 64 bit double precision results", 198 "Counter": "0,1,2,3,4,5,6,7", 199 "EventCode": "0xc8", 200 "EventName": "FP_FLOPS_RETIRED.FP64", 201 "PublicDescription": "Counts the number of floating point operations that produce 64 bit double precision results Available PDIST counters: 0,1", 202 "SampleAfterValue": "1000003", 203 "UMask": "0x1", 204 "Unit": "cpu_atom" 205 }, 206 { 207 "BriefDescription": "Counts the number of retired instructions whose sources are a packed 128 bit double precision floating point. This may be SSE or AVX.128 operations.", 208 "Counter": "0,1,2,3,4,5,6,7", 209 "EventCode": "0xc7", 210 "EventName": "FP_INST_RETIRED.128B_DP", 211 "PublicDescription": "Counts the number of retired instructions whose sources are a packed 128 bit double precision floating point. This may be SSE or AVX.128 operations. Available PDIST counters: 0,1", 212 "SampleAfterValue": "1000003", 213 "UMask": "0x8", 214 "Unit": "cpu_atom" 215 }, 216 { 217 "BriefDescription": "Counts the number of retired instructions whose sources are a packed 128 bit single precision floating point. This may be SSE or AVX.128 operations.", 218 "Counter": "0,1,2,3,4,5,6,7", 219 "EventCode": "0xc7", 220 "EventName": "FP_INST_RETIRED.128B_SP", 221 "PublicDescription": "Counts the number of retired instructions whose sources are a packed 128 bit single precision floating point. This may be SSE or AVX.128 operations. Available PDIST counters: 0,1", 222 "SampleAfterValue": "1000003", 223 "UMask": "0x4", 224 "Unit": "cpu_atom" 225 }, 226 { 227 "BriefDescription": "Counts the number of retired instructions whose sources are a packed 256 bit double precision floating point.", 228 "Counter": "0,1,2,3,4,5,6,7", 229 "EventCode": "0xc7", 230 "EventName": "FP_INST_RETIRED.256B_DP", 231 "PublicDescription": "Counts the number of retired instructions whose sources are a packed 256 bit double precision floating point. Available PDIST counters: 0,1", 232 "SampleAfterValue": "1000003", 233 "UMask": "0x20", 234 "Unit": "cpu_atom" 235 }, 236 { 237 "BriefDescription": "Counts the number of retired instructions whose sources are a packed 256 bit single precision floating point.", 238 "Counter": "0,1,2,3,4,5,6,7", 239 "EventCode": "0xc7", 240 "EventName": "FP_INST_RETIRED.256B_SP", 241 "PublicDescription": "Counts the number of retired instructions whose sources are a packed 256 bit single precision floating point. Available PDIST counters: 0,1", 242 "SampleAfterValue": "1000003", 243 "UMask": "0x10", 244 "Unit": "cpu_atom" 245 }, 246 { 247 "BriefDescription": "Counts the number of retired instructions whose sources are a scalar 32bit single precision floating point.", 248 "Counter": "0,1,2,3,4,5,6,7", 249 "EventCode": "0xc7", 250 "EventName": "FP_INST_RETIRED.32B_SP", 251 "PublicDescription": "Counts the number of retired instructions whose sources are a scalar 32bit single precision floating point. Available PDIST counters: 0,1", 252 "SampleAfterValue": "1000003", 253 "UMask": "0x1", 254 "Unit": "cpu_atom" 255 }, 256 { 257 "BriefDescription": "Counts the number of retired instructions whose sources are a scalar 64 bit double precision floating point.", 258 "Counter": "0,1,2,3,4,5,6,7", 259 "EventCode": "0xc7", 260 "EventName": "FP_INST_RETIRED.64B_DP", 261 "PublicDescription": "Counts the number of retired instructions whose sources are a scalar 64 bit double precision floating point. Available PDIST counters: 0,1", 262 "SampleAfterValue": "1000003", 263 "UMask": "0x2", 264 "Unit": "cpu_atom" 265 }, 266 { 267 "BriefDescription": "Counts the total number of floating point retired instructions.", 268 "Counter": "0,1,2,3,4,5,6,7", 269 "EventCode": "0xc7", 270 "EventName": "FP_INST_RETIRED.ALL", 271 "PublicDescription": "Counts the total number of floating point retired instructions. Available PDIST counters: 0,1", 272 "SampleAfterValue": "1000003", 273 "UMask": "0x3f", 274 "Unit": "cpu_atom" 275 }, 276 { 277 "BriefDescription": "Counts the number of uops executed on all floating point ports.", 278 "Counter": "0,1,2,3,4,5,6,7", 279 "EventCode": "0xb2", 280 "EventName": "FP_VINT_UOPS_EXECUTED.ALL", 281 "SampleAfterValue": "1000003", 282 "UMask": "0x1f", 283 "Unit": "cpu_atom" 284 }, 285 { 286 "BriefDescription": "Counts the number of uops executed on floating point and vector integer port 0.", 287 "Counter": "0,1,2,3,4,5,6,7", 288 "EventCode": "0xb2", 289 "EventName": "FP_VINT_UOPS_EXECUTED.P0", 290 "SampleAfterValue": "1000003", 291 "UMask": "0x2", 292 "Unit": "cpu_atom" 293 }, 294 { 295 "BriefDescription": "Counts the number of uops executed on floating point and vector integer port 1.", 296 "Counter": "0,1,2,3,4,5,6,7", 297 "EventCode": "0xb2", 298 "EventName": "FP_VINT_UOPS_EXECUTED.P1", 299 "SampleAfterValue": "1000003", 300 "UMask": "0x4", 301 "Unit": "cpu_atom" 302 }, 303 { 304 "BriefDescription": "Counts the number of uops executed on floating point and vector integer port 2.", 305 "Counter": "0,1,2,3,4,5,6,7", 306 "EventCode": "0xb2", 307 "EventName": "FP_VINT_UOPS_EXECUTED.P2", 308 "SampleAfterValue": "1000003", 309 "UMask": "0x8", 310 "Unit": "cpu_atom" 311 }, 312 { 313 "BriefDescription": "Counts the number of uops executed on floating point and vector integer port 3.", 314 "Counter": "0,1,2,3,4,5,6,7", 315 "EventCode": "0xb2", 316 "EventName": "FP_VINT_UOPS_EXECUTED.P3", 317 "SampleAfterValue": "1000003", 318 "UMask": "0x10", 319 "Unit": "cpu_atom" 320 }, 321 { 322 "BriefDescription": "Counts the number of uops executed on floating point and vector integer port 0, 1, 2, 3.", 323 "Counter": "0,1,2,3,4,5,6,7", 324 "EventCode": "0xb2", 325 "EventName": "FP_VINT_UOPS_EXECUTED.PRIMARY", 326 "SampleAfterValue": "1000003", 327 "UMask": "0x1e", 328 "Unit": "cpu_atom" 329 }, 330 { 331 "BriefDescription": "Counts the number of uops executed on floating point and vector integer store data port.", 332 "Counter": "0,1,2,3,4,5,6,7", 333 "EventCode": "0xb2", 334 "EventName": "FP_VINT_UOPS_EXECUTED.STD", 335 "SampleAfterValue": "1000003", 336 "UMask": "0x1", 337 "Unit": "cpu_atom" 338 }, 339 { 340 "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.", 341 "Counter": "0,1,2,3,4,5,6,7", 342 "EventCode": "0xc3", 343 "EventName": "MACHINE_CLEARS.FP_ASSIST", 344 "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.", 345 "SampleAfterValue": "1000003", 346 "UMask": "0x4", 347 "Unit": "cpu_atom" 348 }, 349 { 350 "BriefDescription": "Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt).", 351 "Counter": "0,1,2,3,4,5,6,7", 352 "EventCode": "0xc2", 353 "EventName": "UOPS_RETIRED.FPDIV", 354 "PublicDescription": "Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt). Available PDIST counters: 0,1", 355 "SampleAfterValue": "1000003", 356 "UMask": "0x40", 357 "Unit": "cpu_atom" 358 } 359]
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