uncore-memory.json

  1[
  2    {
  3        "BriefDescription": "Counts every CAS read command sent from the Memory Controller 0 to DRAM (sum of all channels).",
  4        "Counter": "0",
  5        "EventCode": "0xff",
  6        "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN",
  7        "PerPkg": "1",
  8        "PublicDescription": "Counts every CAS read command sent from the Memory Controller 0 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data.",
  9        "UMask": "0x20",
 10        "Unit": "imc_free_running_0"
 11    },
 12    {
 13        "BriefDescription": "Counts every read and write request entering the Memory Controller 0.",
 14        "Counter": "2",
 15        "EventCode": "0xff",
 16        "EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN",
 17        "PerPkg": "1",
 18        "PublicDescription": "Counts every read and write request entering the Memory Controller 0 (sum of all channels). All requests are counted as one, whether they are 32B or 64B Read/Write or partial/full line writes. Some write requests to the same address may merge to a single write command to DRAM. Therefore, the total request count may be higher than total DRAM BW.",
 19        "UMask": "0x10",
 20        "Unit": "imc_free_running_0"
 21    },
 22    {
 23        "BriefDescription": "Counts every CAS write command sent from the Memory Controller 0 to DRAM (sum of all channels).",
 24        "Counter": "1",
 25        "EventCode": "0xff",
 26        "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN",
 27        "PerPkg": "1",
 28        "PublicDescription": "Counts every CAS write command sent from the Memory Controller 0 to DRAM (sum of all channels).  Each CAS commands can be for 32B or 64B of data.",
 29        "UMask": "0x30",
 30        "Unit": "imc_free_running_0"
 31    },
 32    {
 33        "BriefDescription": "Counts every CAS read command sent from the Memory Controller 1 to DRAM (sum of all channels).",
 34        "Counter": "3",
 35        "EventCode": "0xff",
 36        "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN",
 37        "PerPkg": "1",
 38        "PublicDescription": "Counts every CAS read command sent from the Memory Controller 1 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data.",
 39        "UMask": "0x20",
 40        "Unit": "imc_free_running_1"
 41    },
 42    {
 43        "BriefDescription": "Counts every read and write request entering the Memory Controller 1.",
 44        "Counter": "5",
 45        "EventCode": "0xff",
 46        "EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN",
 47        "PerPkg": "1",
 48        "PublicDescription": "Counts every read and write request entering the Memory Controller 1 (sum of all channels). All requests are counted as one, whether they are 32B or 64B Read/Write or partial/full line writes. Some write requests to the same address may merge to a single write command to DRAM. Therefore, the total request count may be higher than total DRAM BW.",
 49        "UMask": "0x10",
 50        "Unit": "imc_free_running_1"
 51    },
 52    {
 53        "BriefDescription": "Counts every CAS write command sent from the Memory Controller 1 to DRAM (sum of all channels).",
 54        "Counter": "4",
 55        "EventCode": "0xff",
 56        "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN",
 57        "PerPkg": "1",
 58        "PublicDescription": "Counts every CAS write command sent from the Memory Controller 1 to DRAM (sum of all channels).  Each CAS commands can be for 32B or 64B of data.",
 59        "UMask": "0x30",
 60        "Unit": "imc_free_running_1"
 61    },
 62    {
 63        "BriefDescription": "ACT command for a read request sent to DRAM",
 64        "Counter": "0,1,2,3,4",
 65        "EventCode": "0x24",
 66        "EventName": "UNC_M_ACT_COUNT_RD",
 67        "PerPkg": "1",
 68        "Unit": "iMC"
 69    },
 70    {
 71        "BriefDescription": "ACT command sent to DRAM",
 72        "Counter": "0,1,2,3,4",
 73        "EventCode": "0x26",
 74        "EventName": "UNC_M_ACT_COUNT_TOTAL",
 75        "PerPkg": "1",
 76        "Unit": "iMC"
 77    },
 78    {
 79        "BriefDescription": "ACT command for a write request sent to DRAM",
 80        "Counter": "0,1,2,3,4",
 81        "EventCode": "0x25",
 82        "EventName": "UNC_M_ACT_COUNT_WR",
 83        "PerPkg": "1",
 84        "Unit": "iMC"
 85    },
 86    {
 87        "BriefDescription": "Read CAS command sent to DRAM",
 88        "Counter": "0,1,2,3,4",
 89        "EventCode": "0x22",
 90        "EventName": "UNC_M_CAS_COUNT_RD",
 91        "PerPkg": "1",
 92        "Unit": "iMC"
 93    },
 94    {
 95        "BriefDescription": "Write CAS command sent to DRAM",
 96        "Counter": "0,1,2,3,4",
 97        "EventCode": "0x23",
 98        "EventName": "UNC_M_CAS_COUNT_WR",
 99        "PerPkg": "1",
100        "Unit": "iMC"
101    },
102    {
103        "BriefDescription": "Any Rank at Hot state",
104        "Counter": "0,1,2,3,4",
105        "EventCode": "0x19",
106        "EventName": "UNC_M_DRAM_THERMAL_HOT",
107        "Experimental": "1",
108        "PerPkg": "1",
109        "Unit": "iMC"
110    },
111    {
112        "BriefDescription": "Any Rank at Warm state",
113        "Counter": "0,1,2,3,4",
114        "EventCode": "0x1A",
115        "EventName": "UNC_M_DRAM_THERMAL_WARM",
116        "Experimental": "1",
117        "PerPkg": "1",
118        "Unit": "iMC"
119    },
120    {
121        "BriefDescription": "PRE command sent to DRAM due to page table idle timer expiration",
122        "Counter": "0,1,2,3,4",
123        "EventCode": "0x28",
124        "EventName": "UNC_M_PRE_COUNT_IDLE",
125        "PerPkg": "1",
126        "Unit": "iMC"
127    },
128    {
129        "BriefDescription": "PRE command sent to DRAM for a read/write request",
130        "Counter": "0,1,2,3,4",
131        "EventCode": "0x27",
132        "EventName": "UNC_M_PRE_COUNT_PAGE_MISS",
133        "PerPkg": "1",
134        "Unit": "iMC"
135    },
136    {
137        "BriefDescription": "Number of bytes read from DRAM, in 32B chunks. Counter increments by 1 after receiving 32B chunk data.",
138        "Counter": "0,1,2,3,4",
139        "EventCode": "0x3A",
140        "EventName": "UNC_M_RD_DATA",
141        "PerPkg": "1",
142        "Unit": "iMC"
143    },
144    {
145        "BriefDescription": "Total number of read and write byte transfers to/from DRAM, in 32B chunks. Counter increments by 1 after sending or receiving 32B chunk data.",
146        "Counter": "0,1,2,3,4",
147        "EventCode": "0x3C",
148        "EventName": "UNC_M_TOTAL_DATA",
149        "PerPkg": "1",
150        "Unit": "iMC"
151    },
152    {
153        "BriefDescription": "Number of bytes written to DRAM, in 32B chunks. Counter increments by 1 after sending 32B chunk data.",
154        "Counter": "0,1,2,3,4",
155        "EventCode": "0x3B",
156        "EventName": "UNC_M_WR_DATA",
157        "PerPkg": "1",
158        "Unit": "iMC"
159    }
160]