uncore-memory.json

 1[
 2    {
 3        "BriefDescription": "Read CAS command sent to DRAM",
 4        "Counter": "0,1,2,3,4",
 5        "EventCode": "0x22",
 6        "EventName": "UNC_M_CAS_COUNT_RD",
 7        "PerPkg": "1",
 8        "Unit": "iMC"
 9    },
10    {
11        "BriefDescription": "Write CAS command sent to DRAM",
12        "Counter": "0,1,2,3,4",
13        "EventCode": "0x23",
14        "EventName": "UNC_M_CAS_COUNT_WR",
15        "PerPkg": "1",
16        "Unit": "iMC"
17    },
18    {
19        "BriefDescription": "Any Rank at Hot state",
20        "Counter": "0,1,2,3,4",
21        "EventCode": "0x19",
22        "EventName": "UNC_M_DRAM_THERMAL_HOT",
23        "Experimental": "1",
24        "PerPkg": "1",
25        "Unit": "iMC"
26    },
27    {
28        "BriefDescription": "Any Rank at Warm state",
29        "Counter": "0,1,2,3,4",
30        "EventCode": "0x1A",
31        "EventName": "UNC_M_DRAM_THERMAL_WARM",
32        "Experimental": "1",
33        "PerPkg": "1",
34        "Unit": "iMC"
35    },
36    {
37        "BriefDescription": "Total number of read and write byte transfers to/from DRAM, in 32B chunk, per DDR channel. Counter increments by 1 after sending  or receiving 32B chunk data.",
38        "Counter": "0,1,2,3,4",
39        "EventCode": "0x3C",
40        "EventName": "UNC_M_TOTAL_DATA",
41        "PerPkg": "1",
42        "Unit": "iMC"
43    }
44]