memory.json

  1[
  2    {
  3        "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
  4        "Counter": "0,1,2,3",
  5        "EventCode": "0xC3",
  6        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
  7        "SampleAfterValue": "100003",
  8        "UMask": "0x2"
  9    },
 10    {
 11        "BriefDescription": "Loads with latency value being above 128",
 12        "Counter": "3",
 13        "EventCode": "0xCD",
 14        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
 15        "MSRIndex": "0x3F6",
 16        "MSRValue": "0x80",
 17        "PEBS": "2",
 18        "PublicDescription": "Loads with latency value being above 128.",
 19        "SampleAfterValue": "1009",
 20        "UMask": "0x1"
 21    },
 22    {
 23        "BriefDescription": "Loads with latency value being above 16",
 24        "Counter": "3",
 25        "EventCode": "0xCD",
 26        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
 27        "MSRIndex": "0x3F6",
 28        "MSRValue": "0x10",
 29        "PEBS": "2",
 30        "PublicDescription": "Loads with latency value being above 16.",
 31        "SampleAfterValue": "20011",
 32        "UMask": "0x1"
 33    },
 34    {
 35        "BriefDescription": "Loads with latency value being above 256",
 36        "Counter": "3",
 37        "EventCode": "0xCD",
 38        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
 39        "MSRIndex": "0x3F6",
 40        "MSRValue": "0x100",
 41        "PEBS": "2",
 42        "PublicDescription": "Loads with latency value being above 256.",
 43        "SampleAfterValue": "503",
 44        "UMask": "0x1"
 45    },
 46    {
 47        "BriefDescription": "Loads with latency value being above 32",
 48        "Counter": "3",
 49        "EventCode": "0xCD",
 50        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
 51        "MSRIndex": "0x3F6",
 52        "MSRValue": "0x20",
 53        "PEBS": "2",
 54        "PublicDescription": "Loads with latency value being above 32.",
 55        "SampleAfterValue": "100007",
 56        "UMask": "0x1"
 57    },
 58    {
 59        "BriefDescription": "Loads with latency value being above 4",
 60        "Counter": "3",
 61        "EventCode": "0xCD",
 62        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
 63        "MSRIndex": "0x3F6",
 64        "MSRValue": "0x4",
 65        "PEBS": "2",
 66        "PublicDescription": "Loads with latency value being above 4.",
 67        "SampleAfterValue": "100003",
 68        "UMask": "0x1"
 69    },
 70    {
 71        "BriefDescription": "Loads with latency value being above 512",
 72        "Counter": "3",
 73        "EventCode": "0xCD",
 74        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
 75        "MSRIndex": "0x3F6",
 76        "MSRValue": "0x200",
 77        "PEBS": "2",
 78        "PublicDescription": "Loads with latency value being above 512.",
 79        "SampleAfterValue": "101",
 80        "UMask": "0x1"
 81    },
 82    {
 83        "BriefDescription": "Loads with latency value being above 64",
 84        "Counter": "3",
 85        "EventCode": "0xCD",
 86        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
 87        "MSRIndex": "0x3F6",
 88        "MSRValue": "0x40",
 89        "PEBS": "2",
 90        "PublicDescription": "Loads with latency value being above 64.",
 91        "SampleAfterValue": "2003",
 92        "UMask": "0x1"
 93    },
 94    {
 95        "BriefDescription": "Loads with latency value being above 8",
 96        "Counter": "3",
 97        "EventCode": "0xCD",
 98        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
 99        "MSRIndex": "0x3F6",
100        "MSRValue": "0x8",
101        "PEBS": "2",
102        "PublicDescription": "Loads with latency value being above 8.",
103        "SampleAfterValue": "50021",
104        "UMask": "0x1"
105    },
106    {
107        "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only.",
108        "Counter": "3",
109        "EventCode": "0xCD",
110        "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",
111        "PEBS": "2",
112        "SampleAfterValue": "2000003",
113        "UMask": "0x2"
114    },
115    {
116        "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
117        "Counter": "0,1,2,3",
118        "EventCode": "0x05",
119        "EventName": "MISALIGN_MEM_REF.LOADS",
120        "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.",
121        "SampleAfterValue": "2000003",
122        "UMask": "0x1"
123    },
124    {
125        "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
126        "Counter": "0,1,2,3",
127        "EventCode": "0x05",
128        "EventName": "MISALIGN_MEM_REF.STORES",
129        "PublicDescription": "Speculative cache-line split Store-address uops dispatched to L1D.",
130        "SampleAfterValue": "2000003",
131        "UMask": "0x2"
132    },
133    {
134        "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC  and the data returned from dram",
135        "Counter": "0,1,2,3",
136        "EventCode": "0xB7, 0xBB",
137        "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM",
138        "MSRIndex": "0x1a6,0x1a7",
139        "MSRValue": "0x300400244",
140        "SampleAfterValue": "100003",
141        "UMask": "0x1"
142    },
143    {
144        "BriefDescription": "Counts all demand & prefetch data reads that miss the LLC  and the data returned from dram",
145        "Counter": "0,1,2,3",
146        "EventCode": "0xB7, 0xBB",
147        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM",
148        "MSRIndex": "0x1a6,0x1a7",
149        "MSRValue": "0x300400091",
150        "SampleAfterValue": "100003",
151        "UMask": "0x1"
152    },
153    {
154        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from dram",
155        "Counter": "0,1,2,3",
156        "EventCode": "0xB7, 0xBB",
157        "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM",
158        "MSRIndex": "0x1a6,0x1a7",
159        "MSRValue": "0x3004003f7",
160        "SampleAfterValue": "100003",
161        "UMask": "0x1"
162    },
163    {
164        "BriefDescription": "Counts LLC replacements",
165        "Counter": "0,1,2,3",
166        "EventCode": "0xB7, 0xBB",
167        "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM",
168        "MSRIndex": "0x1a6,0x1a7",
169        "MSRValue": "0x6004001b3",
170        "SampleAfterValue": "100003",
171        "UMask": "0x1"
172    },
173    {
174        "BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram",
175        "Counter": "0,1,2,3",
176        "EventCode": "0xB7, 0xBB",
177        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM",
178        "MSRIndex": "0x1a6,0x1a7",
179        "MSRValue": "0x300400004",
180        "SampleAfterValue": "100003",
181        "UMask": "0x1"
182    },
183    {
184        "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram",
185        "Counter": "0,1,2,3",
186        "EventCode": "0xB7, 0xBB",
187        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM",
188        "MSRIndex": "0x1a6,0x1a7",
189        "MSRValue": "0x300400001",
190        "SampleAfterValue": "100003",
191        "UMask": "0x1"
192    },
193    {
194        "BriefDescription": "Number of any page walk that had a miss in LLC.",
195        "Counter": "0,1,2,3",
196        "EventCode": "0xBE",
197        "EventName": "PAGE_WALKS.LLC_MISS",
198        "SampleAfterValue": "100003",
199        "UMask": "0x1"
200    }
201]