FILE
uncore-io.json
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linux-6.19.14/tools/perf/pmu-events/arch/x86/grandridge/uncore-io.json
1[ 2 { 3 "BriefDescription": "IIO Clockticks", 4 "Counter": "0,1,2,3", 5 "EventCode": "0x01", 6 "EventName": "UNC_IIO_CLOCKTICKS", 7 "PerPkg": "1", 8 "PortMask": "0x000", 9 "Unit": "IIO" 10 }, 11 { 12 "BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.", 13 "Counter": "0,1,2,3", 14 "EventCode": "0xC2", 15 "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", 16 "Experimental": "1", 17 "FCMask": "0x07", 18 "PerPkg": "1", 19 "PortMask": "0x0FF", 20 "UMask": "0x4", 21 "Unit": "IIO" 22 }, 23 { 24 "BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.", 25 "Counter": "0,1,2,3", 26 "EventCode": "0xC2", 27 "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", 28 "Experimental": "1", 29 "FCMask": "0x07", 30 "PerPkg": "1", 31 "PortMask": "0x001", 32 "UMask": "0x4", 33 "Unit": "IIO" 34 }, 35 { 36 "BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.", 37 "Counter": "0,1,2,3", 38 "EventCode": "0xC2", 39 "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", 40 "Experimental": "1", 41 "FCMask": "0x07", 42 "PerPkg": "1", 43 "PortMask": "0x002", 44 "UMask": "0x4", 45 "Unit": "IIO" 46 }, 47 { 48 "BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.", 49 "Counter": "0,1,2,3", 50 "EventCode": "0xC2", 51 "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", 52 "Experimental": "1", 53 "FCMask": "0x07", 54 "PerPkg": "1", 55 "PortMask": "0x004", 56 "UMask": "0x4", 57 "Unit": "IIO" 58 }, 59 { 60 "BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.", 61 "Counter": "0,1,2,3", 62 "EventCode": "0xC2", 63 "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", 64 "Experimental": "1", 65 "FCMask": "0x07", 66 "PerPkg": "1", 67 "PortMask": "0x008", 68 "UMask": "0x4", 69 "Unit": "IIO" 70 }, 71 { 72 "BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.", 73 "Counter": "0,1,2,3", 74 "EventCode": "0xC2", 75 "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4", 76 "Experimental": "1", 77 "FCMask": "0x07", 78 "PerPkg": "1", 79 "PortMask": "0x010", 80 "UMask": "0x4", 81 "Unit": "IIO" 82 }, 83 { 84 "BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.", 85 "Counter": "0,1,2,3", 86 "EventCode": "0xC2", 87 "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5", 88 "Experimental": "1", 89 "FCMask": "0x07", 90 "PerPkg": "1", 91 "PortMask": "0x020", 92 "UMask": "0x4", 93 "Unit": "IIO" 94 }, 95 { 96 "BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.", 97 "Counter": "0,1,2,3", 98 "EventCode": "0xC2", 99 "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6", 100 "Experimental": "1", 101 "FCMask": "0x07", 102 "PerPkg": "1", 103 "PortMask": "0x040", 104 "UMask": "0x4", 105 "Unit": "IIO" 106 }, 107 { 108 "BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.", 109 "Counter": "0,1,2,3", 110 "EventCode": "0xC2", 111 "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7", 112 "Experimental": "1", 113 "FCMask": "0x07", 114 "PerPkg": "1", 115 "PortMask": "0x080", 116 "UMask": "0x4", 117 "Unit": "IIO" 118 }, 119 { 120 "BriefDescription": "Count of allocations in the completion buffer", 121 "Counter": "2,3", 122 "EventCode": "0xD5", 123 "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", 124 "Experimental": "1", 125 "FCMask": "0x07", 126 "PerPkg": "1", 127 "PortMask": "0x0FF", 128 "UMask": "0xff", 129 "Unit": "IIO" 130 }, 131 { 132 "BriefDescription": "Count of allocations in the completion buffer", 133 "Counter": "2,3", 134 "EventCode": "0xD5", 135 "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", 136 "Experimental": "1", 137 "FCMask": "0x07", 138 "PerPkg": "1", 139 "PortMask": "0x001", 140 "UMask": "0x1", 141 "Unit": "IIO" 142 }, 143 { 144 "BriefDescription": "Count of allocations in the completion buffer", 145 "Counter": "2,3", 146 "EventCode": "0xD5", 147 "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", 148 "Experimental": "1", 149 "FCMask": "0x07", 150 "PerPkg": "1", 151 "PortMask": "0x002", 152 "UMask": "0x2", 153 "Unit": "IIO" 154 }, 155 { 156 "BriefDescription": "Count of allocations in the completion buffer", 157 "Counter": "2,3", 158 "EventCode": "0xD5", 159 "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", 160 "Experimental": "1", 161 "FCMask": "0x07", 162 "PerPkg": "1", 163 "PortMask": "0x004", 164 "UMask": "0x4", 165 "Unit": "IIO" 166 }, 167 { 168 "BriefDescription": "Count of allocations in the completion buffer", 169 "Counter": "2,3", 170 "EventCode": "0xD5", 171 "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", 172 "Experimental": "1", 173 "FCMask": "0x07", 174 "PerPkg": "1", 175 "PortMask": "0x008", 176 "UMask": "0x8", 177 "Unit": "IIO" 178 }, 179 { 180 "BriefDescription": "Count of allocations in the completion buffer", 181 "Counter": "2,3", 182 "EventCode": "0xD5", 183 "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4", 184 "Experimental": "1", 185 "FCMask": "0x07", 186 "PerPkg": "1", 187 "PortMask": "0x010", 188 "UMask": "0x10", 189 "Unit": "IIO" 190 }, 191 { 192 "BriefDescription": "Count of allocations in the completion buffer", 193 "Counter": "2,3", 194 "EventCode": "0xD5", 195 "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5", 196 "Experimental": "1", 197 "FCMask": "0x07", 198 "PerPkg": "1", 199 "PortMask": "0x020", 200 "UMask": "0x20", 201 "Unit": "IIO" 202 }, 203 { 204 "BriefDescription": "Count of allocations in the completion buffer", 205 "Counter": "2,3", 206 "EventCode": "0xD5", 207 "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6", 208 "Experimental": "1", 209 "FCMask": "0x07", 210 "PerPkg": "1", 211 "PortMask": "0x040", 212 "UMask": "0x40", 213 "Unit": "IIO" 214 }, 215 { 216 "BriefDescription": "Count of allocations in the completion buffer", 217 "Counter": "2,3", 218 "EventCode": "0xD5", 219 "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7", 220 "Experimental": "1", 221 "FCMask": "0x07", 222 "PerPkg": "1", 223 "PortMask": "0x080", 224 "UMask": "0x80", 225 "Unit": "IIO" 226 }, 227 { 228 "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", 229 "Counter": "2,3", 230 "EventCode": "0xC0", 231 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.ALL_PARTS", 232 "FCMask": "0x07", 233 "PerPkg": "1", 234 "PortMask": "0x0FF", 235 "UMask": "0x4", 236 "Unit": "IIO" 237 }, 238 { 239 "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", 240 "Counter": "2,3", 241 "EventCode": "0xC0", 242 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", 243 "Experimental": "1", 244 "FCMask": "0x07", 245 "PerPkg": "1", 246 "PortMask": "0x001", 247 "UMask": "0x4", 248 "Unit": "IIO" 249 }, 250 { 251 "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", 252 "Counter": "2,3", 253 "EventCode": "0xC0", 254 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", 255 "Experimental": "1", 256 "FCMask": "0x07", 257 "PerPkg": "1", 258 "PortMask": "0x002", 259 "UMask": "0x4", 260 "Unit": "IIO" 261 }, 262 { 263 "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", 264 "Counter": "2,3", 265 "EventCode": "0xC0", 266 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", 267 "Experimental": "1", 268 "FCMask": "0x07", 269 "PerPkg": "1", 270 "PortMask": "0x004", 271 "UMask": "0x4", 272 "Unit": "IIO" 273 }, 274 { 275 "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", 276 "Counter": "2,3", 277 "EventCode": "0xC0", 278 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", 279 "Experimental": "1", 280 "FCMask": "0x07", 281 "PerPkg": "1", 282 "PortMask": "0x008", 283 "UMask": "0x4", 284 "Unit": "IIO" 285 }, 286 { 287 "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", 288 "Counter": "2,3", 289 "EventCode": "0xC0", 290 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4", 291 "Experimental": "1", 292 "FCMask": "0x07", 293 "PerPkg": "1", 294 "PortMask": "0x010", 295 "UMask": "0x4", 296 "Unit": "IIO" 297 }, 298 { 299 "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", 300 "Counter": "2,3", 301 "EventCode": "0xC0", 302 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5", 303 "Experimental": "1", 304 "FCMask": "0x07", 305 "PerPkg": "1", 306 "PortMask": "0x020", 307 "UMask": "0x4", 308 "Unit": "IIO" 309 }, 310 { 311 "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", 312 "Counter": "2,3", 313 "EventCode": "0xC0", 314 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6", 315 "Experimental": "1", 316 "FCMask": "0x07", 317 "PerPkg": "1", 318 "PortMask": "0x040", 319 "UMask": "0x4", 320 "Unit": "IIO" 321 }, 322 { 323 "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", 324 "Counter": "2,3", 325 "EventCode": "0xC0", 326 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7", 327 "Experimental": "1", 328 "FCMask": "0x07", 329 "PerPkg": "1", 330 "PortMask": "0x080", 331 "UMask": "0x4", 332 "Unit": "IIO" 333 }, 334 { 335 "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", 336 "Counter": "2,3", 337 "EventCode": "0xC0", 338 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.ALL_PARTS", 339 "FCMask": "0x07", 340 "PerPkg": "1", 341 "PortMask": "0x0FF", 342 "UMask": "0x1", 343 "Unit": "IIO" 344 }, 345 { 346 "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", 347 "Counter": "2,3", 348 "EventCode": "0xC0", 349 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", 350 "FCMask": "0x07", 351 "PerPkg": "1", 352 "PortMask": "0x001", 353 "UMask": "0x1", 354 "Unit": "IIO" 355 }, 356 { 357 "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", 358 "Counter": "2,3", 359 "EventCode": "0xC0", 360 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", 361 "FCMask": "0x07", 362 "PerPkg": "1", 363 "PortMask": "0x002", 364 "UMask": "0x1", 365 "Unit": "IIO" 366 }, 367 { 368 "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", 369 "Counter": "2,3", 370 "EventCode": "0xC0", 371 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", 372 "FCMask": "0x07", 373 "PerPkg": "1", 374 "PortMask": "0x004", 375 "UMask": "0x1", 376 "Unit": "IIO" 377 }, 378 { 379 "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", 380 "Counter": "2,3", 381 "EventCode": "0xC0", 382 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", 383 "FCMask": "0x07", 384 "PerPkg": "1", 385 "PortMask": "0x008", 386 "UMask": "0x1", 387 "Unit": "IIO" 388 }, 389 { 390 "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", 391 "Counter": "2,3", 392 "EventCode": "0xC0", 393 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4", 394 "FCMask": "0x07", 395 "PerPkg": "1", 396 "PortMask": "0x010", 397 "UMask": "0x1", 398 "Unit": "IIO" 399 }, 400 { 401 "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", 402 "Counter": "2,3", 403 "EventCode": "0xC0", 404 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5", 405 "FCMask": "0x07", 406 "PerPkg": "1", 407 "PortMask": "0x020", 408 "UMask": "0x1", 409 "Unit": "IIO" 410 }, 411 { 412 "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", 413 "Counter": "2,3", 414 "EventCode": "0xC0", 415 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6", 416 "FCMask": "0x07", 417 "PerPkg": "1", 418 "PortMask": "0x040", 419 "UMask": "0x1", 420 "Unit": "IIO" 421 }, 422 { 423 "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", 424 "Counter": "2,3", 425 "EventCode": "0xC0", 426 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7", 427 "FCMask": "0x07", 428 "PerPkg": "1", 429 "PortMask": "0x080", 430 "UMask": "0x1", 431 "Unit": "IIO" 432 }, 433 { 434 "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", 435 "Counter": "0,1", 436 "EventCode": "0x83", 437 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", 438 "FCMask": "0x07", 439 "PerPkg": "1", 440 "PortMask": "0x001", 441 "UMask": "0x4", 442 "Unit": "IIO" 443 }, 444 { 445 "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", 446 "Counter": "0,1", 447 "EventCode": "0x83", 448 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", 449 "FCMask": "0x07", 450 "PerPkg": "1", 451 "PortMask": "0x02", 452 "UMask": "0x4", 453 "Unit": "IIO" 454 }, 455 { 456 "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", 457 "Counter": "0,1", 458 "EventCode": "0x83", 459 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", 460 "FCMask": "0x07", 461 "PerPkg": "1", 462 "PortMask": "0x04", 463 "UMask": "0x4", 464 "Unit": "IIO" 465 }, 466 { 467 "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", 468 "Counter": "0,1", 469 "EventCode": "0x83", 470 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", 471 "FCMask": "0x07", 472 "PerPkg": "1", 473 "PortMask": "0x08", 474 "UMask": "0x4", 475 "Unit": "IIO" 476 }, 477 { 478 "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", 479 "Counter": "0,1", 480 "EventCode": "0x83", 481 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", 482 "FCMask": "0x07", 483 "PerPkg": "1", 484 "PortMask": "0x10", 485 "UMask": "0x4", 486 "Unit": "IIO" 487 }, 488 { 489 "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", 490 "Counter": "0,1", 491 "EventCode": "0x83", 492 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", 493 "FCMask": "0x07", 494 "PerPkg": "1", 495 "PortMask": "0x20", 496 "UMask": "0x4", 497 "Unit": "IIO" 498 }, 499 { 500 "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", 501 "Counter": "0,1", 502 "EventCode": "0x83", 503 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", 504 "FCMask": "0x07", 505 "PerPkg": "1", 506 "PortMask": "0x40", 507 "UMask": "0x4", 508 "Unit": "IIO" 509 }, 510 { 511 "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", 512 "Counter": "0,1", 513 "EventCode": "0x83", 514 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", 515 "FCMask": "0x07", 516 "PerPkg": "1", 517 "PortMask": "0x80", 518 "UMask": "0x4", 519 "Unit": "IIO" 520 }, 521 { 522 "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", 523 "Counter": "0,1", 524 "EventCode": "0x83", 525 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", 526 "FCMask": "0x07", 527 "PerPkg": "1", 528 "PortMask": "0x001", 529 "UMask": "0x1", 530 "Unit": "IIO" 531 }, 532 { 533 "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", 534 "Counter": "0,1", 535 "EventCode": "0x83", 536 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", 537 "FCMask": "0x07", 538 "PerPkg": "1", 539 "PortMask": "0x02", 540 "UMask": "0x1", 541 "Unit": "IIO" 542 }, 543 { 544 "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", 545 "Counter": "0,1", 546 "EventCode": "0x83", 547 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", 548 "FCMask": "0x07", 549 "PerPkg": "1", 550 "PortMask": "0x04", 551 "UMask": "0x1", 552 "Unit": "IIO" 553 }, 554 { 555 "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", 556 "Counter": "0,1", 557 "EventCode": "0x83", 558 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", 559 "FCMask": "0x07", 560 "PerPkg": "1", 561 "PortMask": "0x08", 562 "UMask": "0x1", 563 "Unit": "IIO" 564 }, 565 { 566 "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", 567 "Counter": "0,1", 568 "EventCode": "0x83", 569 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", 570 "FCMask": "0x07", 571 "PerPkg": "1", 572 "PortMask": "0x10", 573 "UMask": "0x1", 574 "Unit": "IIO" 575 }, 576 { 577 "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", 578 "Counter": "0,1", 579 "EventCode": "0x83", 580 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", 581 "FCMask": "0x07", 582 "PerPkg": "1", 583 "PortMask": "0x20", 584 "UMask": "0x1", 585 "Unit": "IIO" 586 }, 587 { 588 "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", 589 "Counter": "0,1", 590 "EventCode": "0x83", 591 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", 592 "FCMask": "0x07", 593 "PerPkg": "1", 594 "PortMask": "0x40", 595 "UMask": "0x1", 596 "Unit": "IIO" 597 }, 598 { 599 "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", 600 "Counter": "0,1", 601 "EventCode": "0x83", 602 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", 603 "FCMask": "0x07", 604 "PerPkg": "1", 605 "PortMask": "0x80", 606 "UMask": "0x1", 607 "Unit": "IIO" 608 }, 609 { 610 "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", 611 "Counter": "0,1", 612 "EventCode": "0x83", 613 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", 614 "Experimental": "1", 615 "FCMask": "0x07", 616 "PerPkg": "1", 617 "PortMask": "0x001", 618 "UMask": "0x2", 619 "Unit": "IIO" 620 }, 621 { 622 "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", 623 "Counter": "0,1", 624 "EventCode": "0x83", 625 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", 626 "Experimental": "1", 627 "FCMask": "0x07", 628 "PerPkg": "1", 629 "PortMask": "0x002", 630 "UMask": "0x2", 631 "Unit": "IIO" 632 }, 633 { 634 "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", 635 "Counter": "0,1", 636 "EventCode": "0x83", 637 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", 638 "Experimental": "1", 639 "FCMask": "0x07", 640 "PerPkg": "1", 641 "PortMask": "0x004", 642 "UMask": "0x2", 643 "Unit": "IIO" 644 }, 645 { 646 "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", 647 "Counter": "0,1", 648 "EventCode": "0x83", 649 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", 650 "Experimental": "1", 651 "FCMask": "0x07", 652 "PerPkg": "1", 653 "PortMask": "0x008", 654 "UMask": "0x2", 655 "Unit": "IIO" 656 }, 657 { 658 "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", 659 "Counter": "0,1", 660 "EventCode": "0x83", 661 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4", 662 "Experimental": "1", 663 "FCMask": "0x07", 664 "PerPkg": "1", 665 "PortMask": "0x010", 666 "UMask": "0x2", 667 "Unit": "IIO" 668 }, 669 { 670 "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", 671 "Counter": "0,1", 672 "EventCode": "0x83", 673 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5", 674 "Experimental": "1", 675 "FCMask": "0x07", 676 "PerPkg": "1", 677 "PortMask": "0x020", 678 "UMask": "0x2", 679 "Unit": "IIO" 680 }, 681 { 682 "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", 683 "Counter": "0,1", 684 "EventCode": "0x83", 685 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6", 686 "Experimental": "1", 687 "FCMask": "0x07", 688 "PerPkg": "1", 689 "PortMask": "0x040", 690 "UMask": "0x2", 691 "Unit": "IIO" 692 }, 693 { 694 "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", 695 "Counter": "0,1", 696 "EventCode": "0x83", 697 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7", 698 "Experimental": "1", 699 "FCMask": "0x07", 700 "PerPkg": "1", 701 "PortMask": "0x080", 702 "UMask": "0x2", 703 "Unit": "IIO" 704 }, 705 { 706 "BriefDescription": "IOTLB Hits to a 1G Page", 707 "Counter": "0,1,2,3", 708 "EventCode": "0x40", 709 "EventName": "UNC_IIO_IOMMU0.1G_HITS", 710 "Experimental": "1", 711 "PerPkg": "1", 712 "PortMask": "0x000", 713 "UMask": "0x10", 714 "Unit": "IIO" 715 }, 716 { 717 "BriefDescription": "IOTLB Hits to a 2M Page", 718 "Counter": "0,1,2,3", 719 "EventCode": "0x40", 720 "EventName": "UNC_IIO_IOMMU0.2M_HITS", 721 "Experimental": "1", 722 "PerPkg": "1", 723 "PortMask": "0x000", 724 "UMask": "0x8", 725 "Unit": "IIO" 726 }, 727 { 728 "BriefDescription": "IOTLB Hits to a 4K Page", 729 "Counter": "0,1,2,3", 730 "EventCode": "0x40", 731 "EventName": "UNC_IIO_IOMMU0.4K_HITS", 732 "Experimental": "1", 733 "PerPkg": "1", 734 "PortMask": "0x000", 735 "UMask": "0x4", 736 "Unit": "IIO" 737 }, 738 { 739 "BriefDescription": "Context cache hits", 740 "Counter": "0,1,2,3", 741 "EventCode": "0x40", 742 "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS", 743 "Experimental": "1", 744 "PerPkg": "1", 745 "PortMask": "0x000", 746 "UMask": "0x80", 747 "Unit": "IIO" 748 }, 749 { 750 "BriefDescription": "Context cache lookups", 751 "Counter": "0,1,2,3", 752 "EventCode": "0x40", 753 "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS", 754 "Experimental": "1", 755 "PerPkg": "1", 756 "PortMask": "0x000", 757 "UMask": "0x40", 758 "Unit": "IIO" 759 }, 760 { 761 "BriefDescription": "IOTLB lookups first", 762 "Counter": "0,1,2,3", 763 "EventCode": "0x40", 764 "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS", 765 "Experimental": "1", 766 "PerPkg": "1", 767 "PortMask": "0x000", 768 "UMask": "0x1", 769 "Unit": "IIO" 770 }, 771 { 772 "BriefDescription": "IOTLB Fills (same as IOTLB miss)", 773 "Counter": "0,1,2,3", 774 "EventCode": "0x40", 775 "EventName": "UNC_IIO_IOMMU0.MISSES", 776 "Experimental": "1", 777 "PerPkg": "1", 778 "PortMask": "0x000", 779 "UMask": "0x20", 780 "Unit": "IIO" 781 }, 782 { 783 "BriefDescription": "IOMMU memory access (both low and high priority)", 784 "Counter": "0,1,2,3", 785 "EventCode": "0x41", 786 "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES", 787 "Experimental": "1", 788 "PerPkg": "1", 789 "PortMask": "0x000", 790 "UMask": "0xc0", 791 "Unit": "IIO" 792 }, 793 { 794 "BriefDescription": "Second Level Page Walk Cache Hit to a 1G page", 795 "Counter": "0,1,2,3", 796 "EventCode": "0x41", 797 "EventName": "UNC_IIO_IOMMU1.SLPWC_1G_HITS", 798 "Experimental": "1", 799 "PerPkg": "1", 800 "PortMask": "0x000", 801 "UMask": "0x4", 802 "Unit": "IIO" 803 }, 804 { 805 "BriefDescription": "Second Level Page Walk Cache Hit to a 256T page", 806 "Counter": "0,1,2,3", 807 "EventCode": "0x41", 808 "EventName": "UNC_IIO_IOMMU1.SLPWC_256T_HITS", 809 "Experimental": "1", 810 "PerPkg": "1", 811 "PortMask": "0x000", 812 "UMask": "0x10", 813 "Unit": "IIO" 814 }, 815 { 816 "BriefDescription": "Second Level Page Walk Cache Hit to a 512G page", 817 "Counter": "0,1,2,3", 818 "EventCode": "0x41", 819 "EventName": "UNC_IIO_IOMMU1.SLPWC_512G_HITS", 820 "Experimental": "1", 821 "PerPkg": "1", 822 "PortMask": "0x000", 823 "UMask": "0x8", 824 "Unit": "IIO" 825 }, 826 { 827 "BriefDescription": "-", 828 "Counter": "0,1,2,3", 829 "EventCode": "0x8e", 830 "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT", 831 "Experimental": "1", 832 "FCMask": "0x07", 833 "PerPkg": "1", 834 "PortMask": "0x0FF", 835 "UMask": "0x80", 836 "Unit": "IIO" 837 }, 838 { 839 "BriefDescription": "-", 840 "Counter": "0,1,2,3", 841 "EventCode": "0x8e", 842 "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P", 843 "Experimental": "1", 844 "FCMask": "0x07", 845 "PerPkg": "1", 846 "PortMask": "0x0FF", 847 "UMask": "0x40", 848 "Unit": "IIO" 849 }, 850 { 851 "BriefDescription": "-", 852 "Counter": "0,1,2,3", 853 "EventCode": "0x8e", 854 "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P", 855 "Experimental": "1", 856 "FCMask": "0x07", 857 "PerPkg": "1", 858 "PortMask": "0x0FF", 859 "UMask": "0x20", 860 "Unit": "IIO" 861 }, 862 { 863 "BriefDescription": "-", 864 "Counter": "0,1,2,3", 865 "EventCode": "0x8e", 866 "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST", 867 "Experimental": "1", 868 "FCMask": "0x07", 869 "PerPkg": "1", 870 "PortMask": "0x0FF", 871 "UMask": "0x2", 872 "Unit": "IIO" 873 }, 874 { 875 "BriefDescription": "-", 876 "Counter": "0,1,2,3", 877 "EventCode": "0x8e", 878 "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM", 879 "Experimental": "1", 880 "FCMask": "0x07", 881 "PerPkg": "1", 882 "PortMask": "0x0FF", 883 "UMask": "0x8", 884 "Unit": "IIO" 885 }, 886 { 887 "BriefDescription": "-", 888 "Counter": "0,1,2,3", 889 "EventCode": "0x8e", 890 "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB", 891 "Experimental": "1", 892 "FCMask": "0x07", 893 "PerPkg": "1", 894 "PortMask": "0x0FF", 895 "UMask": "0x1", 896 "Unit": "IIO" 897 }, 898 { 899 "BriefDescription": "-", 900 "Counter": "0,1,2,3", 901 "EventCode": "0x8e", 902 "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX", 903 "Experimental": "1", 904 "FCMask": "0x07", 905 "PerPkg": "1", 906 "PortMask": "0x0FF", 907 "UMask": "0x4", 908 "Unit": "IIO" 909 }, 910 { 911 "BriefDescription": "Posted requests sent by the integrated IO (IIO) controller to the Ubox, useful for counting message signaled interrupts (MSI).", 912 "Counter": "0,1,2,3", 913 "EventCode": "0x8e", 914 "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX_POSTED", 915 "FCMask": "0x01", 916 "PerPkg": "1", 917 "PortMask": "0x0FF", 918 "PublicDescription": "-", 919 "UMask": "0x4", 920 "Unit": "IIO" 921 }, 922 { 923 "BriefDescription": "All 9 bits of Page Walk Tracker Occupancy", 924 "Counter": "0,1,2,3", 925 "EventCode": "0x42", 926 "EventName": "UNC_IIO_PWT_OCCUPANCY", 927 "Experimental": "1", 928 "PerPkg": "1", 929 "PortMask": "0x000", 930 "Unit": "IIO" 931 }, 932 { 933 "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", 934 "Counter": "2,3", 935 "EventCode": "0xC1", 936 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", 937 "FCMask": "0x07", 938 "PerPkg": "1", 939 "PortMask": "0x001", 940 "UMask": "0x4", 941 "Unit": "IIO" 942 }, 943 { 944 "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", 945 "Counter": "2,3", 946 "EventCode": "0xC1", 947 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", 948 "FCMask": "0x07", 949 "PerPkg": "1", 950 "PortMask": "0x002", 951 "UMask": "0x4", 952 "Unit": "IIO" 953 }, 954 { 955 "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", 956 "Counter": "2,3", 957 "EventCode": "0xC1", 958 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", 959 "FCMask": "0x07", 960 "PerPkg": "1", 961 "PortMask": "0x004", 962 "UMask": "0x4", 963 "Unit": "IIO" 964 }, 965 { 966 "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", 967 "Counter": "2,3", 968 "EventCode": "0xC1", 969 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", 970 "FCMask": "0x07", 971 "PerPkg": "1", 972 "PortMask": "0x008", 973 "UMask": "0x4", 974 "Unit": "IIO" 975 }, 976 { 977 "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", 978 "Counter": "2,3", 979 "EventCode": "0xC1", 980 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4", 981 "FCMask": "0x07", 982 "PerPkg": "1", 983 "PortMask": "0x010", 984 "UMask": "0x4", 985 "Unit": "IIO" 986 }, 987 { 988 "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", 989 "Counter": "2,3", 990 "EventCode": "0xC1", 991 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5", 992 "FCMask": "0x07", 993 "PerPkg": "1", 994 "PortMask": "0x020", 995 "UMask": "0x4", 996 "Unit": "IIO" 997 }, 998 { 999 "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", 1000 "Counter": "2,3", 1001 "EventCode": "0xC1", 1002 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6", 1003 "FCMask": "0x07", 1004 "PerPkg": "1", 1005 "PortMask": "0x040", 1006 "UMask": "0x4", 1007 "Unit": "IIO" 1008 }, 1009 { 1010 "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", 1011 "Counter": "2,3", 1012 "EventCode": "0xC1", 1013 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7", 1014 "FCMask": "0x07", 1015 "PerPkg": "1", 1016 "PortMask": "0x080", 1017 "UMask": "0x4", 1018 "Unit": "IIO" 1019 }, 1020 { 1021 "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", 1022 "Counter": "2,3", 1023 "EventCode": "0xC1", 1024 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", 1025 "FCMask": "0x07", 1026 "PerPkg": "1", 1027 "PortMask": "0x001", 1028 "UMask": "0x1", 1029 "Unit": "IIO" 1030 }, 1031 { 1032 "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", 1033 "Counter": "2,3", 1034 "EventCode": "0xC1", 1035 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", 1036 "FCMask": "0x07", 1037 "PerPkg": "1", 1038 "PortMask": "0x002", 1039 "UMask": "0x1", 1040 "Unit": "IIO" 1041 }, 1042 { 1043 "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", 1044 "Counter": "2,3", 1045 "EventCode": "0xC1", 1046 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", 1047 "FCMask": "0x07", 1048 "PerPkg": "1", 1049 "PortMask": "0x004", 1050 "UMask": "0x1", 1051 "Unit": "IIO" 1052 }, 1053 { 1054 "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", 1055 "Counter": "2,3", 1056 "EventCode": "0xC1", 1057 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", 1058 "FCMask": "0x07", 1059 "PerPkg": "1", 1060 "PortMask": "0x008", 1061 "UMask": "0x1", 1062 "Unit": "IIO" 1063 }, 1064 { 1065 "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", 1066 "Counter": "2,3", 1067 "EventCode": "0xC1", 1068 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4", 1069 "FCMask": "0x07", 1070 "PerPkg": "1", 1071 "PortMask": "0x010", 1072 "UMask": "0x1", 1073 "Unit": "IIO" 1074 }, 1075 { 1076 "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", 1077 "Counter": "2,3", 1078 "EventCode": "0xC1", 1079 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5", 1080 "FCMask": "0x07", 1081 "PerPkg": "1", 1082 "PortMask": "0x020", 1083 "UMask": "0x1", 1084 "Unit": "IIO" 1085 }, 1086 { 1087 "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", 1088 "Counter": "2,3", 1089 "EventCode": "0xC1", 1090 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6", 1091 "FCMask": "0x07", 1092 "PerPkg": "1", 1093 "PortMask": "0x040", 1094 "UMask": "0x1", 1095 "Unit": "IIO" 1096 }, 1097 { 1098 "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", 1099 "Counter": "2,3", 1100 "EventCode": "0xC1", 1101 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7", 1102 "FCMask": "0x07", 1103 "PerPkg": "1", 1104 "PortMask": "0x080", 1105 "UMask": "0x1", 1106 "Unit": "IIO" 1107 }, 1108 { 1109 "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", 1110 "Counter": "0,1", 1111 "EventCode": "0x84", 1112 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", 1113 "FCMask": "0x07", 1114 "PerPkg": "1", 1115 "PortMask": "0x001", 1116 "UMask": "0x4", 1117 "Unit": "IIO" 1118 }, 1119 { 1120 "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", 1121 "Counter": "0,1", 1122 "EventCode": "0x84", 1123 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", 1124 "FCMask": "0x07", 1125 "PerPkg": "1", 1126 "PortMask": "0x002", 1127 "UMask": "0x4", 1128 "Unit": "IIO" 1129 }, 1130 { 1131 "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", 1132 "Counter": "0,1", 1133 "EventCode": "0x84", 1134 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", 1135 "FCMask": "0x07", 1136 "PerPkg": "1", 1137 "PortMask": "0x004", 1138 "UMask": "0x4", 1139 "Unit": "IIO" 1140 }, 1141 { 1142 "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", 1143 "Counter": "0,1", 1144 "EventCode": "0x84", 1145 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", 1146 "FCMask": "0x07", 1147 "PerPkg": "1", 1148 "PortMask": "0x008", 1149 "UMask": "0x4", 1150 "Unit": "IIO" 1151 }, 1152 { 1153 "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", 1154 "Counter": "0,1", 1155 "EventCode": "0x84", 1156 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4", 1157 "FCMask": "0x07", 1158 "PerPkg": "1", 1159 "PortMask": "0x010", 1160 "UMask": "0x4", 1161 "Unit": "IIO" 1162 }, 1163 { 1164 "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", 1165 "Counter": "0,1", 1166 "EventCode": "0x84", 1167 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5", 1168 "FCMask": "0x07", 1169 "PerPkg": "1", 1170 "PortMask": "0x020", 1171 "UMask": "0x4", 1172 "Unit": "IIO" 1173 }, 1174 { 1175 "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", 1176 "Counter": "0,1", 1177 "EventCode": "0x84", 1178 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6", 1179 "FCMask": "0x07", 1180 "PerPkg": "1", 1181 "PortMask": "0x040", 1182 "UMask": "0x4", 1183 "Unit": "IIO" 1184 }, 1185 { 1186 "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", 1187 "Counter": "0,1", 1188 "EventCode": "0x84", 1189 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7", 1190 "FCMask": "0x07", 1191 "PerPkg": "1", 1192 "PortMask": "0x080", 1193 "UMask": "0x4", 1194 "Unit": "IIO" 1195 }, 1196 { 1197 "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", 1198 "Counter": "0,1", 1199 "EventCode": "0x84", 1200 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", 1201 "FCMask": "0x07", 1202 "PerPkg": "1", 1203 "PortMask": "0x001", 1204 "UMask": "0x1", 1205 "Unit": "IIO" 1206 }, 1207 { 1208 "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", 1209 "Counter": "0,1", 1210 "EventCode": "0x84", 1211 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", 1212 "FCMask": "0x07", 1213 "PerPkg": "1", 1214 "PortMask": "0x002", 1215 "UMask": "0x1", 1216 "Unit": "IIO" 1217 }, 1218 { 1219 "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", 1220 "Counter": "0,1", 1221 "EventCode": "0x84", 1222 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", 1223 "FCMask": "0x07", 1224 "PerPkg": "1", 1225 "PortMask": "0x004", 1226 "UMask": "0x1", 1227 "Unit": "IIO" 1228 }, 1229 { 1230 "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", 1231 "Counter": "0,1", 1232 "EventCode": "0x84", 1233 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", 1234 "FCMask": "0x07", 1235 "PerPkg": "1", 1236 "PortMask": "0x008", 1237 "UMask": "0x1", 1238 "Unit": "IIO" 1239 }, 1240 { 1241 "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", 1242 "Counter": "0,1", 1243 "EventCode": "0x84", 1244 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4", 1245 "FCMask": "0x07", 1246 "PerPkg": "1", 1247 "PortMask": "0x010", 1248 "UMask": "0x1", 1249 "Unit": "IIO" 1250 }, 1251 { 1252 "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", 1253 "Counter": "0,1", 1254 "EventCode": "0x84", 1255 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5", 1256 "FCMask": "0x07", 1257 "PerPkg": "1", 1258 "PortMask": "0x020", 1259 "UMask": "0x1", 1260 "Unit": "IIO" 1261 }, 1262 { 1263 "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", 1264 "Counter": "0,1", 1265 "EventCode": "0x84", 1266 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6", 1267 "FCMask": "0x07", 1268 "PerPkg": "1", 1269 "PortMask": "0x040", 1270 "UMask": "0x1", 1271 "Unit": "IIO" 1272 }, 1273 { 1274 "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", 1275 "Counter": "0,1", 1276 "EventCode": "0x84", 1277 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7", 1278 "FCMask": "0x07", 1279 "PerPkg": "1", 1280 "PortMask": "0x080", 1281 "UMask": "0x1", 1282 "Unit": "IIO" 1283 }, 1284 { 1285 "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", 1286 "Counter": "0,1", 1287 "EventCode": "0x84", 1288 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", 1289 "Experimental": "1", 1290 "FCMask": "0x07", 1291 "PerPkg": "1", 1292 "PortMask": "0x001", 1293 "UMask": "0x2", 1294 "Unit": "IIO" 1295 }, 1296 { 1297 "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", 1298 "Counter": "0,1", 1299 "EventCode": "0x84", 1300 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", 1301 "Experimental": "1", 1302 "FCMask": "0x07", 1303 "PerPkg": "1", 1304 "PortMask": "0x002", 1305 "UMask": "0x2", 1306 "Unit": "IIO" 1307 }, 1308 { 1309 "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", 1310 "Counter": "0,1", 1311 "EventCode": "0x84", 1312 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", 1313 "Experimental": "1", 1314 "FCMask": "0x07", 1315 "PerPkg": "1", 1316 "PortMask": "0x004", 1317 "UMask": "0x2", 1318 "Unit": "IIO" 1319 }, 1320 { 1321 "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", 1322 "Counter": "0,1", 1323 "EventCode": "0x84", 1324 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", 1325 "Experimental": "1", 1326 "FCMask": "0x07", 1327 "PerPkg": "1", 1328 "PortMask": "0x008", 1329 "UMask": "0x2", 1330 "Unit": "IIO" 1331 }, 1332 { 1333 "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", 1334 "Counter": "0,1", 1335 "EventCode": "0x84", 1336 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4", 1337 "Experimental": "1", 1338 "FCMask": "0x07", 1339 "PerPkg": "1", 1340 "PortMask": "0x010", 1341 "UMask": "0x2", 1342 "Unit": "IIO" 1343 }, 1344 { 1345 "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", 1346 "Counter": "0,1", 1347 "EventCode": "0x84", 1348 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5", 1349 "Experimental": "1", 1350 "FCMask": "0x07", 1351 "PerPkg": "1", 1352 "PortMask": "0x020", 1353 "UMask": "0x2", 1354 "Unit": "IIO" 1355 }, 1356 { 1357 "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", 1358 "Counter": "0,1", 1359 "EventCode": "0x84", 1360 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6", 1361 "Experimental": "1", 1362 "FCMask": "0x07", 1363 "PerPkg": "1", 1364 "PortMask": "0x040", 1365 "UMask": "0x2", 1366 "Unit": "IIO" 1367 }, 1368 { 1369 "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", 1370 "Counter": "0,1", 1371 "EventCode": "0x84", 1372 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7", 1373 "Experimental": "1", 1374 "FCMask": "0x07", 1375 "PerPkg": "1", 1376 "PortMask": "0x080", 1377 "UMask": "0x2", 1378 "Unit": "IIO" 1379 } 1380]
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