FILE
floating-point.json

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linux-6.19.14/tools/perf/pmu-events/arch/x86/emeraldrapids/floating-point.json JSON
  1[
  2    {
  3        "BriefDescription": "ARITH.FPDIV_ACTIVE",
  4        "Counter": "0,1,2,3,4,5,6,7",
  5        "CounterMask": "1",
  6        "EventCode": "0xb0",
  7        "EventName": "ARITH.FPDIV_ACTIVE",
  8        "SampleAfterValue": "1000003",
  9        "UMask": "0x1"
 10    },
 11    {
 12        "BriefDescription": "Counts all microcode FP assists.",
 13        "Counter": "0,1,2,3,4,5,6,7",
 14        "EventCode": "0xc1",
 15        "EventName": "ASSISTS.FP",
 16        "PublicDescription": "Counts all microcode Floating Point assists.",
 17        "SampleAfterValue": "100003",
 18        "UMask": "0x2"
 19    },
 20    {
 21        "BriefDescription": "ASSISTS.SSE_AVX_MIX",
 22        "Counter": "0,1,2,3,4,5,6,7",
 23        "EventCode": "0xc1",
 24        "EventName": "ASSISTS.SSE_AVX_MIX",
 25        "SampleAfterValue": "1000003",
 26        "UMask": "0x10"
 27    },
 28    {
 29        "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0]",
 30        "Counter": "0,1,2,3,4,5,6,7",
 31        "EventCode": "0xb3",
 32        "EventName": "FP_ARITH_DISPATCHED.PORT_0",
 33        "SampleAfterValue": "2000003",
 34        "UMask": "0x1"
 35    },
 36    {
 37        "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1]",
 38        "Counter": "0,1,2,3,4,5,6,7",
 39        "EventCode": "0xb3",
 40        "EventName": "FP_ARITH_DISPATCHED.PORT_1",
 41        "SampleAfterValue": "2000003",
 42        "UMask": "0x2"
 43    },
 44    {
 45        "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2]",
 46        "Counter": "0,1,2,3,4,5,6,7",
 47        "EventCode": "0xb3",
 48        "EventName": "FP_ARITH_DISPATCHED.PORT_5",
 49        "SampleAfterValue": "2000003",
 50        "UMask": "0x4"
 51    },
 52    {
 53        "BriefDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0]",
 54        "Counter": "0,1,2,3,4,5,6,7",
 55        "EventCode": "0xb3",
 56        "EventName": "FP_ARITH_DISPATCHED.V0",
 57        "SampleAfterValue": "2000003",
 58        "UMask": "0x1"
 59    },
 60    {
 61        "BriefDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1]",
 62        "Counter": "0,1,2,3,4,5,6,7",
 63        "EventCode": "0xb3",
 64        "EventName": "FP_ARITH_DISPATCHED.V1",
 65        "SampleAfterValue": "2000003",
 66        "UMask": "0x2"
 67    },
 68    {
 69        "BriefDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5]",
 70        "Counter": "0,1,2,3,4,5,6,7",
 71        "EventCode": "0xb3",
 72        "EventName": "FP_ARITH_DISPATCHED.V2",
 73        "SampleAfterValue": "2000003",
 74        "UMask": "0x4"
 75    },
 76    {
 77        "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
 78        "Counter": "0,1,2,3,4,5,6,7",
 79        "EventCode": "0xc7",
 80        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
 81        "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
 82        "SampleAfterValue": "100003",
 83        "UMask": "0x4"
 84    },
 85    {
 86        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
 87        "Counter": "0,1,2,3,4,5,6,7",
 88        "EventCode": "0xc7",
 89        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
 90        "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
 91        "SampleAfterValue": "100003",
 92        "UMask": "0x8"
 93    },
 94    {
 95        "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
 96        "Counter": "0,1,2,3,4,5,6,7",
 97        "EventCode": "0xc7",
 98        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
 99        "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
100        "SampleAfterValue": "100003",
101        "UMask": "0x10"
102    },
103    {
104        "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
105        "Counter": "0,1,2,3,4,5,6,7",
106        "EventCode": "0xc7",
107        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
108        "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
109        "SampleAfterValue": "100003",
110        "UMask": "0x20"
111    },
112    {
113        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, 1 for each element.  Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",
114        "Counter": "0,1,2,3,4,5,6,7",
115        "EventCode": "0xc7",
116        "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS",
117        "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision  floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
118        "SampleAfterValue": "100003",
119        "UMask": "0x18"
120    },
121    {
122        "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
123        "Counter": "0,1,2,3,4,5,6,7",
124        "EventCode": "0xc7",
125        "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
126        "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
127        "SampleAfterValue": "100003",
128        "UMask": "0x40"
129    },
130    {
131        "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
132        "Counter": "0,1,2,3,4,5,6,7",
133        "EventCode": "0xc7",
134        "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
135        "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
136        "SampleAfterValue": "100003",
137        "UMask": "0x80"
138    },
139    {
140        "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision  FP instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, 1 for each element.  Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",
141        "Counter": "0,1,2,3,4,5,6,7",
142        "EventCode": "0xc7",
143        "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS",
144        "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision  floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
145        "SampleAfterValue": "100003",
146        "UMask": "0x60"
147    },
148    {
149        "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below.  Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
150        "Counter": "0,1,2,3,4,5,6,7",
151        "EventCode": "0xc7",
152        "EventName": "FP_ARITH_INST_RETIRED.SCALAR",
153        "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
154        "SampleAfterValue": "1000003",
155        "UMask": "0x3"
156    },
157    {
158        "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
159        "Counter": "0,1,2,3,4,5,6,7",
160        "EventCode": "0xc7",
161        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
162        "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
163        "SampleAfterValue": "100003",
164        "UMask": "0x1"
165    },
166    {
167        "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
168        "Counter": "0,1,2,3,4,5,6,7",
169        "EventCode": "0xc7",
170        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
171        "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
172        "SampleAfterValue": "100003",
173        "UMask": "0x2"
174    },
175    {
176        "BriefDescription": "Number of any Vector retired FP arithmetic instructions",
177        "Counter": "0,1,2,3,4,5,6,7",
178        "EventCode": "0xc7",
179        "EventName": "FP_ARITH_INST_RETIRED.VECTOR",
180        "PublicDescription": "Number of any Vector retired FP arithmetic instructions.  The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
181        "SampleAfterValue": "1000003",
182        "UMask": "0xfc"
183    },
184    {
185        "BriefDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF",
186        "Counter": "0,1,2,3,4,5,6,7",
187        "EventCode": "0xcf",
188        "EventName": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF",
189        "SampleAfterValue": "100003",
190        "UMask": "0x4"
191    },
192    {
193        "BriefDescription": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF",
194        "Counter": "0,1,2,3,4,5,6,7",
195        "EventCode": "0xcf",
196        "EventName": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF",
197        "SampleAfterValue": "100003",
198        "UMask": "0x8"
199    },
200    {
201        "BriefDescription": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF",
202        "Counter": "0,1,2,3,4,5,6,7",
203        "EventCode": "0xcf",
204        "EventName": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF",
205        "SampleAfterValue": "100003",
206        "UMask": "0x10"
207    },
208    {
209        "BriefDescription": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF",
210        "Counter": "0,1,2,3,4,5,6,7",
211        "EventCode": "0xcf",
212        "EventName": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF",
213        "SampleAfterValue": "100003",
214        "UMask": "0x2"
215    },
216    {
217        "BriefDescription": "Number of all Scalar Half-Precision FP arithmetic instructions(1) retired - regular and complex.",
218        "Counter": "0,1,2,3,4,5,6,7",
219        "EventCode": "0xcf",
220        "EventName": "FP_ARITH_INST_RETIRED2.SCALAR",
221        "PublicDescription": "FP_ARITH_INST_RETIRED2.SCALAR",
222        "SampleAfterValue": "100003",
223        "UMask": "0x3"
224    },
225    {
226        "BriefDescription": "FP_ARITH_INST_RETIRED2.SCALAR_HALF",
227        "Counter": "0,1,2,3,4,5,6,7",
228        "EventCode": "0xcf",
229        "EventName": "FP_ARITH_INST_RETIRED2.SCALAR_HALF",
230        "SampleAfterValue": "100003",
231        "UMask": "0x1"
232    },
233    {
234        "BriefDescription": "Number of all Vector (also called packed) Half-Precision FP arithmetic instructions(1) retired.",
235        "Counter": "0,1,2,3,4,5,6,7",
236        "EventCode": "0xcf",
237        "EventName": "FP_ARITH_INST_RETIRED2.VECTOR",
238        "PublicDescription": "FP_ARITH_INST_RETIRED2.VECTOR",
239        "SampleAfterValue": "100003",
240        "UMask": "0x1c"
241    }
242]
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