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memory.json
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linux-6.19.14/tools/perf/pmu-events/arch/x86/broadwell/memory.json
1[ 2 { 3 "BriefDescription": "Number of times HLE abort was triggered", 4 "Counter": "0,1,2,3", 5 "EventCode": "0xc8", 6 "EventName": "HLE_RETIRED.ABORTED", 7 "PEBS": "1", 8 "PublicDescription": "Number of times HLE abort was triggered.", 9 "SampleAfterValue": "2000003", 10 "UMask": "0x4" 11 }, 12 { 13 "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 14 "Counter": "0,1,2,3", 15 "EventCode": "0xc8", 16 "EventName": "HLE_RETIRED.ABORTED_MISC1", 17 "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).", 18 "SampleAfterValue": "2000003", 19 "UMask": "0x8" 20 }, 21 { 22 "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions", 23 "Counter": "0,1,2,3", 24 "EventCode": "0xc8", 25 "EventName": "HLE_RETIRED.ABORTED_MISC2", 26 "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.", 27 "SampleAfterValue": "2000003", 28 "UMask": "0x10" 29 }, 30 { 31 "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions", 32 "Counter": "0,1,2,3", 33 "EventCode": "0xc8", 34 "EventName": "HLE_RETIRED.ABORTED_MISC3", 35 "PublicDescription": "Number of times a disallowed operation caused an HLE abort.", 36 "SampleAfterValue": "2000003", 37 "UMask": "0x20" 38 }, 39 { 40 "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", 41 "Counter": "0,1,2,3", 42 "EventCode": "0xc8", 43 "EventName": "HLE_RETIRED.ABORTED_MISC4", 44 "PublicDescription": "Number of times HLE caused a fault.", 45 "SampleAfterValue": "2000003", 46 "UMask": "0x40" 47 }, 48 { 49 "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)", 50 "Counter": "0,1,2,3", 51 "EventCode": "0xc8", 52 "EventName": "HLE_RETIRED.ABORTED_MISC5", 53 "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.", 54 "SampleAfterValue": "2000003", 55 "UMask": "0x80" 56 }, 57 { 58 "BriefDescription": "Number of times HLE commit succeeded", 59 "Counter": "0,1,2,3", 60 "EventCode": "0xc8", 61 "EventName": "HLE_RETIRED.COMMIT", 62 "PublicDescription": "Number of times HLE commit succeeded.", 63 "SampleAfterValue": "2000003", 64 "UMask": "0x2" 65 }, 66 { 67 "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions", 68 "Counter": "0,1,2,3", 69 "EventCode": "0xc8", 70 "EventName": "HLE_RETIRED.START", 71 "PublicDescription": "Number of times we entered an HLE region does not count nested transactions.", 72 "SampleAfterValue": "2000003", 73 "UMask": "0x1" 74 }, 75 { 76 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 77 "Counter": "0,1,2,3", 78 "EventCode": "0xC3", 79 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 80 "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following: 1. memory disambiguation, 2. external snoop, or 3. cross SMT-HW-thread snoop (stores) hitting load buffer.", 81 "SampleAfterValue": "100003", 82 "UMask": "0x2" 83 }, 84 { 85 "BriefDescription": "Randomly selected loads with latency value being above 128", 86 "Counter": "3", 87 "Data_LA": "1", 88 "Errata": "BDM100, BDM35", 89 "EventCode": "0xcd", 90 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 91 "MSRIndex": "0x3F6", 92 "MSRValue": "0x80", 93 "PEBS": "2", 94 "PublicDescription": "Counts randomly selected loads with latency value being above 128.", 95 "SampleAfterValue": "1009", 96 "UMask": "0x1" 97 }, 98 { 99 "BriefDescription": "Randomly selected loads with latency value being above 16", 100 "Counter": "3", 101 "Data_LA": "1", 102 "Errata": "BDM100, BDM35", 103 "EventCode": "0xcd", 104 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 105 "MSRIndex": "0x3F6", 106 "MSRValue": "0x10", 107 "PEBS": "2", 108 "PublicDescription": "Counts randomly selected loads with latency value being above 16.", 109 "SampleAfterValue": "20011", 110 "UMask": "0x1" 111 }, 112 { 113 "BriefDescription": "Randomly selected loads with latency value being above 256", 114 "Counter": "3", 115 "Data_LA": "1", 116 "Errata": "BDM100, BDM35", 117 "EventCode": "0xcd", 118 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 119 "MSRIndex": "0x3F6", 120 "MSRValue": "0x100", 121 "PEBS": "2", 122 "PublicDescription": "Counts randomly selected loads with latency value being above 256.", 123 "SampleAfterValue": "503", 124 "UMask": "0x1" 125 }, 126 { 127 "BriefDescription": "Randomly selected loads with latency value being above 32", 128 "Counter": "3", 129 "Data_LA": "1", 130 "Errata": "BDM100, BDM35", 131 "EventCode": "0xcd", 132 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 133 "MSRIndex": "0x3F6", 134 "MSRValue": "0x20", 135 "PEBS": "2", 136 "PublicDescription": "Counts randomly selected loads with latency value being above 32.", 137 "SampleAfterValue": "100007", 138 "UMask": "0x1" 139 }, 140 { 141 "BriefDescription": "Randomly selected loads with latency value being above 4", 142 "Counter": "3", 143 "Data_LA": "1", 144 "Errata": "BDM100, BDM35", 145 "EventCode": "0xcd", 146 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 147 "MSRIndex": "0x3F6", 148 "MSRValue": "0x4", 149 "PEBS": "2", 150 "PublicDescription": "Counts randomly selected loads with latency value being above four.", 151 "SampleAfterValue": "100003", 152 "UMask": "0x1" 153 }, 154 { 155 "BriefDescription": "Randomly selected loads with latency value being above 512", 156 "Counter": "3", 157 "Data_LA": "1", 158 "Errata": "BDM100, BDM35", 159 "EventCode": "0xcd", 160 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 161 "MSRIndex": "0x3F6", 162 "MSRValue": "0x200", 163 "PEBS": "2", 164 "PublicDescription": "Counts randomly selected loads with latency value being above 512.", 165 "SampleAfterValue": "101", 166 "UMask": "0x1" 167 }, 168 { 169 "BriefDescription": "Randomly selected loads with latency value being above 64", 170 "Counter": "3", 171 "Data_LA": "1", 172 "Errata": "BDM100, BDM35", 173 "EventCode": "0xcd", 174 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 175 "MSRIndex": "0x3F6", 176 "MSRValue": "0x40", 177 "PEBS": "2", 178 "PublicDescription": "Counts randomly selected loads with latency value being above 64.", 179 "SampleAfterValue": "2003", 180 "UMask": "0x1" 181 }, 182 { 183 "BriefDescription": "Randomly selected loads with latency value being above 8", 184 "Counter": "3", 185 "Data_LA": "1", 186 "Errata": "BDM100, BDM35", 187 "EventCode": "0xcd", 188 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 189 "MSRIndex": "0x3F6", 190 "MSRValue": "0x8", 191 "PEBS": "2", 192 "PublicDescription": "Counts randomly selected loads with latency value being above eight.", 193 "SampleAfterValue": "50021", 194 "UMask": "0x1" 195 }, 196 { 197 "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", 198 "Counter": "0,1,2,3", 199 "EventCode": "0x05", 200 "EventName": "MISALIGN_MEM_REF.LOADS", 201 "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.", 202 "SampleAfterValue": "2000003", 203 "UMask": "0x1" 204 }, 205 { 206 "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", 207 "Counter": "0,1,2,3", 208 "EventCode": "0x05", 209 "EventName": "MISALIGN_MEM_REF.STORES", 210 "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.", 211 "SampleAfterValue": "2000003", 212 "UMask": "0x2" 213 }, 214 { 215 "BriefDescription": "Counts all demand & prefetch data reads", 216 "Counter": "0,1,2,3", 217 "EventCode": "0xB7, 0xBB", 218 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NON_DRAM", 219 "MSRIndex": "0x1a6,0x1a7", 220 "MSRValue": "0x20003C0091", 221 "SampleAfterValue": "100003", 222 "UMask": "0x1" 223 }, 224 { 225 "BriefDescription": "Counts all demand & prefetch data reads", 226 "Counter": "0,1,2,3", 227 "EventCode": "0xB7, 0xBB", 228 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", 229 "MSRIndex": "0x1a6,0x1a7", 230 "MSRValue": "0x43C000091", 231 "SampleAfterValue": "100003", 232 "UMask": "0x1" 233 }, 234 { 235 "BriefDescription": "Counts all demand & prefetch data reads", 236 "Counter": "0,1,2,3", 237 "EventCode": "0xB7, 0xBB", 238 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS", 239 "MSRIndex": "0x1a6,0x1a7", 240 "MSRValue": "0x23C000091", 241 "SampleAfterValue": "100003", 242 "UMask": "0x1" 243 }, 244 { 245 "BriefDescription": "Counts all demand & prefetch data reads", 246 "Counter": "0,1,2,3", 247 "EventCode": "0xB7, 0xBB", 248 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NONE", 249 "MSRIndex": "0x1a6,0x1a7", 250 "MSRValue": "0xBC000091", 251 "SampleAfterValue": "100003", 252 "UMask": "0x1" 253 }, 254 { 255 "BriefDescription": "Counts all demand & prefetch data reads", 256 "Counter": "0,1,2,3", 257 "EventCode": "0xB7, 0xBB", 258 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED", 259 "MSRIndex": "0x1a6,0x1a7", 260 "MSRValue": "0x13C000091", 261 "SampleAfterValue": "100003", 262 "UMask": "0x1" 263 }, 264 { 265 "BriefDescription": "Counts all demand & prefetch data reads", 266 "Counter": "0,1,2,3", 267 "EventCode": "0xB7, 0xBB", 268 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 269 "MSRIndex": "0x1a6,0x1a7", 270 "MSRValue": "0x3F84000091", 271 "SampleAfterValue": "100003", 272 "UMask": "0x1" 273 }, 274 { 275 "BriefDescription": "Counts all demand & prefetch data reads", 276 "Counter": "0,1,2,3", 277 "EventCode": "0xB7, 0xBB", 278 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 279 "MSRIndex": "0x1a6,0x1a7", 280 "MSRValue": "0x1004000091", 281 "SampleAfterValue": "100003", 282 "UMask": "0x1" 283 }, 284 { 285 "BriefDescription": "Counts all demand & prefetch data reads", 286 "Counter": "0,1,2,3", 287 "EventCode": "0xB7, 0xBB", 288 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 289 "MSRIndex": "0x1a6,0x1a7", 290 "MSRValue": "0x404000091", 291 "SampleAfterValue": "100003", 292 "UMask": "0x1" 293 }, 294 { 295 "BriefDescription": "Counts all demand & prefetch data reads", 296 "Counter": "0,1,2,3", 297 "EventCode": "0xB7, 0xBB", 298 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 299 "MSRIndex": "0x1a6,0x1a7", 300 "MSRValue": "0x204000091", 301 "SampleAfterValue": "100003", 302 "UMask": "0x1" 303 }, 304 { 305 "BriefDescription": "Counts all demand & prefetch data reads", 306 "Counter": "0,1,2,3", 307 "EventCode": "0xB7, 0xBB", 308 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 309 "MSRIndex": "0x1a6,0x1a7", 310 "MSRValue": "0x84000091", 311 "SampleAfterValue": "100003", 312 "UMask": "0x1" 313 }, 314 { 315 "BriefDescription": "Counts all demand & prefetch data reads", 316 "Counter": "0,1,2,3", 317 "EventCode": "0xB7, 0xBB", 318 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 319 "MSRIndex": "0x1a6,0x1a7", 320 "MSRValue": "0x2004000091", 321 "SampleAfterValue": "100003", 322 "UMask": "0x1" 323 }, 324 { 325 "BriefDescription": "Counts all demand & prefetch data reads", 326 "Counter": "0,1,2,3", 327 "EventCode": "0xB7, 0xBB", 328 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 329 "MSRIndex": "0x1a6,0x1a7", 330 "MSRValue": "0x104000091", 331 "SampleAfterValue": "100003", 332 "UMask": "0x1" 333 }, 334 { 335 "BriefDescription": "Counts all demand & prefetch data reads", 336 "Counter": "0,1,2,3", 337 "EventCode": "0xB7, 0xBB", 338 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", 339 "MSRIndex": "0x1a6,0x1a7", 340 "MSRValue": "0x2000020091", 341 "SampleAfterValue": "100003", 342 "UMask": "0x1" 343 }, 344 { 345 "BriefDescription": "Counts all prefetch code reads", 346 "Counter": "0,1,2,3", 347 "EventCode": "0xB7, 0xBB", 348 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NON_DRAM", 349 "MSRIndex": "0x1a6,0x1a7", 350 "MSRValue": "0x20003C0240", 351 "SampleAfterValue": "100003", 352 "UMask": "0x1" 353 }, 354 { 355 "BriefDescription": "Counts all prefetch code reads", 356 "Counter": "0,1,2,3", 357 "EventCode": "0xB7, 0xBB", 358 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD", 359 "MSRIndex": "0x1a6,0x1a7", 360 "MSRValue": "0x43C000240", 361 "SampleAfterValue": "100003", 362 "UMask": "0x1" 363 }, 364 { 365 "BriefDescription": "Counts all prefetch code reads", 366 "Counter": "0,1,2,3", 367 "EventCode": "0xB7, 0xBB", 368 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_MISS", 369 "MSRIndex": "0x1a6,0x1a7", 370 "MSRValue": "0x23C000240", 371 "SampleAfterValue": "100003", 372 "UMask": "0x1" 373 }, 374 { 375 "BriefDescription": "Counts all prefetch code reads", 376 "Counter": "0,1,2,3", 377 "EventCode": "0xB7, 0xBB", 378 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_NONE", 379 "MSRIndex": "0x1a6,0x1a7", 380 "MSRValue": "0xBC000240", 381 "SampleAfterValue": "100003", 382 "UMask": "0x1" 383 }, 384 { 385 "BriefDescription": "Counts all prefetch code reads", 386 "Counter": "0,1,2,3", 387 "EventCode": "0xB7, 0xBB", 388 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED", 389 "MSRIndex": "0x1a6,0x1a7", 390 "MSRValue": "0x13C000240", 391 "SampleAfterValue": "100003", 392 "UMask": "0x1" 393 }, 394 { 395 "BriefDescription": "Counts all prefetch code reads", 396 "Counter": "0,1,2,3", 397 "EventCode": "0xB7, 0xBB", 398 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 399 "MSRIndex": "0x1a6,0x1a7", 400 "MSRValue": "0x3F84000240", 401 "SampleAfterValue": "100003", 402 "UMask": "0x1" 403 }, 404 { 405 "BriefDescription": "Counts all prefetch code reads", 406 "Counter": "0,1,2,3", 407 "EventCode": "0xB7, 0xBB", 408 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 409 "MSRIndex": "0x1a6,0x1a7", 410 "MSRValue": "0x1004000240", 411 "SampleAfterValue": "100003", 412 "UMask": "0x1" 413 }, 414 { 415 "BriefDescription": "Counts all prefetch code reads", 416 "Counter": "0,1,2,3", 417 "EventCode": "0xB7, 0xBB", 418 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 419 "MSRIndex": "0x1a6,0x1a7", 420 "MSRValue": "0x404000240", 421 "SampleAfterValue": "100003", 422 "UMask": "0x1" 423 }, 424 { 425 "BriefDescription": "Counts all prefetch code reads", 426 "Counter": "0,1,2,3", 427 "EventCode": "0xB7, 0xBB", 428 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 429 "MSRIndex": "0x1a6,0x1a7", 430 "MSRValue": "0x204000240", 431 "SampleAfterValue": "100003", 432 "UMask": "0x1" 433 }, 434 { 435 "BriefDescription": "Counts all prefetch code reads", 436 "Counter": "0,1,2,3", 437 "EventCode": "0xB7, 0xBB", 438 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 439 "MSRIndex": "0x1a6,0x1a7", 440 "MSRValue": "0x84000240", 441 "SampleAfterValue": "100003", 442 "UMask": "0x1" 443 }, 444 { 445 "BriefDescription": "Counts all prefetch code reads", 446 "Counter": "0,1,2,3", 447 "EventCode": "0xB7, 0xBB", 448 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 449 "MSRIndex": "0x1a6,0x1a7", 450 "MSRValue": "0x2004000240", 451 "SampleAfterValue": "100003", 452 "UMask": "0x1" 453 }, 454 { 455 "BriefDescription": "Counts all prefetch code reads", 456 "Counter": "0,1,2,3", 457 "EventCode": "0xB7, 0xBB", 458 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 459 "MSRIndex": "0x1a6,0x1a7", 460 "MSRValue": "0x104000240", 461 "SampleAfterValue": "100003", 462 "UMask": "0x1" 463 }, 464 { 465 "BriefDescription": "Counts all prefetch code reads", 466 "Counter": "0,1,2,3", 467 "EventCode": "0xB7, 0xBB", 468 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", 469 "MSRIndex": "0x1a6,0x1a7", 470 "MSRValue": "0x2000020240", 471 "SampleAfterValue": "100003", 472 "UMask": "0x1" 473 }, 474 { 475 "BriefDescription": "Counts all prefetch data reads", 476 "Counter": "0,1,2,3", 477 "EventCode": "0xB7, 0xBB", 478 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NON_DRAM", 479 "MSRIndex": "0x1a6,0x1a7", 480 "MSRValue": "0x20003C0090", 481 "SampleAfterValue": "100003", 482 "UMask": "0x1" 483 }, 484 { 485 "BriefDescription": "Counts all prefetch data reads", 486 "Counter": "0,1,2,3", 487 "EventCode": "0xB7, 0xBB", 488 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", 489 "MSRIndex": "0x1a6,0x1a7", 490 "MSRValue": "0x43C000090", 491 "SampleAfterValue": "100003", 492 "UMask": "0x1" 493 }, 494 { 495 "BriefDescription": "Counts all prefetch data reads", 496 "Counter": "0,1,2,3", 497 "EventCode": "0xB7, 0xBB", 498 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS", 499 "MSRIndex": "0x1a6,0x1a7", 500 "MSRValue": "0x23C000090", 501 "SampleAfterValue": "100003", 502 "UMask": "0x1" 503 }, 504 { 505 "BriefDescription": "Counts all prefetch data reads", 506 "Counter": "0,1,2,3", 507 "EventCode": "0xB7, 0xBB", 508 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE", 509 "MSRIndex": "0x1a6,0x1a7", 510 "MSRValue": "0xBC000090", 511 "SampleAfterValue": "100003", 512 "UMask": "0x1" 513 }, 514 { 515 "BriefDescription": "Counts all prefetch data reads", 516 "Counter": "0,1,2,3", 517 "EventCode": "0xB7, 0xBB", 518 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED", 519 "MSRIndex": "0x1a6,0x1a7", 520 "MSRValue": "0x13C000090", 521 "SampleAfterValue": "100003", 522 "UMask": "0x1" 523 }, 524 { 525 "BriefDescription": "Counts all prefetch data reads", 526 "Counter": "0,1,2,3", 527 "EventCode": "0xB7, 0xBB", 528 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 529 "MSRIndex": "0x1a6,0x1a7", 530 "MSRValue": "0x3F84000090", 531 "SampleAfterValue": "100003", 532 "UMask": "0x1" 533 }, 534 { 535 "BriefDescription": "Counts all prefetch data reads", 536 "Counter": "0,1,2,3", 537 "EventCode": "0xB7, 0xBB", 538 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 539 "MSRIndex": "0x1a6,0x1a7", 540 "MSRValue": "0x1004000090", 541 "SampleAfterValue": "100003", 542 "UMask": "0x1" 543 }, 544 { 545 "BriefDescription": "Counts all prefetch data reads", 546 "Counter": "0,1,2,3", 547 "EventCode": "0xB7, 0xBB", 548 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 549 "MSRIndex": "0x1a6,0x1a7", 550 "MSRValue": "0x404000090", 551 "SampleAfterValue": "100003", 552 "UMask": "0x1" 553 }, 554 { 555 "BriefDescription": "Counts all prefetch data reads", 556 "Counter": "0,1,2,3", 557 "EventCode": "0xB7, 0xBB", 558 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 559 "MSRIndex": "0x1a6,0x1a7", 560 "MSRValue": "0x204000090", 561 "SampleAfterValue": "100003", 562 "UMask": "0x1" 563 }, 564 { 565 "BriefDescription": "Counts all prefetch data reads", 566 "Counter": "0,1,2,3", 567 "EventCode": "0xB7, 0xBB", 568 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 569 "MSRIndex": "0x1a6,0x1a7", 570 "MSRValue": "0x84000090", 571 "SampleAfterValue": "100003", 572 "UMask": "0x1" 573 }, 574 { 575 "BriefDescription": "Counts all prefetch data reads", 576 "Counter": "0,1,2,3", 577 "EventCode": "0xB7, 0xBB", 578 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 579 "MSRIndex": "0x1a6,0x1a7", 580 "MSRValue": "0x2004000090", 581 "SampleAfterValue": "100003", 582 "UMask": "0x1" 583 }, 584 { 585 "BriefDescription": "Counts all prefetch data reads", 586 "Counter": "0,1,2,3", 587 "EventCode": "0xB7, 0xBB", 588 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 589 "MSRIndex": "0x1a6,0x1a7", 590 "MSRValue": "0x104000090", 591 "SampleAfterValue": "100003", 592 "UMask": "0x1" 593 }, 594 { 595 "BriefDescription": "Counts all prefetch data reads", 596 "Counter": "0,1,2,3", 597 "EventCode": "0xB7, 0xBB", 598 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", 599 "MSRIndex": "0x1a6,0x1a7", 600 "MSRValue": "0x2000020090", 601 "SampleAfterValue": "100003", 602 "UMask": "0x1" 603 }, 604 { 605 "BriefDescription": "Counts prefetch RFOs", 606 "Counter": "0,1,2,3", 607 "EventCode": "0xB7, 0xBB", 608 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NON_DRAM", 609 "MSRIndex": "0x1a6,0x1a7", 610 "MSRValue": "0x20003C0120", 611 "SampleAfterValue": "100003", 612 "UMask": "0x1" 613 }, 614 { 615 "BriefDescription": "Counts prefetch RFOs", 616 "Counter": "0,1,2,3", 617 "EventCode": "0xB7, 0xBB", 618 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_HIT_NO_FWD", 619 "MSRIndex": "0x1a6,0x1a7", 620 "MSRValue": "0x43C000120", 621 "SampleAfterValue": "100003", 622 "UMask": "0x1" 623 }, 624 { 625 "BriefDescription": "Counts prefetch RFOs", 626 "Counter": "0,1,2,3", 627 "EventCode": "0xB7, 0xBB", 628 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS", 629 "MSRIndex": "0x1a6,0x1a7", 630 "MSRValue": "0x23C000120", 631 "SampleAfterValue": "100003", 632 "UMask": "0x1" 633 }, 634 { 635 "BriefDescription": "Counts prefetch RFOs", 636 "Counter": "0,1,2,3", 637 "EventCode": "0xB7, 0xBB", 638 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_NONE", 639 "MSRIndex": "0x1a6,0x1a7", 640 "MSRValue": "0xBC000120", 641 "SampleAfterValue": "100003", 642 "UMask": "0x1" 643 }, 644 { 645 "BriefDescription": "Counts prefetch RFOs", 646 "Counter": "0,1,2,3", 647 "EventCode": "0xB7, 0xBB", 648 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_NOT_NEEDED", 649 "MSRIndex": "0x1a6,0x1a7", 650 "MSRValue": "0x13C000120", 651 "SampleAfterValue": "100003", 652 "UMask": "0x1" 653 }, 654 { 655 "BriefDescription": "Counts prefetch RFOs", 656 "Counter": "0,1,2,3", 657 "EventCode": "0xB7, 0xBB", 658 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 659 "MSRIndex": "0x1a6,0x1a7", 660 "MSRValue": "0x3F84000120", 661 "SampleAfterValue": "100003", 662 "UMask": "0x1" 663 }, 664 { 665 "BriefDescription": "Counts prefetch RFOs", 666 "Counter": "0,1,2,3", 667 "EventCode": "0xB7, 0xBB", 668 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 669 "MSRIndex": "0x1a6,0x1a7", 670 "MSRValue": "0x1004000120", 671 "SampleAfterValue": "100003", 672 "UMask": "0x1" 673 }, 674 { 675 "BriefDescription": "Counts prefetch RFOs", 676 "Counter": "0,1,2,3", 677 "EventCode": "0xB7, 0xBB", 678 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 679 "MSRIndex": "0x1a6,0x1a7", 680 "MSRValue": "0x404000120", 681 "SampleAfterValue": "100003", 682 "UMask": "0x1" 683 }, 684 { 685 "BriefDescription": "Counts prefetch RFOs", 686 "Counter": "0,1,2,3", 687 "EventCode": "0xB7, 0xBB", 688 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 689 "MSRIndex": "0x1a6,0x1a7", 690 "MSRValue": "0x204000120", 691 "SampleAfterValue": "100003", 692 "UMask": "0x1" 693 }, 694 { 695 "BriefDescription": "Counts prefetch RFOs", 696 "Counter": "0,1,2,3", 697 "EventCode": "0xB7, 0xBB", 698 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 699 "MSRIndex": "0x1a6,0x1a7", 700 "MSRValue": "0x84000120", 701 "SampleAfterValue": "100003", 702 "UMask": "0x1" 703 }, 704 { 705 "BriefDescription": "Counts prefetch RFOs", 706 "Counter": "0,1,2,3", 707 "EventCode": "0xB7, 0xBB", 708 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 709 "MSRIndex": "0x1a6,0x1a7", 710 "MSRValue": "0x2004000120", 711 "SampleAfterValue": "100003", 712 "UMask": "0x1" 713 }, 714 { 715 "BriefDescription": "Counts prefetch RFOs", 716 "Counter": "0,1,2,3", 717 "EventCode": "0xB7, 0xBB", 718 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 719 "MSRIndex": "0x1a6,0x1a7", 720 "MSRValue": "0x104000120", 721 "SampleAfterValue": "100003", 722 "UMask": "0x1" 723 }, 724 { 725 "BriefDescription": "Counts prefetch RFOs", 726 "Counter": "0,1,2,3", 727 "EventCode": "0xB7, 0xBB", 728 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM", 729 "MSRIndex": "0x1a6,0x1a7", 730 "MSRValue": "0x2000020120", 731 "SampleAfterValue": "100003", 732 "UMask": "0x1" 733 }, 734 { 735 "BriefDescription": "Counts all demand & prefetch RFOs", 736 "Counter": "0,1,2,3", 737 "EventCode": "0xB7, 0xBB", 738 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NON_DRAM", 739 "MSRIndex": "0x1a6,0x1a7", 740 "MSRValue": "0x20003C0122", 741 "SampleAfterValue": "100003", 742 "UMask": "0x1" 743 }, 744 { 745 "BriefDescription": "Counts all demand & prefetch RFOs", 746 "Counter": "0,1,2,3", 747 "EventCode": "0xB7, 0xBB", 748 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_HIT_NO_FWD", 749 "MSRIndex": "0x1a6,0x1a7", 750 "MSRValue": "0x43C000122", 751 "SampleAfterValue": "100003", 752 "UMask": "0x1" 753 }, 754 { 755 "BriefDescription": "Counts all demand & prefetch RFOs", 756 "Counter": "0,1,2,3", 757 "EventCode": "0xB7, 0xBB", 758 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS", 759 "MSRIndex": "0x1a6,0x1a7", 760 "MSRValue": "0x23C000122", 761 "SampleAfterValue": "100003", 762 "UMask": "0x1" 763 }, 764 { 765 "BriefDescription": "Counts all demand & prefetch RFOs", 766 "Counter": "0,1,2,3", 767 "EventCode": "0xB7, 0xBB", 768 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_NONE", 769 "MSRIndex": "0x1a6,0x1a7", 770 "MSRValue": "0xBC000122", 771 "SampleAfterValue": "100003", 772 "UMask": "0x1" 773 }, 774 { 775 "BriefDescription": "Counts all demand & prefetch RFOs", 776 "Counter": "0,1,2,3", 777 "EventCode": "0xB7, 0xBB", 778 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_NOT_NEEDED", 779 "MSRIndex": "0x1a6,0x1a7", 780 "MSRValue": "0x13C000122", 781 "SampleAfterValue": "100003", 782 "UMask": "0x1" 783 }, 784 { 785 "BriefDescription": "Counts all demand & prefetch RFOs", 786 "Counter": "0,1,2,3", 787 "EventCode": "0xB7, 0xBB", 788 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 789 "MSRIndex": "0x1a6,0x1a7", 790 "MSRValue": "0x3F84000122", 791 "SampleAfterValue": "100003", 792 "UMask": "0x1" 793 }, 794 { 795 "BriefDescription": "Counts all demand & prefetch RFOs", 796 "Counter": "0,1,2,3", 797 "EventCode": "0xB7, 0xBB", 798 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 799 "MSRIndex": "0x1a6,0x1a7", 800 "MSRValue": "0x1004000122", 801 "SampleAfterValue": "100003", 802 "UMask": "0x1" 803 }, 804 { 805 "BriefDescription": "Counts all demand & prefetch RFOs", 806 "Counter": "0,1,2,3", 807 "EventCode": "0xB7, 0xBB", 808 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 809 "MSRIndex": "0x1a6,0x1a7", 810 "MSRValue": "0x404000122", 811 "SampleAfterValue": "100003", 812 "UMask": "0x1" 813 }, 814 { 815 "BriefDescription": "Counts all demand & prefetch RFOs", 816 "Counter": "0,1,2,3", 817 "EventCode": "0xB7, 0xBB", 818 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 819 "MSRIndex": "0x1a6,0x1a7", 820 "MSRValue": "0x204000122", 821 "SampleAfterValue": "100003", 822 "UMask": "0x1" 823 }, 824 { 825 "BriefDescription": "Counts all demand & prefetch RFOs", 826 "Counter": "0,1,2,3", 827 "EventCode": "0xB7, 0xBB", 828 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 829 "MSRIndex": "0x1a6,0x1a7", 830 "MSRValue": "0x84000122", 831 "SampleAfterValue": "100003", 832 "UMask": "0x1" 833 }, 834 { 835 "BriefDescription": "Counts all demand & prefetch RFOs", 836 "Counter": "0,1,2,3", 837 "EventCode": "0xB7, 0xBB", 838 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 839 "MSRIndex": "0x1a6,0x1a7", 840 "MSRValue": "0x2004000122", 841 "SampleAfterValue": "100003", 842 "UMask": "0x1" 843 }, 844 { 845 "BriefDescription": "Counts all demand & prefetch RFOs", 846 "Counter": "0,1,2,3", 847 "EventCode": "0xB7, 0xBB", 848 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 849 "MSRIndex": "0x1a6,0x1a7", 850 "MSRValue": "0x104000122", 851 "SampleAfterValue": "100003", 852 "UMask": "0x1" 853 }, 854 { 855 "BriefDescription": "Counts all demand & prefetch RFOs", 856 "Counter": "0,1,2,3", 857 "EventCode": "0xB7, 0xBB", 858 "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM", 859 "MSRIndex": "0x1a6,0x1a7", 860 "MSRValue": "0x2000020122", 861 "SampleAfterValue": "100003", 862 "UMask": "0x1" 863 }, 864 { 865 "BriefDescription": "Counts writebacks (modified to exclusive)", 866 "Counter": "0,1,2,3", 867 "EventCode": "0xB7, 0xBB", 868 "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_NON_DRAM", 869 "MSRIndex": "0x1a6,0x1a7", 870 "MSRValue": "0x20003C0008", 871 "SampleAfterValue": "100003", 872 "UMask": "0x1" 873 }, 874 { 875 "BriefDescription": "Counts writebacks (modified to exclusive)", 876 "Counter": "0,1,2,3", 877 "EventCode": "0xB7, 0xBB", 878 "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_HIT_NO_FWD", 879 "MSRIndex": "0x1a6,0x1a7", 880 "MSRValue": "0x43C000008", 881 "SampleAfterValue": "100003", 882 "UMask": "0x1" 883 }, 884 { 885 "BriefDescription": "Counts writebacks (modified to exclusive)", 886 "Counter": "0,1,2,3", 887 "EventCode": "0xB7, 0xBB", 888 "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_MISS", 889 "MSRIndex": "0x1a6,0x1a7", 890 "MSRValue": "0x23C000008", 891 "SampleAfterValue": "100003", 892 "UMask": "0x1" 893 }, 894 { 895 "BriefDescription": "Counts writebacks (modified to exclusive)", 896 "Counter": "0,1,2,3", 897 "EventCode": "0xB7, 0xBB", 898 "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_NONE", 899 "MSRIndex": "0x1a6,0x1a7", 900 "MSRValue": "0xBC000008", 901 "SampleAfterValue": "100003", 902 "UMask": "0x1" 903 }, 904 { 905 "BriefDescription": "Counts writebacks (modified to exclusive)", 906 "Counter": "0,1,2,3", 907 "EventCode": "0xB7, 0xBB", 908 "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_NOT_NEEDED", 909 "MSRIndex": "0x1a6,0x1a7", 910 "MSRValue": "0x13C000008", 911 "SampleAfterValue": "100003", 912 "UMask": "0x1" 913 }, 914 { 915 "BriefDescription": "Counts writebacks (modified to exclusive)", 916 "Counter": "0,1,2,3", 917 "EventCode": "0xB7, 0xBB", 918 "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 919 "MSRIndex": "0x1a6,0x1a7", 920 "MSRValue": "0x3F84000008", 921 "SampleAfterValue": "100003", 922 "UMask": "0x1" 923 }, 924 { 925 "BriefDescription": "Counts writebacks (modified to exclusive)", 926 "Counter": "0,1,2,3", 927 "EventCode": "0xB7, 0xBB", 928 "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 929 "MSRIndex": "0x1a6,0x1a7", 930 "MSRValue": "0x1004000008", 931 "SampleAfterValue": "100003", 932 "UMask": "0x1" 933 }, 934 { 935 "BriefDescription": "Counts writebacks (modified to exclusive)", 936 "Counter": "0,1,2,3", 937 "EventCode": "0xB7, 0xBB", 938 "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 939 "MSRIndex": "0x1a6,0x1a7", 940 "MSRValue": "0x404000008", 941 "SampleAfterValue": "100003", 942 "UMask": "0x1" 943 }, 944 { 945 "BriefDescription": "Counts writebacks (modified to exclusive)", 946 "Counter": "0,1,2,3", 947 "EventCode": "0xB7, 0xBB", 948 "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 949 "MSRIndex": "0x1a6,0x1a7", 950 "MSRValue": "0x204000008", 951 "SampleAfterValue": "100003", 952 "UMask": "0x1" 953 }, 954 { 955 "BriefDescription": "Counts writebacks (modified to exclusive)", 956 "Counter": "0,1,2,3", 957 "EventCode": "0xB7, 0xBB", 958 "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 959 "MSRIndex": "0x1a6,0x1a7", 960 "MSRValue": "0x84000008", 961 "SampleAfterValue": "100003", 962 "UMask": "0x1" 963 }, 964 { 965 "BriefDescription": "Counts writebacks (modified to exclusive)", 966 "Counter": "0,1,2,3", 967 "EventCode": "0xB7, 0xBB", 968 "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 969 "MSRIndex": "0x1a6,0x1a7", 970 "MSRValue": "0x2004000008", 971 "SampleAfterValue": "100003", 972 "UMask": "0x1" 973 }, 974 { 975 "BriefDescription": "Counts writebacks (modified to exclusive)", 976 "Counter": "0,1,2,3", 977 "EventCode": "0xB7, 0xBB", 978 "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 979 "MSRIndex": "0x1a6,0x1a7", 980 "MSRValue": "0x104000008", 981 "SampleAfterValue": "100003", 982 "UMask": "0x1" 983 }, 984 { 985 "BriefDescription": "Counts writebacks (modified to exclusive)", 986 "Counter": "0,1,2,3", 987 "EventCode": "0xB7, 0xBB", 988 "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_NON_DRAM", 989 "MSRIndex": "0x1a6,0x1a7", 990 "MSRValue": "0x2000020008", 991 "SampleAfterValue": "100003", 992 "UMask": "0x1" 993 }, 994 { 995 "BriefDescription": "Counts all demand code reads", 996 "Counter": "0,1,2,3", 997 "EventCode": "0xB7, 0xBB", 998 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NON_DRAM", 999 "MSRIndex": "0x1a6,0x1a7", 1000 "MSRValue": "0x20003C0004", 1001 "SampleAfterValue": "100003", 1002 "UMask": "0x1" 1003 }, 1004 { 1005 "BriefDescription": "Counts all demand code reads", 1006 "Counter": "0,1,2,3", 1007 "EventCode": "0xB7, 0xBB", 1008 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD", 1009 "MSRIndex": "0x1a6,0x1a7", 1010 "MSRValue": "0x43C000004", 1011 "SampleAfterValue": "100003", 1012 "UMask": "0x1" 1013 }, 1014 { 1015 "BriefDescription": "Counts all demand code reads", 1016 "Counter": "0,1,2,3", 1017 "EventCode": "0xB7, 0xBB", 1018 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", 1019 "MSRIndex": "0x1a6,0x1a7", 1020 "MSRValue": "0x23C000004", 1021 "SampleAfterValue": "100003", 1022 "UMask": "0x1" 1023 }, 1024 { 1025 "BriefDescription": "Counts all demand code reads", 1026 "Counter": "0,1,2,3", 1027 "EventCode": "0xB7, 0xBB", 1028 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", 1029 "MSRIndex": "0x1a6,0x1a7", 1030 "MSRValue": "0xBC000004", 1031 "SampleAfterValue": "100003", 1032 "UMask": "0x1" 1033 }, 1034 { 1035 "BriefDescription": "Counts all demand code reads", 1036 "Counter": "0,1,2,3", 1037 "EventCode": "0xB7, 0xBB", 1038 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED", 1039 "MSRIndex": "0x1a6,0x1a7", 1040 "MSRValue": "0x13C000004", 1041 "SampleAfterValue": "100003", 1042 "UMask": "0x1" 1043 }, 1044 { 1045 "BriefDescription": "Counts all demand code reads", 1046 "Counter": "0,1,2,3", 1047 "EventCode": "0xB7, 0xBB", 1048 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1049 "MSRIndex": "0x1a6,0x1a7", 1050 "MSRValue": "0x3F84000004", 1051 "SampleAfterValue": "100003", 1052 "UMask": "0x1" 1053 }, 1054 { 1055 "BriefDescription": "Counts all demand code reads", 1056 "Counter": "0,1,2,3", 1057 "EventCode": "0xB7, 0xBB", 1058 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 1059 "MSRIndex": "0x1a6,0x1a7", 1060 "MSRValue": "0x1004000004", 1061 "SampleAfterValue": "100003", 1062 "UMask": "0x1" 1063 }, 1064 { 1065 "BriefDescription": "Counts all demand code reads", 1066 "Counter": "0,1,2,3", 1067 "EventCode": "0xB7, 0xBB", 1068 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 1069 "MSRIndex": "0x1a6,0x1a7", 1070 "MSRValue": "0x404000004", 1071 "SampleAfterValue": "100003", 1072 "UMask": "0x1" 1073 }, 1074 { 1075 "BriefDescription": "Counts all demand code reads", 1076 "Counter": "0,1,2,3", 1077 "EventCode": "0xB7, 0xBB", 1078 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1079 "MSRIndex": "0x1a6,0x1a7", 1080 "MSRValue": "0x204000004", 1081 "SampleAfterValue": "100003", 1082 "UMask": "0x1" 1083 }, 1084 { 1085 "BriefDescription": "Counts all demand code reads", 1086 "Counter": "0,1,2,3", 1087 "EventCode": "0xB7, 0xBB", 1088 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1089 "MSRIndex": "0x1a6,0x1a7", 1090 "MSRValue": "0x84000004", 1091 "SampleAfterValue": "100003", 1092 "UMask": "0x1" 1093 }, 1094 { 1095 "BriefDescription": "Counts all demand code reads", 1096 "Counter": "0,1,2,3", 1097 "EventCode": "0xB7, 0xBB", 1098 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 1099 "MSRIndex": "0x1a6,0x1a7", 1100 "MSRValue": "0x2004000004", 1101 "SampleAfterValue": "100003", 1102 "UMask": "0x1" 1103 }, 1104 { 1105 "BriefDescription": "Counts all demand code reads", 1106 "Counter": "0,1,2,3", 1107 "EventCode": "0xB7, 0xBB", 1108 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 1109 "MSRIndex": "0x1a6,0x1a7", 1110 "MSRValue": "0x104000004", 1111 "SampleAfterValue": "100003", 1112 "UMask": "0x1" 1113 }, 1114 { 1115 "BriefDescription": "Counts all demand code reads", 1116 "Counter": "0,1,2,3", 1117 "EventCode": "0xB7, 0xBB", 1118 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", 1119 "MSRIndex": "0x1a6,0x1a7", 1120 "MSRValue": "0x2000020004", 1121 "SampleAfterValue": "100003", 1122 "UMask": "0x1" 1123 }, 1124 { 1125 "BriefDescription": "Counts demand data reads", 1126 "Counter": "0,1,2,3", 1127 "EventCode": "0xB7, 0xBB", 1128 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NON_DRAM", 1129 "MSRIndex": "0x1a6,0x1a7", 1130 "MSRValue": "0x20003C0001", 1131 "SampleAfterValue": "100003", 1132 "UMask": "0x1" 1133 }, 1134 { 1135 "BriefDescription": "Counts demand data reads", 1136 "Counter": "0,1,2,3", 1137 "EventCode": "0xB7, 0xBB", 1138 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", 1139 "MSRIndex": "0x1a6,0x1a7", 1140 "MSRValue": "0x43C000001", 1141 "SampleAfterValue": "100003", 1142 "UMask": "0x1" 1143 }, 1144 { 1145 "BriefDescription": "Counts demand data reads", 1146 "Counter": "0,1,2,3", 1147 "EventCode": "0xB7, 0xBB", 1148 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", 1149 "MSRIndex": "0x1a6,0x1a7", 1150 "MSRValue": "0x23C000001", 1151 "SampleAfterValue": "100003", 1152 "UMask": "0x1" 1153 }, 1154 { 1155 "BriefDescription": "Counts demand data reads", 1156 "Counter": "0,1,2,3", 1157 "EventCode": "0xB7, 0xBB", 1158 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", 1159 "MSRIndex": "0x1a6,0x1a7", 1160 "MSRValue": "0xBC000001", 1161 "SampleAfterValue": "100003", 1162 "UMask": "0x1" 1163 }, 1164 { 1165 "BriefDescription": "Counts demand data reads", 1166 "Counter": "0,1,2,3", 1167 "EventCode": "0xB7, 0xBB", 1168 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED", 1169 "MSRIndex": "0x1a6,0x1a7", 1170 "MSRValue": "0x13C000001", 1171 "SampleAfterValue": "100003", 1172 "UMask": "0x1" 1173 }, 1174 { 1175 "BriefDescription": "Counts demand data reads", 1176 "Counter": "0,1,2,3", 1177 "EventCode": "0xB7, 0xBB", 1178 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1179 "MSRIndex": "0x1a6,0x1a7", 1180 "MSRValue": "0x3F84000001", 1181 "SampleAfterValue": "100003", 1182 "UMask": "0x1" 1183 }, 1184 { 1185 "BriefDescription": "Counts demand data reads", 1186 "Counter": "0,1,2,3", 1187 "EventCode": "0xB7, 0xBB", 1188 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 1189 "MSRIndex": "0x1a6,0x1a7", 1190 "MSRValue": "0x1004000001", 1191 "SampleAfterValue": "100003", 1192 "UMask": "0x1" 1193 }, 1194 { 1195 "BriefDescription": "Counts demand data reads", 1196 "Counter": "0,1,2,3", 1197 "EventCode": "0xB7, 0xBB", 1198 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 1199 "MSRIndex": "0x1a6,0x1a7", 1200 "MSRValue": "0x404000001", 1201 "SampleAfterValue": "100003", 1202 "UMask": "0x1" 1203 }, 1204 { 1205 "BriefDescription": "Counts demand data reads", 1206 "Counter": "0,1,2,3", 1207 "EventCode": "0xB7, 0xBB", 1208 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1209 "MSRIndex": "0x1a6,0x1a7", 1210 "MSRValue": "0x204000001", 1211 "SampleAfterValue": "100003", 1212 "UMask": "0x1" 1213 }, 1214 { 1215 "BriefDescription": "Counts demand data reads", 1216 "Counter": "0,1,2,3", 1217 "EventCode": "0xB7, 0xBB", 1218 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1219 "MSRIndex": "0x1a6,0x1a7", 1220 "MSRValue": "0x84000001", 1221 "SampleAfterValue": "100003", 1222 "UMask": "0x1" 1223 }, 1224 { 1225 "BriefDescription": "Counts demand data reads", 1226 "Counter": "0,1,2,3", 1227 "EventCode": "0xB7, 0xBB", 1228 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 1229 "MSRIndex": "0x1a6,0x1a7", 1230 "MSRValue": "0x2004000001", 1231 "SampleAfterValue": "100003", 1232 "UMask": "0x1" 1233 }, 1234 { 1235 "BriefDescription": "Counts demand data reads", 1236 "Counter": "0,1,2,3", 1237 "EventCode": "0xB7, 0xBB", 1238 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 1239 "MSRIndex": "0x1a6,0x1a7", 1240 "MSRValue": "0x104000001", 1241 "SampleAfterValue": "100003", 1242 "UMask": "0x1" 1243 }, 1244 { 1245 "BriefDescription": "Counts demand data reads", 1246 "Counter": "0,1,2,3", 1247 "EventCode": "0xB7, 0xBB", 1248 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", 1249 "MSRIndex": "0x1a6,0x1a7", 1250 "MSRValue": "0x2000020001", 1251 "SampleAfterValue": "100003", 1252 "UMask": "0x1" 1253 }, 1254 { 1255 "BriefDescription": "Counts all demand data writes (RFOs)", 1256 "Counter": "0,1,2,3", 1257 "EventCode": "0xB7, 0xBB", 1258 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NON_DRAM", 1259 "MSRIndex": "0x1a6,0x1a7", 1260 "MSRValue": "0x20003C0002", 1261 "SampleAfterValue": "100003", 1262 "UMask": "0x1" 1263 }, 1264 { 1265 "BriefDescription": "Counts all demand data writes (RFOs)", 1266 "Counter": "0,1,2,3", 1267 "EventCode": "0xB7, 0xBB", 1268 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HIT_NO_FWD", 1269 "MSRIndex": "0x1a6,0x1a7", 1270 "MSRValue": "0x43C000002", 1271 "SampleAfterValue": "100003", 1272 "UMask": "0x1" 1273 }, 1274 { 1275 "BriefDescription": "Counts all demand data writes (RFOs)", 1276 "Counter": "0,1,2,3", 1277 "EventCode": "0xB7, 0xBB", 1278 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS", 1279 "MSRIndex": "0x1a6,0x1a7", 1280 "MSRValue": "0x23C000002", 1281 "SampleAfterValue": "100003", 1282 "UMask": "0x1" 1283 }, 1284 { 1285 "BriefDescription": "Counts all demand data writes (RFOs)", 1286 "Counter": "0,1,2,3", 1287 "EventCode": "0xB7, 0xBB", 1288 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE", 1289 "MSRIndex": "0x1a6,0x1a7", 1290 "MSRValue": "0xBC000002", 1291 "SampleAfterValue": "100003", 1292 "UMask": "0x1" 1293 }, 1294 { 1295 "BriefDescription": "Counts all demand data writes (RFOs)", 1296 "Counter": "0,1,2,3", 1297 "EventCode": "0xB7, 0xBB", 1298 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NOT_NEEDED", 1299 "MSRIndex": "0x1a6,0x1a7", 1300 "MSRValue": "0x13C000002", 1301 "SampleAfterValue": "100003", 1302 "UMask": "0x1" 1303 }, 1304 { 1305 "BriefDescription": "Counts all demand data writes (RFOs)", 1306 "Counter": "0,1,2,3", 1307 "EventCode": "0xB7, 0xBB", 1308 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1309 "MSRIndex": "0x1a6,0x1a7", 1310 "MSRValue": "0x3F84000002", 1311 "SampleAfterValue": "100003", 1312 "UMask": "0x1" 1313 }, 1314 { 1315 "BriefDescription": "Counts any other requests", 1316 "Counter": "0,1,2,3", 1317 "EventCode": "0xB7, 0xBB", 1318 "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NON_DRAM", 1319 "MSRIndex": "0x1a6,0x1a7", 1320 "MSRValue": "0x20003C8000", 1321 "SampleAfterValue": "100003", 1322 "UMask": "0x1" 1323 }, 1324 { 1325 "BriefDescription": "Counts any other requests", 1326 "Counter": "0,1,2,3", 1327 "EventCode": "0xB7, 0xBB", 1328 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD", 1329 "MSRIndex": "0x1a6,0x1a7", 1330 "MSRValue": "0x43C008000", 1331 "SampleAfterValue": "100003", 1332 "UMask": "0x1" 1333 }, 1334 { 1335 "BriefDescription": "Counts any other requests", 1336 "Counter": "0,1,2,3", 1337 "EventCode": "0xB7, 0xBB", 1338 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS", 1339 "MSRIndex": "0x1a6,0x1a7", 1340 "MSRValue": "0x23C008000", 1341 "SampleAfterValue": "100003", 1342 "UMask": "0x1" 1343 }, 1344 { 1345 "BriefDescription": "Counts any other requests", 1346 "Counter": "0,1,2,3", 1347 "EventCode": "0xB7, 0xBB", 1348 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE", 1349 "MSRIndex": "0x1a6,0x1a7", 1350 "MSRValue": "0xBC008000", 1351 "SampleAfterValue": "100003", 1352 "UMask": "0x1" 1353 }, 1354 { 1355 "BriefDescription": "Counts any other requests", 1356 "Counter": "0,1,2,3", 1357 "EventCode": "0xB7, 0xBB", 1358 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED", 1359 "MSRIndex": "0x1a6,0x1a7", 1360 "MSRValue": "0x13C008000", 1361 "SampleAfterValue": "100003", 1362 "UMask": "0x1" 1363 }, 1364 { 1365 "BriefDescription": "Counts any other requests", 1366 "Counter": "0,1,2,3", 1367 "EventCode": "0xB7, 0xBB", 1368 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1369 "MSRIndex": "0x1a6,0x1a7", 1370 "MSRValue": "0x3F84008000", 1371 "SampleAfterValue": "100003", 1372 "UMask": "0x1" 1373 }, 1374 { 1375 "BriefDescription": "Counts any other requests", 1376 "Counter": "0,1,2,3", 1377 "EventCode": "0xB7, 0xBB", 1378 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 1379 "MSRIndex": "0x1a6,0x1a7", 1380 "MSRValue": "0x1004008000", 1381 "SampleAfterValue": "100003", 1382 "UMask": "0x1" 1383 }, 1384 { 1385 "BriefDescription": "Counts any other requests", 1386 "Counter": "0,1,2,3", 1387 "EventCode": "0xB7, 0xBB", 1388 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 1389 "MSRIndex": "0x1a6,0x1a7", 1390 "MSRValue": "0x404008000", 1391 "SampleAfterValue": "100003", 1392 "UMask": "0x1" 1393 }, 1394 { 1395 "BriefDescription": "Counts any other requests", 1396 "Counter": "0,1,2,3", 1397 "EventCode": "0xB7, 0xBB", 1398 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1399 "MSRIndex": "0x1a6,0x1a7", 1400 "MSRValue": "0x204008000", 1401 "SampleAfterValue": "100003", 1402 "UMask": "0x1" 1403 }, 1404 { 1405 "BriefDescription": "Counts any other requests", 1406 "Counter": "0,1,2,3", 1407 "EventCode": "0xB7, 0xBB", 1408 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1409 "MSRIndex": "0x1a6,0x1a7", 1410 "MSRValue": "0x84008000", 1411 "SampleAfterValue": "100003", 1412 "UMask": "0x1" 1413 }, 1414 { 1415 "BriefDescription": "Counts any other requests", 1416 "Counter": "0,1,2,3", 1417 "EventCode": "0xB7, 0xBB", 1418 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 1419 "MSRIndex": "0x1a6,0x1a7", 1420 "MSRValue": "0x2004008000", 1421 "SampleAfterValue": "100003", 1422 "UMask": "0x1" 1423 }, 1424 { 1425 "BriefDescription": "Counts any other requests", 1426 "Counter": "0,1,2,3", 1427 "EventCode": "0xB7, 0xBB", 1428 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 1429 "MSRIndex": "0x1a6,0x1a7", 1430 "MSRValue": "0x104008000", 1431 "SampleAfterValue": "100003", 1432 "UMask": "0x1" 1433 }, 1434 { 1435 "BriefDescription": "Counts any other requests", 1436 "Counter": "0,1,2,3", 1437 "EventCode": "0xB7, 0xBB", 1438 "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NON_DRAM", 1439 "MSRIndex": "0x1a6,0x1a7", 1440 "MSRValue": "0x2000028000", 1441 "SampleAfterValue": "100003", 1442 "UMask": "0x1" 1443 }, 1444 { 1445 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", 1446 "Counter": "0,1,2,3", 1447 "EventCode": "0xB7, 0xBB", 1448 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_NON_DRAM", 1449 "MSRIndex": "0x1a6,0x1a7", 1450 "MSRValue": "0x20003C0040", 1451 "SampleAfterValue": "100003", 1452 "UMask": "0x1" 1453 }, 1454 { 1455 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", 1456 "Counter": "0,1,2,3", 1457 "EventCode": "0xB7, 0xBB", 1458 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD", 1459 "MSRIndex": "0x1a6,0x1a7", 1460 "MSRValue": "0x43C000040", 1461 "SampleAfterValue": "100003", 1462 "UMask": "0x1" 1463 }, 1464 { 1465 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", 1466 "Counter": "0,1,2,3", 1467 "EventCode": "0xB7, 0xBB", 1468 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_MISS", 1469 "MSRIndex": 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"OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1499 "MSRIndex": "0x1a6,0x1a7", 1500 "MSRValue": "0x3F84000040", 1501 "SampleAfterValue": "100003", 1502 "UMask": "0x1" 1503 }, 1504 { 1505 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", 1506 "Counter": "0,1,2,3", 1507 "EventCode": "0xB7, 0xBB", 1508 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 1509 "MSRIndex": "0x1a6,0x1a7", 1510 "MSRValue": "0x1004000040", 1511 "SampleAfterValue": "100003", 1512 "UMask": "0x1" 1513 }, 1514 { 1515 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", 1516 "Counter": "0,1,2,3", 1517 "EventCode": "0xB7, 0xBB", 1518 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 1519 "MSRIndex": "0x1a6,0x1a7", 1520 "MSRValue": "0x404000040", 1521 "SampleAfterValue": "100003", 1522 "UMask": "0x1" 1523 }, 1524 { 1525 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", 1526 "Counter": "0,1,2,3", 1527 "EventCode": "0xB7, 0xBB", 1528 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1529 "MSRIndex": "0x1a6,0x1a7", 1530 "MSRValue": "0x204000040", 1531 "SampleAfterValue": "100003", 1532 "UMask": "0x1" 1533 }, 1534 { 1535 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", 1536 "Counter": "0,1,2,3", 1537 "EventCode": "0xB7, 0xBB", 1538 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1539 "MSRIndex": "0x1a6,0x1a7", 1540 "MSRValue": "0x84000040", 1541 "SampleAfterValue": "100003", 1542 "UMask": "0x1" 1543 }, 1544 { 1545 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", 1546 "Counter": "0,1,2,3", 1547 "EventCode": "0xB7, 0xBB", 1548 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 1549 "MSRIndex": "0x1a6,0x1a7", 1550 "MSRValue": "0x2004000040", 1551 "SampleAfterValue": "100003", 1552 "UMask": "0x1" 1553 }, 1554 { 1555 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", 1556 "Counter": "0,1,2,3", 1557 "EventCode": "0xB7, 0xBB", 1558 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 1559 "MSRIndex": "0x1a6,0x1a7", 1560 "MSRValue": "0x104000040", 1561 "SampleAfterValue": "100003", 1562 "UMask": "0x1" 1563 }, 1564 { 1565 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", 1566 "Counter": "0,1,2,3", 1567 "EventCode": "0xB7, 0xBB", 1568 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", 1569 "MSRIndex": "0x1a6,0x1a7", 1570 "MSRValue": "0x2000020040", 1571 "SampleAfterValue": "100003", 1572 "UMask": "0x1" 1573 }, 1574 { 1575 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1576 "Counter": "0,1,2,3", 1577 "EventCode": "0xB7, 0xBB", 1578 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NON_DRAM", 1579 "MSRIndex": "0x1a6,0x1a7", 1580 "MSRValue": "0x20003C0010", 1581 "SampleAfterValue": "100003", 1582 "UMask": "0x1" 1583 }, 1584 { 1585 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1586 "Counter": "0,1,2,3", 1587 "EventCode": "0xB7, 0xBB", 1588 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", 1589 "MSRIndex": "0x1a6,0x1a7", 1590 "MSRValue": "0x43C000010", 1591 "SampleAfterValue": "100003", 1592 "UMask": "0x1" 1593 }, 1594 { 1595 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1596 "Counter": "0,1,2,3", 1597 "EventCode": "0xB7, 0xBB", 1598 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS", 1599 "MSRIndex": "0x1a6,0x1a7", 1600 "MSRValue": "0x23C000010", 1601 "SampleAfterValue": "100003", 1602 "UMask": "0x1" 1603 }, 1604 { 1605 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1606 "Counter": "0,1,2,3", 1607 "EventCode": "0xB7, 0xBB", 1608 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE", 1609 "MSRIndex": "0x1a6,0x1a7", 1610 "MSRValue": "0xBC000010", 1611 "SampleAfterValue": "100003", 1612 "UMask": "0x1" 1613 }, 1614 { 1615 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1616 "Counter": "0,1,2,3", 1617 "EventCode": "0xB7, 0xBB", 1618 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED", 1619 "MSRIndex": "0x1a6,0x1a7", 1620 "MSRValue": "0x13C000010", 1621 "SampleAfterValue": "100003", 1622 "UMask": "0x1" 1623 }, 1624 { 1625 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1626 "Counter": "0,1,2,3", 1627 "EventCode": "0xB7, 0xBB", 1628 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1629 "MSRIndex": "0x1a6,0x1a7", 1630 "MSRValue": "0x3F84000010", 1631 "SampleAfterValue": "100003", 1632 "UMask": "0x1" 1633 }, 1634 { 1635 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1636 "Counter": "0,1,2,3", 1637 "EventCode": "0xB7, 0xBB", 1638 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 1639 "MSRIndex": "0x1a6,0x1a7", 1640 "MSRValue": "0x1004000010", 1641 "SampleAfterValue": "100003", 1642 "UMask": "0x1" 1643 }, 1644 { 1645 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1646 "Counter": "0,1,2,3", 1647 "EventCode": "0xB7, 0xBB", 1648 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 1649 "MSRIndex": "0x1a6,0x1a7", 1650 "MSRValue": "0x404000010", 1651 "SampleAfterValue": "100003", 1652 "UMask": "0x1" 1653 }, 1654 { 1655 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1656 "Counter": "0,1,2,3", 1657 "EventCode": "0xB7, 0xBB", 1658 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1659 "MSRIndex": "0x1a6,0x1a7", 1660 "MSRValue": "0x204000010", 1661 "SampleAfterValue": "100003", 1662 "UMask": "0x1" 1663 }, 1664 { 1665 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1666 "Counter": "0,1,2,3", 1667 "EventCode": "0xB7, 0xBB", 1668 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1669 "MSRIndex": "0x1a6,0x1a7", 1670 "MSRValue": "0x84000010", 1671 "SampleAfterValue": "100003", 1672 "UMask": "0x1" 1673 }, 1674 { 1675 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1676 "Counter": "0,1,2,3", 1677 "EventCode": "0xB7, 0xBB", 1678 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 1679 "MSRIndex": "0x1a6,0x1a7", 1680 "MSRValue": "0x2004000010", 1681 "SampleAfterValue": "100003", 1682 "UMask": "0x1" 1683 }, 1684 { 1685 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1686 "Counter": "0,1,2,3", 1687 "EventCode": "0xB7, 0xBB", 1688 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 1689 "MSRIndex": "0x1a6,0x1a7", 1690 "MSRValue": "0x104000010", 1691 "SampleAfterValue": "100003", 1692 "UMask": "0x1" 1693 }, 1694 { 1695 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 1696 "Counter": "0,1,2,3", 1697 "EventCode": "0xB7, 0xBB", 1698 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", 1699 "MSRIndex": "0x1a6,0x1a7", 1700 "MSRValue": "0x2000020010", 1701 "SampleAfterValue": "100003", 1702 "UMask": "0x1" 1703 }, 1704 { 1705 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 1706 "Counter": "0,1,2,3", 1707 "EventCode": "0xB7, 0xBB", 1708 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NON_DRAM", 1709 "MSRIndex": "0x1a6,0x1a7", 1710 "MSRValue": "0x20003C0020", 1711 "SampleAfterValue": "100003", 1712 "UMask": "0x1" 1713 }, 1714 { 1715 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 1716 "Counter": "0,1,2,3", 1717 "EventCode": "0xB7, 0xBB", 1718 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_HIT_NO_FWD", 1719 "MSRIndex": "0x1a6,0x1a7", 1720 "MSRValue": "0x43C000020", 1721 "SampleAfterValue": "100003", 1722 "UMask": "0x1" 1723 }, 1724 { 1725 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 1726 "Counter": "0,1,2,3", 1727 "EventCode": "0xB7, 0xBB", 1728 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS", 1729 "MSRIndex": "0x1a6,0x1a7", 1730 "MSRValue": "0x23C000020", 1731 "SampleAfterValue": "100003", 1732 "UMask": "0x1" 1733 }, 1734 { 1735 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 1736 "Counter": "0,1,2,3", 1737 "EventCode": "0xB7, 0xBB", 1738 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_NONE", 1739 "MSRIndex": "0x1a6,0x1a7", 1740 "MSRValue": "0xBC000020", 1741 "SampleAfterValue": "100003", 1742 "UMask": "0x1" 1743 }, 1744 { 1745 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 1746 "Counter": "0,1,2,3", 1747 "EventCode": "0xB7, 0xBB", 1748 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_NOT_NEEDED", 1749 "MSRIndex": "0x1a6,0x1a7", 1750 "MSRValue": "0x13C000020", 1751 "SampleAfterValue": "100003", 1752 "UMask": "0x1" 1753 }, 1754 { 1755 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 1756 "Counter": "0,1,2,3", 1757 "EventCode": "0xB7, 0xBB", 1758 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1759 "MSRIndex": "0x1a6,0x1a7", 1760 "MSRValue": "0x3F84000020", 1761 "SampleAfterValue": "100003", 1762 "UMask": "0x1" 1763 }, 1764 { 1765 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 1766 "Counter": "0,1,2,3", 1767 "EventCode": "0xB7, 0xBB", 1768 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 1769 "MSRIndex": "0x1a6,0x1a7", 1770 "MSRValue": "0x1004000020", 1771 "SampleAfterValue": "100003", 1772 "UMask": "0x1" 1773 }, 1774 { 1775 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 1776 "Counter": "0,1,2,3", 1777 "EventCode": "0xB7, 0xBB", 1778 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 1779 "MSRIndex": "0x1a6,0x1a7", 1780 "MSRValue": "0x404000020", 1781 "SampleAfterValue": "100003", 1782 "UMask": "0x1" 1783 }, 1784 { 1785 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 1786 "Counter": "0,1,2,3", 1787 "EventCode": "0xB7, 0xBB", 1788 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1789 "MSRIndex": "0x1a6,0x1a7", 1790 "MSRValue": "0x204000020", 1791 "SampleAfterValue": "100003", 1792 "UMask": "0x1" 1793 }, 1794 { 1795 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 1796 "Counter": "0,1,2,3", 1797 "EventCode": "0xB7, 0xBB", 1798 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1799 "MSRIndex": "0x1a6,0x1a7", 1800 "MSRValue": "0x84000020", 1801 "SampleAfterValue": "100003", 1802 "UMask": "0x1" 1803 }, 1804 { 1805 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 1806 "Counter": "0,1,2,3", 1807 "EventCode": "0xB7, 0xBB", 1808 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 1809 "MSRIndex": "0x1a6,0x1a7", 1810 "MSRValue": "0x2004000020", 1811 "SampleAfterValue": "100003", 1812 "UMask": "0x1" 1813 }, 1814 { 1815 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 1816 "Counter": "0,1,2,3", 1817 "EventCode": "0xB7, 0xBB", 1818 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 1819 "MSRIndex": "0x1a6,0x1a7", 1820 "MSRValue": "0x104000020", 1821 "SampleAfterValue": "100003", 1822 "UMask": "0x1" 1823 }, 1824 { 1825 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 1826 "Counter": "0,1,2,3", 1827 "EventCode": "0xB7, 0xBB", 1828 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM", 1829 "MSRIndex": "0x1a6,0x1a7", 1830 "MSRValue": "0x2000020020", 1831 "SampleAfterValue": "100003", 1832 "UMask": "0x1" 1833 }, 1834 { 1835 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", 1836 "Counter": "0,1,2,3", 1837 "EventCode": "0xB7, 0xBB", 1838 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NON_DRAM", 1839 "MSRIndex": "0x1a6,0x1a7", 1840 "MSRValue": "0x20003C0200", 1841 "SampleAfterValue": "100003", 1842 "UMask": "0x1" 1843 }, 1844 { 1845 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", 1846 "Counter": "0,1,2,3", 1847 "EventCode": "0xB7, 0xBB", 1848 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD", 1849 "MSRIndex": "0x1a6,0x1a7", 1850 "MSRValue": "0x43C000200", 1851 "SampleAfterValue": "100003", 1852 "UMask": "0x1" 1853 }, 1854 { 1855 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", 1856 "Counter": "0,1,2,3", 1857 "EventCode": "0xB7, 0xBB", 1858 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_MISS", 1859 "MSRIndex": "0x1a6,0x1a7", 1860 "MSRValue": "0x23C000200", 1861 "SampleAfterValue": "100003", 1862 "UMask": "0x1" 1863 }, 1864 { 1865 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", 1866 "Counter": "0,1,2,3", 1867 "EventCode": "0xB7, 0xBB", 1868 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_NONE", 1869 "MSRIndex": "0x1a6,0x1a7", 1870 "MSRValue": "0xBC000200", 1871 "SampleAfterValue": "100003", 1872 "UMask": "0x1" 1873 }, 1874 { 1875 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", 1876 "Counter": "0,1,2,3", 1877 "EventCode": "0xB7, 0xBB", 1878 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED", 1879 "MSRIndex": "0x1a6,0x1a7", 1880 "MSRValue": "0x13C000200", 1881 "SampleAfterValue": "100003", 1882 "UMask": "0x1" 1883 }, 1884 { 1885 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", 1886 "Counter": "0,1,2,3", 1887 "EventCode": "0xB7, 0xBB", 1888 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1889 "MSRIndex": "0x1a6,0x1a7", 1890 "MSRValue": "0x3F84000200", 1891 "SampleAfterValue": "100003", 1892 "UMask": "0x1" 1893 }, 1894 { 1895 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", 1896 "Counter": "0,1,2,3", 1897 "EventCode": "0xB7, 0xBB", 1898 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 1899 "MSRIndex": "0x1a6,0x1a7", 1900 "MSRValue": "0x1004000200", 1901 "SampleAfterValue": "100003", 1902 "UMask": "0x1" 1903 }, 1904 { 1905 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", 1906 "Counter": "0,1,2,3", 1907 "EventCode": "0xB7, 0xBB", 1908 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 1909 "MSRIndex": "0x1a6,0x1a7", 1910 "MSRValue": "0x404000200", 1911 "SampleAfterValue": "100003", 1912 "UMask": "0x1" 1913 }, 1914 { 1915 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", 1916 "Counter": "0,1,2,3", 1917 "EventCode": "0xB7, 0xBB", 1918 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1919 "MSRIndex": "0x1a6,0x1a7", 1920 "MSRValue": "0x204000200", 1921 "SampleAfterValue": "100003", 1922 "UMask": "0x1" 1923 }, 1924 { 1925 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", 1926 "Counter": "0,1,2,3", 1927 "EventCode": "0xB7, 0xBB", 1928 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1929 "MSRIndex": "0x1a6,0x1a7", 1930 "MSRValue": "0x84000200", 1931 "SampleAfterValue": "100003", 1932 "UMask": "0x1" 1933 }, 1934 { 1935 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", 1936 "Counter": "0,1,2,3", 1937 "EventCode": "0xB7, 0xBB", 1938 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 1939 "MSRIndex": "0x1a6,0x1a7", 1940 "MSRValue": "0x2004000200", 1941 "SampleAfterValue": "100003", 1942 "UMask": "0x1" 1943 }, 1944 { 1945 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", 1946 "Counter": "0,1,2,3", 1947 "EventCode": "0xB7, 0xBB", 1948 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 1949 "MSRIndex": "0x1a6,0x1a7", 1950 "MSRValue": "0x104000200", 1951 "SampleAfterValue": "100003", 1952 "UMask": "0x1" 1953 }, 1954 { 1955 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", 1956 "Counter": "0,1,2,3", 1957 "EventCode": "0xB7, 0xBB", 1958 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", 1959 "MSRIndex": "0x1a6,0x1a7", 1960 "MSRValue": "0x2000020200", 1961 "SampleAfterValue": "100003", 1962 "UMask": "0x1" 1963 }, 1964 { 1965 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 1966 "Counter": "0,1,2,3", 1967 "EventCode": "0xB7, 0xBB", 1968 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NON_DRAM", 1969 "MSRIndex": "0x1a6,0x1a7", 1970 "MSRValue": "0x20003C0080", 1971 "SampleAfterValue": "100003", 1972 "UMask": "0x1" 1973 }, 1974 { 1975 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 1976 "Counter": "0,1,2,3", 1977 "EventCode": "0xB7, 0xBB", 1978 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", 1979 "MSRIndex": "0x1a6,0x1a7", 1980 "MSRValue": "0x43C000080", 1981 "SampleAfterValue": "100003", 1982 "UMask": "0x1" 1983 }, 1984 { 1985 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 1986 "Counter": "0,1,2,3", 1987 "EventCode": "0xB7, 0xBB", 1988 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", 1989 "MSRIndex": "0x1a6,0x1a7", 1990 "MSRValue": "0x23C000080", 1991 "SampleAfterValue": "100003", 1992 "UMask": "0x1" 1993 }, 1994 { 1995 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 1996 "Counter": "0,1,2,3", 1997 "EventCode": "0xB7, 0xBB", 1998 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", 1999 "MSRIndex": "0x1a6,0x1a7", 2000 "MSRValue": "0xBC000080", 2001 "SampleAfterValue": "100003", 2002 "UMask": "0x1" 2003 }, 2004 { 2005 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2006 "Counter": "0,1,2,3", 2007 "EventCode": "0xB7, 0xBB", 2008 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED", 2009 "MSRIndex": "0x1a6,0x1a7", 2010 "MSRValue": "0x13C000080", 2011 "SampleAfterValue": "100003", 2012 "UMask": "0x1" 2013 }, 2014 { 2015 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2016 "Counter": "0,1,2,3", 2017 "EventCode": "0xB7, 0xBB", 2018 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 2019 "MSRIndex": "0x1a6,0x1a7", 2020 "MSRValue": "0x3F84000080", 2021 "SampleAfterValue": "100003", 2022 "UMask": "0x1" 2023 }, 2024 { 2025 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2026 "Counter": "0,1,2,3", 2027 "EventCode": "0xB7, 0xBB", 2028 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 2029 "MSRIndex": "0x1a6,0x1a7", 2030 "MSRValue": "0x1004000080", 2031 "SampleAfterValue": "100003", 2032 "UMask": "0x1" 2033 }, 2034 { 2035 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2036 "Counter": "0,1,2,3", 2037 "EventCode": "0xB7, 0xBB", 2038 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 2039 "MSRIndex": "0x1a6,0x1a7", 2040 "MSRValue": "0x404000080", 2041 "SampleAfterValue": "100003", 2042 "UMask": "0x1" 2043 }, 2044 { 2045 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2046 "Counter": "0,1,2,3", 2047 "EventCode": "0xB7, 0xBB", 2048 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 2049 "MSRIndex": "0x1a6,0x1a7", 2050 "MSRValue": "0x204000080", 2051 "SampleAfterValue": "100003", 2052 "UMask": "0x1" 2053 }, 2054 { 2055 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2056 "Counter": "0,1,2,3", 2057 "EventCode": "0xB7, 0xBB", 2058 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 2059 "MSRIndex": "0x1a6,0x1a7", 2060 "MSRValue": "0x84000080", 2061 "SampleAfterValue": "100003", 2062 "UMask": "0x1" 2063 }, 2064 { 2065 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2066 "Counter": "0,1,2,3", 2067 "EventCode": "0xB7, 0xBB", 2068 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 2069 "MSRIndex": "0x1a6,0x1a7", 2070 "MSRValue": "0x2004000080", 2071 "SampleAfterValue": "100003", 2072 "UMask": "0x1" 2073 }, 2074 { 2075 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2076 "Counter": "0,1,2,3", 2077 "EventCode": "0xB7, 0xBB", 2078 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 2079 "MSRIndex": "0x1a6,0x1a7", 2080 "MSRValue": "0x104000080", 2081 "SampleAfterValue": "100003", 2082 "UMask": "0x1" 2083 }, 2084 { 2085 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 2086 "Counter": "0,1,2,3", 2087 "EventCode": "0xB7, 0xBB", 2088 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", 2089 "MSRIndex": "0x1a6,0x1a7", 2090 "MSRValue": "0x2000020080", 2091 "SampleAfterValue": "100003", 2092 "UMask": "0x1" 2093 }, 2094 { 2095 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2096 "Counter": "0,1,2,3", 2097 "EventCode": "0xB7, 0xBB", 2098 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NON_DRAM", 2099 "MSRIndex": "0x1a6,0x1a7", 2100 "MSRValue": "0x20003C0100", 2101 "SampleAfterValue": "100003", 2102 "UMask": "0x1" 2103 }, 2104 { 2105 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2106 "Counter": "0,1,2,3", 2107 "EventCode": "0xB7, 0xBB", 2108 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_HIT_NO_FWD", 2109 "MSRIndex": "0x1a6,0x1a7", 2110 "MSRValue": "0x43C000100", 2111 "SampleAfterValue": "100003", 2112 "UMask": "0x1" 2113 }, 2114 { 2115 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2116 "Counter": "0,1,2,3", 2117 "EventCode": "0xB7, 0xBB", 2118 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS", 2119 "MSRIndex": "0x1a6,0x1a7", 2120 "MSRValue": "0x23C000100", 2121 "SampleAfterValue": "100003", 2122 "UMask": "0x1" 2123 }, 2124 { 2125 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2126 "Counter": "0,1,2,3", 2127 "EventCode": "0xB7, 0xBB", 2128 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NONE", 2129 "MSRIndex": "0x1a6,0x1a7", 2130 "MSRValue": "0xBC000100", 2131 "SampleAfterValue": "100003", 2132 "UMask": "0x1" 2133 }, 2134 { 2135 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2136 "Counter": "0,1,2,3", 2137 "EventCode": "0xB7, 0xBB", 2138 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NOT_NEEDED", 2139 "MSRIndex": "0x1a6,0x1a7", 2140 "MSRValue": "0x13C000100", 2141 "SampleAfterValue": "100003", 2142 "UMask": "0x1" 2143 }, 2144 { 2145 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2146 "Counter": "0,1,2,3", 2147 "EventCode": "0xB7, 0xBB", 2148 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 2149 "MSRIndex": "0x1a6,0x1a7", 2150 "MSRValue": "0x3F84000100", 2151 "SampleAfterValue": "100003", 2152 "UMask": "0x1" 2153 }, 2154 { 2155 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2156 "Counter": "0,1,2,3", 2157 "EventCode": "0xB7, 0xBB", 2158 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 2159 "MSRIndex": "0x1a6,0x1a7", 2160 "MSRValue": "0x1004000100", 2161 "SampleAfterValue": "100003", 2162 "UMask": "0x1" 2163 }, 2164 { 2165 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2166 "Counter": "0,1,2,3", 2167 "EventCode": "0xB7, 0xBB", 2168 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 2169 "MSRIndex": "0x1a6,0x1a7", 2170 "MSRValue": "0x404000100", 2171 "SampleAfterValue": "100003", 2172 "UMask": "0x1" 2173 }, 2174 { 2175 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2176 "Counter": "0,1,2,3", 2177 "EventCode": "0xB7, 0xBB", 2178 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 2179 "MSRIndex": "0x1a6,0x1a7", 2180 "MSRValue": "0x204000100", 2181 "SampleAfterValue": "100003", 2182 "UMask": "0x1" 2183 }, 2184 { 2185 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2186 "Counter": "0,1,2,3", 2187 "EventCode": "0xB7, 0xBB", 2188 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 2189 "MSRIndex": "0x1a6,0x1a7", 2190 "MSRValue": "0x84000100", 2191 "SampleAfterValue": "100003", 2192 "UMask": "0x1" 2193 }, 2194 { 2195 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2196 "Counter": "0,1,2,3", 2197 "EventCode": "0xB7, 0xBB", 2198 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 2199 "MSRIndex": "0x1a6,0x1a7", 2200 "MSRValue": "0x2004000100", 2201 "SampleAfterValue": "100003", 2202 "UMask": "0x1" 2203 }, 2204 { 2205 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2206 "Counter": "0,1,2,3", 2207 "EventCode": "0xB7, 0xBB", 2208 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 2209 "MSRIndex": "0x1a6,0x1a7", 2210 "MSRValue": "0x104000100", 2211 "SampleAfterValue": "100003", 2212 "UMask": "0x1" 2213 }, 2214 { 2215 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 2216 "Counter": "0,1,2,3", 2217 "EventCode": "0xB7, 0xBB", 2218 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM", 2219 "MSRIndex": "0x1a6,0x1a7", 2220 "MSRValue": "0x2000020100", 2221 "SampleAfterValue": "100003", 2222 "UMask": "0x1" 2223 }, 2224 { 2225 "BriefDescription": "Number of times RTM abort was triggered", 2226 "Counter": "0,1,2,3", 2227 "EventCode": "0xc9", 2228 "EventName": "RTM_RETIRED.ABORTED", 2229 "PEBS": "1", 2230 "PublicDescription": "Number of times RTM abort was triggered .", 2231 "SampleAfterValue": "2000003", 2232 "UMask": "0x4" 2233 }, 2234 { 2235 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 2236 "Counter": "0,1,2,3", 2237 "EventCode": "0xc9", 2238 "EventName": "RTM_RETIRED.ABORTED_MISC1", 2239 "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).", 2240 "SampleAfterValue": "2000003", 2241 "UMask": "0x8" 2242 }, 2243 { 2244 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 2245 "Counter": "0,1,2,3", 2246 "EventCode": "0xc9", 2247 "EventName": "RTM_RETIRED.ABORTED_MISC2", 2248 "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.", 2249 "SampleAfterValue": "2000003", 2250 "UMask": "0x10" 2251 }, 2252 { 2253 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 2254 "Counter": "0,1,2,3", 2255 "EventCode": "0xc9", 2256 "EventName": "RTM_RETIRED.ABORTED_MISC3", 2257 "PublicDescription": "Number of times a disallowed operation caused an RTM abort.", 2258 "SampleAfterValue": "2000003", 2259 "UMask": "0x20" 2260 }, 2261 { 2262 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 2263 "Counter": "0,1,2,3", 2264 "EventCode": "0xc9", 2265 "EventName": "RTM_RETIRED.ABORTED_MISC4", 2266 "PublicDescription": "Number of times a RTM caused a fault.", 2267 "SampleAfterValue": "2000003", 2268 "UMask": "0x40" 2269 }, 2270 { 2271 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 2272 "Counter": "0,1,2,3", 2273 "EventCode": "0xc9", 2274 "EventName": "RTM_RETIRED.ABORTED_MISC5", 2275 "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.", 2276 "SampleAfterValue": "2000003", 2277 "UMask": "0x80" 2278 }, 2279 { 2280 "BriefDescription": "Number of times RTM commit succeeded", 2281 "Counter": "0,1,2,3", 2282 "EventCode": "0xc9", 2283 "EventName": "RTM_RETIRED.COMMIT", 2284 "PublicDescription": "Number of times RTM commit succeeded.", 2285 "SampleAfterValue": "2000003", 2286 "UMask": "0x2" 2287 }, 2288 { 2289 "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions", 2290 "Counter": "0,1,2,3", 2291 "EventCode": "0xc9", 2292 "EventName": "RTM_RETIRED.START", 2293 "PublicDescription": "Number of times we entered an RTM region does not count nested transactions.", 2294 "SampleAfterValue": "2000003", 2295 "UMask": "0x1" 2296 }, 2297 { 2298 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", 2299 "Counter": "0,1,2,3", 2300 "EventCode": "0x5d", 2301 "EventName": "TX_EXEC.MISC1", 2302 "SampleAfterValue": "2000003", 2303 "UMask": "0x1" 2304 }, 2305 { 2306 "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", 2307 "Counter": "0,1,2,3", 2308 "EventCode": "0x5d", 2309 "EventName": "TX_EXEC.MISC2", 2310 "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", 2311 "SampleAfterValue": "2000003", 2312 "UMask": "0x2" 2313 }, 2314 { 2315 "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", 2316 "Counter": "0,1,2,3", 2317 "EventCode": "0x5d", 2318 "EventName": "TX_EXEC.MISC3", 2319 "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", 2320 "SampleAfterValue": "2000003", 2321 "UMask": "0x4" 2322 }, 2323 { 2324 "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", 2325 "Counter": "0,1,2,3", 2326 "EventCode": "0x5d", 2327 "EventName": "TX_EXEC.MISC4", 2328 "PublicDescription": "RTM region detected inside HLE.", 2329 "SampleAfterValue": "2000003", 2330 "UMask": "0x8" 2331 }, 2332 { 2333 "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", 2334 "Counter": "0,1,2,3", 2335 "EventCode": "0x5d", 2336 "EventName": "TX_EXEC.MISC5", 2337 "SampleAfterValue": "2000003", 2338 "UMask": "0x10" 2339 }, 2340 { 2341 "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow", 2342 "Counter": "0,1,2,3", 2343 "EventCode": "0x54", 2344 "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", 2345 "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.", 2346 "SampleAfterValue": "2000003", 2347 "UMask": "0x2" 2348 }, 2349 { 2350 "BriefDescription": "Number of times a TSX line had a cache conflict", 2351 "Counter": "0,1,2,3", 2352 "EventCode": "0x54", 2353 "EventName": "TX_MEM.ABORT_CONFLICT", 2354 "PublicDescription": "Number of times a TSX line had a cache conflict.", 2355 "SampleAfterValue": "2000003", 2356 "UMask": "0x1" 2357 }, 2358 { 2359 "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch", 2360 "Counter": "0,1,2,3", 2361 "EventCode": "0x54", 2362 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 2363 "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", 2364 "SampleAfterValue": "2000003", 2365 "UMask": "0x10" 2366 }, 2367 { 2368 "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty", 2369 "Counter": "0,1,2,3", 2370 "EventCode": "0x54", 2371 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 2372 "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", 2373 "SampleAfterValue": "2000003", 2374 "UMask": "0x8" 2375 }, 2376 { 2377 "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer", 2378 "Counter": "0,1,2,3", 2379 "EventCode": "0x54", 2380 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", 2381 "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", 2382 "SampleAfterValue": "2000003", 2383 "UMask": "0x20" 2384 }, 2385 { 2386 "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock", 2387 "Counter": "0,1,2,3", 2388 "EventCode": "0x54", 2389 "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 2390 "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", 2391 "SampleAfterValue": "2000003", 2392 "UMask": "0x4" 2393 }, 2394 { 2395 "BriefDescription": "Number of times we could not allocate Lock Buffer", 2396 "Counter": "0,1,2,3", 2397 "EventCode": "0x54", 2398 "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", 2399 "PublicDescription": "Number of times we could not allocate Lock Buffer.", 2400 "SampleAfterValue": "2000003", 2401 "UMask": "0x40" 2402 } 2403]
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