virtual-memory.json

  1[
  2    {
  3        "BriefDescription": "Memory accesses that missed the DTLB.",
  4        "Counter": "0,1",
  5        "EventCode": "0x8",
  6        "EventName": "DATA_TLB_MISSES.DTLB_MISS",
  7        "SampleAfterValue": "200000",
  8        "UMask": "0x7"
  9    },
 10    {
 11        "BriefDescription": "DTLB misses due to load operations.",
 12        "Counter": "0,1",
 13        "EventCode": "0x8",
 14        "EventName": "DATA_TLB_MISSES.DTLB_MISS_LD",
 15        "SampleAfterValue": "200000",
 16        "UMask": "0x5"
 17    },
 18    {
 19        "BriefDescription": "DTLB misses due to store operations.",
 20        "Counter": "0,1",
 21        "EventCode": "0x8",
 22        "EventName": "DATA_TLB_MISSES.DTLB_MISS_ST",
 23        "SampleAfterValue": "200000",
 24        "UMask": "0x6"
 25    },
 26    {
 27        "BriefDescription": "L0 DTLB misses due to load operations.",
 28        "Counter": "0,1",
 29        "EventCode": "0x8",
 30        "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD",
 31        "SampleAfterValue": "200000",
 32        "UMask": "0x9"
 33    },
 34    {
 35        "BriefDescription": "L0 DTLB misses due to store operations",
 36        "Counter": "0,1",
 37        "EventCode": "0x8",
 38        "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST",
 39        "SampleAfterValue": "200000",
 40        "UMask": "0xa"
 41    },
 42    {
 43        "BriefDescription": "ITLB flushes.",
 44        "Counter": "0,1",
 45        "EventCode": "0x82",
 46        "EventName": "ITLB.FLUSH",
 47        "SampleAfterValue": "200000",
 48        "UMask": "0x4"
 49    },
 50    {
 51        "BriefDescription": "ITLB hits.",
 52        "Counter": "0,1",
 53        "EventCode": "0x82",
 54        "EventName": "ITLB.HIT",
 55        "SampleAfterValue": "200000",
 56        "UMask": "0x1"
 57    },
 58    {
 59        "BriefDescription": "ITLB misses.",
 60        "Counter": "0,1",
 61        "EventCode": "0x82",
 62        "EventName": "ITLB.MISSES",
 63        "PEBS": "2",
 64        "SampleAfterValue": "200000",
 65        "UMask": "0x2"
 66    },
 67    {
 68        "BriefDescription": "Retired loads that miss the DTLB (precise event).",
 69        "Counter": "0,1",
 70        "EventCode": "0xCB",
 71        "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
 72        "PEBS": "1",
 73        "SampleAfterValue": "200000",
 74        "UMask": "0x4"
 75    },
 76    {
 77        "BriefDescription": "Duration of page-walks in core cycles",
 78        "Counter": "0,1",
 79        "EventCode": "0xC",
 80        "EventName": "PAGE_WALKS.CYCLES",
 81        "SampleAfterValue": "2000000",
 82        "UMask": "0x3"
 83    },
 84    {
 85        "BriefDescription": "Duration of D-side only page walks",
 86        "Counter": "0,1",
 87        "EventCode": "0xC",
 88        "EventName": "PAGE_WALKS.D_SIDE_CYCLES",
 89        "SampleAfterValue": "2000000",
 90        "UMask": "0x1"
 91    },
 92    {
 93        "BriefDescription": "Number of D-side only page walks",
 94        "Counter": "0,1",
 95        "EventCode": "0xC",
 96        "EventName": "PAGE_WALKS.D_SIDE_WALKS",
 97        "SampleAfterValue": "200000",
 98        "UMask": "0x1"
 99    },
100    {
101        "BriefDescription": "Duration of I-Side page walks",
102        "Counter": "0,1",
103        "EventCode": "0xC",
104        "EventName": "PAGE_WALKS.I_SIDE_CYCLES",
105        "SampleAfterValue": "2000000",
106        "UMask": "0x2"
107    },
108    {
109        "BriefDescription": "Number of I-Side page walks",
110        "Counter": "0,1",
111        "EventCode": "0xC",
112        "EventName": "PAGE_WALKS.I_SIDE_WALKS",
113        "SampleAfterValue": "200000",
114        "UMask": "0x2"
115    },
116    {
117        "BriefDescription": "Number of page-walks executed.",
118        "Counter": "0,1",
119        "EventCode": "0xC",
120        "EventName": "PAGE_WALKS.WALKS",
121        "SampleAfterValue": "200000",
122        "UMask": "0x3"
123    }
124]