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floating-point.json

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linux-6.19.14/tools/perf/pmu-events/arch/x86/arrowlake/floating-point.json JSON 
  1[
  2    {
  3        "BriefDescription": "Counts the number of cycles when any of the floating point dividers are active.",
  4        "Counter": "0,1,2,3,4,5,6,7",
  5        "CounterMask": "1",
  6        "EventCode": "0xcd",
  7        "EventName": "ARITH.FPDIV_ACTIVE",
  8        "SampleAfterValue": "1000003",
  9        "UMask": "0x2",
 10        "Unit": "cpu_atom"
 11    },
 12    {
 13        "BriefDescription": "Cycles when floating-point divide unit is busy executing divide or square root operations.",
 14        "Counter": "0,1,2,3,4,5,6,7,8,9",
 15        "CounterMask": "1",
 16        "EventCode": "0xb0",
 17        "EventName": "ARITH.FPDIV_ACTIVE",
 18        "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for floating-point operations only.",
 19        "SampleAfterValue": "1000003",
 20        "UMask": "0x1",
 21        "Unit": "cpu_core"
 22    },
 23    {
 24        "BriefDescription": "Counts the number of cycles when any of the floating point dividers are active.",
 25        "Counter": "0,1,2,3,4,5,6,7",
 26        "CounterMask": "1",
 27        "EventCode": "0xcd",
 28        "EventName": "ARITH.FPDIV_ACTIVE",
 29        "SampleAfterValue": "1000003",
 30        "UMask": "0x2",
 31        "Unit": "cpu_lowpower"
 32    },
 33    {
 34        "BriefDescription": "Counts the number of active floating point dividers per cycle in the loop stage.",
 35        "Counter": "0,1,2,3,4,5,6,7",
 36        "EventCode": "0xcd",
 37        "EventName": "ARITH.FPDIV_OCCUPANCY",
 38        "SampleAfterValue": "1000003",
 39        "UMask": "0x2",
 40        "Unit": "cpu_atom"
 41    },
 42    {
 43        "BriefDescription": "Counts the number of floating point divider uops executed per cycle.",
 44        "Counter": "0,1,2,3,4,5,6,7",
 45        "EventCode": "0xcd",
 46        "EventName": "ARITH.FPDIV_UOPS",
 47        "SampleAfterValue": "1000003",
 48        "UMask": "0x8",
 49        "Unit": "cpu_atom"
 50    },
 51    {
 52        "BriefDescription": "Counts all microcode FP assists.",
 53        "Counter": "0,1,2,3,4,5,6,7,8,9",
 54        "EventCode": "0xc1",
 55        "EventName": "ASSISTS.FP",
 56        "PublicDescription": "Counts all microcode Floating Point assists.",
 57        "SampleAfterValue": "100003",
 58        "UMask": "0x2",
 59        "Unit": "cpu_core"
 60    },
 61    {
 62        "BriefDescription": "ASSISTS.SSE_AVX_MIX",
 63        "Counter": "0,1,2,3,4,5,6,7,8,9",
 64        "EventCode": "0xc1",
 65        "EventName": "ASSISTS.SSE_AVX_MIX",
 66        "SampleAfterValue": "1000003",
 67        "UMask": "0x10",
 68        "Unit": "cpu_core"
 69    },
 70    {
 71        "BriefDescription": "Number of FP-arith-uops dispatched on 1st VEC port (port 0). FP-arith-uops are of type ADD* / SUB* / MUL / FMA* / DPP.",
 72        "Counter": "0,1,2,3,4,5,6,7,8,9",
 73        "EventCode": "0xb3",
 74        "EventName": "FP_ARITH_DISPATCHED.V0",
 75        "SampleAfterValue": "2000003",
 76        "UMask": "0x1",
 77        "Unit": "cpu_core"
 78    },
 79    {
 80        "BriefDescription": "Number of FP-arith-uops dispatched on 2nd VEC port (port 1)",
 81        "Counter": "0,1,2,3,4,5,6,7,8,9",
 82        "EventCode": "0xb3",
 83        "EventName": "FP_ARITH_DISPATCHED.V1",
 84        "SampleAfterValue": "2000003",
 85        "UMask": "0x2",
 86        "Unit": "cpu_core"
 87    },
 88    {
 89        "BriefDescription": "Number of FP-arith-uops dispatched on 3rd VEC port (port 5)",
 90        "Counter": "0,1,2,3,4,5,6,7,8,9",
 91        "EventCode": "0xb3",
 92        "EventName": "FP_ARITH_DISPATCHED.V2",
 93        "SampleAfterValue": "2000003",
 94        "UMask": "0x4",
 95        "Unit": "cpu_core"
 96    },
 97    {
 98        "BriefDescription": "Number of FP-arith-uops dispatched on 4th VEC port",
 99        "Counter": "0,1,2,3,4,5,6,7,8,9",
100        "EventCode": "0xb3",
101        "EventName": "FP_ARITH_DISPATCHED.V3",
102        "SampleAfterValue": "2000003",
103        "UMask": "0x8",
104        "Unit": "cpu_core"
105    },
106    {
107        "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.128B_PACKED_DOUBLE",
108        "Counter": "0,1,2,3,4,5,6,7,8,9",
109        "Deprecated": "1",
110        "EventCode": "0xc7",
111        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
112        "SampleAfterValue": "100003",
113        "UMask": "0x4",
114        "Unit": "cpu_core"
115    },
116    {
117        "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.128B_PACKED_SINGLE",
118        "Counter": "0,1,2,3,4,5,6,7,8,9",
119        "Deprecated": "1",
120        "EventCode": "0xc7",
121        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
122        "SampleAfterValue": "100003",
123        "UMask": "0x8",
124        "Unit": "cpu_core"
125    },
126    {
127        "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.256B_PACKED_DOUBLE",
128        "Counter": "0,1,2,3,4,5,6,7,8,9",
129        "Deprecated": "1",
130        "EventCode": "0xc7",
131        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
132        "SampleAfterValue": "100003",
133        "UMask": "0x10",
134        "Unit": "cpu_core"
135    },
136    {
137        "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.256B_PACKED_SINGLE",
138        "Counter": "0,1,2,3,4,5,6,7,8,9",
139        "Deprecated": "1",
140        "EventCode": "0xc7",
141        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
142        "SampleAfterValue": "100003",
143        "UMask": "0x20",
144        "Unit": "cpu_core"
145    },
146    {
147        "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.4_FLOPS",
148        "Counter": "0,1,2,3,4,5,6,7,8,9",
149        "Deprecated": "1",
150        "EventCode": "0xc7",
151        "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS",
152        "SampleAfterValue": "100003",
153        "UMask": "0x18",
154        "Unit": "cpu_core"
155    },
156    {
157        "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.SCALAR",
158        "Counter": "0,1,2,3,4,5,6,7,8,9",
159        "Deprecated": "1",
160        "EventCode": "0xc7",
161        "EventName": "FP_ARITH_INST_RETIRED.SCALAR",
162        "SampleAfterValue": "1000003",
163        "UMask": "0x3",
164        "Unit": "cpu_core"
165    },
166    {
167        "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.SCALAR_DOUBLE",
168        "Counter": "0,1,2,3,4,5,6,7,8,9",
169        "Deprecated": "1",
170        "EventCode": "0xc7",
171        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
172        "SampleAfterValue": "100003",
173        "UMask": "0x1",
174        "Unit": "cpu_core"
175    },
176    {
177        "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.SCALAR_SINGLE",
178        "Counter": "0,1,2,3,4,5,6,7,8,9",
179        "Deprecated": "1",
180        "EventCode": "0xc7",
181        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
182        "SampleAfterValue": "100003",
183        "UMask": "0x2",
184        "Unit": "cpu_core"
185    },
186    {
187        "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.VECTOR",
188        "Counter": "0,1,2,3,4,5,6,7,8,9",
189        "Deprecated": "1",
190        "EventCode": "0xc7",
191        "EventName": "FP_ARITH_INST_RETIRED.VECTOR",
192        "SampleAfterValue": "1000003",
193        "UMask": "0x3c",
194        "Unit": "cpu_core"
195    },
196    {
197        "BriefDescription": "FP_ARITH_INST_RETIRED.VECTOR_128B [This event is alias to FP_ARITH_OPS_RETIRED.VECTOR_128B]",
198        "Counter": "0,1,2,3,4,5,6,7,8,9",
199        "EventCode": "0xc7",
200        "EventName": "FP_ARITH_INST_RETIRED.VECTOR_128B",
201        "SampleAfterValue": "100003",
202        "UMask": "0xc",
203        "Unit": "cpu_core"
204    },
205    {
206        "BriefDescription": "FP_ARITH_INST_RETIRED.VECTOR_256B [This event is alias to FP_ARITH_OPS_RETIRED.VECTOR_256B]",
207        "Counter": "0,1,2,3,4,5,6,7,8,9",
208        "EventCode": "0xc7",
209        "EventName": "FP_ARITH_INST_RETIRED.VECTOR_256B",
210        "SampleAfterValue": "100003",
211        "UMask": "0x30",
212        "Unit": "cpu_core"
213    },
214    {
215        "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
216        "Counter": "0,1,2,3,4,5,6,7,8,9",
217        "EventCode": "0xc7",
218        "EventName": "FP_ARITH_OPS_RETIRED.128B_PACKED_DOUBLE",
219        "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
220        "SampleAfterValue": "100003",
221        "UMask": "0x4",
222        "Unit": "cpu_core"
223    },
224    {
225        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
226        "Counter": "0,1,2,3,4,5,6,7,8,9",
227        "EventCode": "0xc7",
228        "EventName": "FP_ARITH_OPS_RETIRED.128B_PACKED_SINGLE",
229        "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
230        "SampleAfterValue": "100003",
231        "UMask": "0x8",
232        "Unit": "cpu_core"
233    },
234    {
235        "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
236        "Counter": "0,1,2,3,4,5,6,7,8,9",
237        "EventCode": "0xc7",
238        "EventName": "FP_ARITH_OPS_RETIRED.256B_PACKED_DOUBLE",
239        "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
240        "SampleAfterValue": "100003",
241        "UMask": "0x10",
242        "Unit": "cpu_core"
243    },
244    {
245        "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
246        "Counter": "0,1,2,3,4,5,6,7,8,9",
247        "EventCode": "0xc7",
248        "EventName": "FP_ARITH_OPS_RETIRED.256B_PACKED_SINGLE",
249        "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
250        "SampleAfterValue": "100003",
251        "UMask": "0x20",
252        "Unit": "cpu_core"
253    },
254    {
255        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, 1 for each element.  Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",
256        "Counter": "0,1,2,3,4,5,6,7,8,9",
257        "EventCode": "0xc7",
258        "EventName": "FP_ARITH_OPS_RETIRED.4_FLOPS",
259        "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision  floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
260        "SampleAfterValue": "100003",
261        "UMask": "0x18",
262        "Unit": "cpu_core"
263    },
264    {
265        "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below.  Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
266        "Counter": "0,1,2,3,4,5,6,7,8,9",
267        "EventCode": "0xc7",
268        "EventName": "FP_ARITH_OPS_RETIRED.SCALAR",
269        "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
270        "SampleAfterValue": "1000003",
271        "UMask": "0x3",
272        "Unit": "cpu_core"
273    },
274    {
275        "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
276        "Counter": "0,1,2,3,4,5,6,7,8,9",
277        "EventCode": "0xc7",
278        "EventName": "FP_ARITH_OPS_RETIRED.SCALAR_DOUBLE",
279        "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
280        "SampleAfterValue": "100003",
281        "UMask": "0x1",
282        "Unit": "cpu_core"
283    },
284    {
285        "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
286        "Counter": "0,1,2,3,4,5,6,7,8,9",
287        "EventCode": "0xc7",
288        "EventName": "FP_ARITH_OPS_RETIRED.SCALAR_SINGLE",
289        "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
290        "SampleAfterValue": "100003",
291        "UMask": "0x2",
292        "Unit": "cpu_core"
293    },
294    {
295        "BriefDescription": "Number of any Vector retired FP arithmetic instructions",
296        "Counter": "0,1,2,3,4,5,6,7,8,9",
297        "EventCode": "0xc7",
298        "EventName": "FP_ARITH_OPS_RETIRED.VECTOR",
299        "PublicDescription": "Number of any Vector retired FP arithmetic instructions.  The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
300        "SampleAfterValue": "1000003",
301        "UMask": "0x3c",
302        "Unit": "cpu_core"
303    },
304    {
305        "BriefDescription": "FP_ARITH_OPS_RETIRED.VECTOR_128B [This event is alias to FP_ARITH_INST_RETIRED.VECTOR_128B]",
306        "Counter": "0,1,2,3,4,5,6,7,8,9",
307        "EventCode": "0xc7",
308        "EventName": "FP_ARITH_OPS_RETIRED.VECTOR_128B",
309        "SampleAfterValue": "100003",
310        "UMask": "0xc",
311        "Unit": "cpu_core"
312    },
313    {
314        "BriefDescription": "FP_ARITH_OPS_RETIRED.VECTOR_256B [This event is alias to FP_ARITH_INST_RETIRED.VECTOR_256B]",
315        "Counter": "0,1,2,3,4,5,6,7,8,9",
316        "EventCode": "0xc7",
317        "EventName": "FP_ARITH_OPS_RETIRED.VECTOR_256B",
318        "SampleAfterValue": "100003",
319        "UMask": "0x30",
320        "Unit": "cpu_core"
321    },
322    {
323        "BriefDescription": "Counts the number of all types of floating point operations per uop with all default weighting",
324        "Counter": "0,1,2,3,4,5,6,7",
325        "EventCode": "0xc8",
326        "EventName": "FP_FLOPS_RETIRED.ALL",
327        "SampleAfterValue": "1000003",
328        "UMask": "0x3",
329        "Unit": "cpu_atom"
330    },
331    {
332        "BriefDescription": "Counts the number of all types of floating point operations per uop with all default weighting",
333        "Counter": "0,1,2,3,4,5,6,7",
334        "EventCode": "0xc8",
335        "EventName": "FP_FLOPS_RETIRED.ALL",
336        "SampleAfterValue": "1000003",
337        "UMask": "0x3",
338        "Unit": "cpu_lowpower"
339    },
340    {
341        "BriefDescription": "This event is deprecated. [This event is alias to FP_FLOPS_RETIRED.FP64]",
342        "Counter": "0,1,2,3,4,5,6,7",
343        "Deprecated": "1",
344        "EventCode": "0xc8",
345        "EventName": "FP_FLOPS_RETIRED.DP",
346        "SampleAfterValue": "1000003",
347        "UMask": "0x1",
348        "Unit": "cpu_lowpower"
349    },
350    {
351        "BriefDescription": "Counts the number of floating point operations that produce 32 bit single precision results",
352        "Counter": "0,1,2,3,4,5,6,7",
353        "EventCode": "0xc8",
354        "EventName": "FP_FLOPS_RETIRED.FP32",
355        "SampleAfterValue": "1000003",
356        "UMask": "0x2",
357        "Unit": "cpu_atom"
358    },
359    {
360        "BriefDescription": "Counts the number of floating point operations that produce 32 bit single precision results [This event is alias to FP_FLOPS_RETIRED.SP]",
361        "Counter": "0,1,2,3,4,5,6,7",
362        "EventCode": "0xc8",
363        "EventName": "FP_FLOPS_RETIRED.FP32",
364        "SampleAfterValue": "1000003",
365        "UMask": "0x2",
366        "Unit": "cpu_lowpower"
367    },
368    {
369        "BriefDescription": "Counts the number of floating point operations that produce 64 bit double precision results",
370        "Counter": "0,1,2,3,4,5,6,7",
371        "EventCode": "0xc8",
372        "EventName": "FP_FLOPS_RETIRED.FP64",
373        "SampleAfterValue": "1000003",
374        "UMask": "0x1",
375        "Unit": "cpu_atom"
376    },
377    {
378        "BriefDescription": "Counts the number of floating point operations that produce 64 bit double precision results [This event is alias to FP_FLOPS_RETIRED.DP]",
379        "Counter": "0,1,2,3,4,5,6,7",
380        "EventCode": "0xc8",
381        "EventName": "FP_FLOPS_RETIRED.FP64",
382        "SampleAfterValue": "1000003",
383        "UMask": "0x1",
384        "Unit": "cpu_lowpower"
385    },
386    {
387        "BriefDescription": "This event is deprecated. [This event is alias to FP_FLOPS_RETIRED.FP32]",
388        "Counter": "0,1,2,3,4,5,6,7",
389        "Deprecated": "1",
390        "EventCode": "0xc8",
391        "EventName": "FP_FLOPS_RETIRED.SP",
392        "SampleAfterValue": "1000003",
393        "UMask": "0x2",
394        "Unit": "cpu_lowpower"
395    },
396    {
397        "BriefDescription": "Counts the number of retired instructions whose sources are a packed 128 bit double precision floating point. This may be SSE or AVX.128 operations.",
398        "Counter": "0,1,2,3,4,5,6,7",
399        "EventCode": "0xc7",
400        "EventName": "FP_INST_RETIRED.128B_DP",
401        "SampleAfterValue": "1000003",
402        "UMask": "0x8",
403        "Unit": "cpu_atom"
404    },
405    {
406        "BriefDescription": "Counts the total number of  floating point retired instructions.",
407        "Counter": "0,1,2,3,4,5,6,7",
408        "EventCode": "0xc7",
409        "EventName": "FP_INST_RETIRED.128B_DP",
410        "SampleAfterValue": "1000003",
411        "UMask": "0x8",
412        "Unit": "cpu_lowpower"
413    },
414    {
415        "BriefDescription": "Counts the number of retired instructions whose sources are a packed 128 bit single precision floating point. This may be SSE or AVX.128 operations.",
416        "Counter": "0,1,2,3,4,5,6,7",
417        "EventCode": "0xc7",
418        "EventName": "FP_INST_RETIRED.128B_SP",
419        "SampleAfterValue": "1000003",
420        "UMask": "0x4",
421        "Unit": "cpu_atom"
422    },
423    {
424        "BriefDescription": "Counts the number of retired instructions whose sources are a packed 128 bit single precision floating point. This may be SSE or AVX.128 operations.",
425        "Counter": "0,1,2,3,4,5,6,7",
426        "EventCode": "0xc7",
427        "EventName": "FP_INST_RETIRED.128B_SP",
428        "SampleAfterValue": "1000003",
429        "UMask": "0x4",
430        "Unit": "cpu_lowpower"
431    },
432    {
433        "BriefDescription": "Counts the number of retired instructions whose sources are a packed 256 bit double precision floating point.",
434        "Counter": "0,1,2,3,4,5,6,7",
435        "EventCode": "0xc7",
436        "EventName": "FP_INST_RETIRED.256B_DP",
437        "SampleAfterValue": "1000003",
438        "UMask": "0x20",
439        "Unit": "cpu_atom"
440    },
441    {
442        "BriefDescription": "Counts the number of retired instructions whose sources are a packed 256 bit double precision floating point.",
443        "Counter": "0,1,2,3,4,5,6,7",
444        "EventCode": "0xc7",
445        "EventName": "FP_INST_RETIRED.256B_DP",
446        "SampleAfterValue": "1000003",
447        "UMask": "0x20",
448        "Unit": "cpu_lowpower"
449    },
450    {
451        "BriefDescription": "Counts the number of retired instructions whose sources are a packed 256 bit single precision floating point.",
452        "Counter": "0,1,2,3,4,5,6,7",
453        "EventCode": "0xc7",
454        "EventName": "FP_INST_RETIRED.256B_SP",
455        "SampleAfterValue": "1000003",
456        "UMask": "0x10",
457        "Unit": "cpu_atom"
458    },
459    {
460        "BriefDescription": "Counts the number of retired instructions whose sources are a scalar 32bit single precision floating point",
461        "Counter": "0,1,2,3,4,5,6,7",
462        "EventCode": "0xc7",
463        "EventName": "FP_INST_RETIRED.32B_SP",
464        "SampleAfterValue": "1000003",
465        "UMask": "0x1",
466        "Unit": "cpu_atom"
467    },
468    {
469        "BriefDescription": "Counts the number of retired instructions whose sources are a scalar 32bit single precision floating point.",
470        "Counter": "0,1,2,3,4,5,6,7",
471        "EventCode": "0xc7",
472        "EventName": "FP_INST_RETIRED.32B_SP",
473        "SampleAfterValue": "1000003",
474        "UMask": "0x1",
475        "Unit": "cpu_lowpower"
476    },
477    {
478        "BriefDescription": "Counts the number of retired instructions whose sources are a scalar 64 bit double precision floating point",
479        "Counter": "0,1,2,3,4,5,6,7",
480        "EventCode": "0xc7",
481        "EventName": "FP_INST_RETIRED.64B_DP",
482        "SampleAfterValue": "1000003",
483        "UMask": "0x2",
484        "Unit": "cpu_atom"
485    },
486    {
487        "BriefDescription": "Counts the number of retired instructions whose sources are a scalar 64 bit double precision floating point.",
488        "Counter": "0,1,2,3,4,5,6,7",
489        "EventCode": "0xc7",
490        "EventName": "FP_INST_RETIRED.64B_DP",
491        "SampleAfterValue": "1000003",
492        "UMask": "0x2",
493        "Unit": "cpu_lowpower"
494    },
495    {
496        "BriefDescription": "Counts the total number of  floating point retired instructions.",
497        "Counter": "0,1,2,3,4,5,6,7",
498        "EventCode": "0xc7",
499        "EventName": "FP_INST_RETIRED.ALL",
500        "SampleAfterValue": "1000003",
501        "UMask": "0x3f",
502        "Unit": "cpu_atom"
503    },
504    {
505        "BriefDescription": "Counts the number of uops executed on all floating point ports.",
506        "Counter": "0,1,2,3,4,5,6,7",
507        "EventCode": "0xb2",
508        "EventName": "FP_VINT_UOPS_EXECUTED.ALL",
509        "SampleAfterValue": "1000003",
510        "UMask": "0x1f",
511        "Unit": "cpu_atom"
512    },
513    {
514        "BriefDescription": "Counts the number of uops executed on floating point and vector integer port 0.",
515        "Counter": "0,1,2,3,4,5,6,7",
516        "EventCode": "0xb2",
517        "EventName": "FP_VINT_UOPS_EXECUTED.P0",
518        "SampleAfterValue": "1000003",
519        "UMask": "0x2",
520        "Unit": "cpu_atom"
521    },
522    {
523        "BriefDescription": "Counts the number of uops executed on floating point and vector integer port 1.",
524        "Counter": "0,1,2,3,4,5,6,7",
525        "EventCode": "0xb2",
526        "EventName": "FP_VINT_UOPS_EXECUTED.P1",
527        "SampleAfterValue": "1000003",
528        "UMask": "0x4",
529        "Unit": "cpu_atom"
530    },
531    {
532        "BriefDescription": "Counts the number of uops executed on floating point and vector integer port 2.",
533        "Counter": "0,1,2,3,4,5,6,7",
534        "EventCode": "0xb2",
535        "EventName": "FP_VINT_UOPS_EXECUTED.P2",
536        "SampleAfterValue": "1000003",
537        "UMask": "0x8",
538        "Unit": "cpu_atom"
539    },
540    {
541        "BriefDescription": "Counts the number of uops executed on floating point and vector integer port 3.",
542        "Counter": "0,1,2,3,4,5,6,7",
543        "EventCode": "0xb2",
544        "EventName": "FP_VINT_UOPS_EXECUTED.P3",
545        "SampleAfterValue": "1000003",
546        "UMask": "0x10",
547        "Unit": "cpu_atom"
548    },
549    {
550        "BriefDescription": "Counts the number of uops executed on floating point and vector integer port 0, 1, 2, 3.",
551        "Counter": "0,1,2,3,4,5,6,7",
552        "EventCode": "0xb2",
553        "EventName": "FP_VINT_UOPS_EXECUTED.PRIMARY",
554        "SampleAfterValue": "1000003",
555        "UMask": "0x1e",
556        "Unit": "cpu_atom"
557    },
558    {
559        "BriefDescription": "Counts the number of uops executed on floating point and vector integer store data port.",
560        "Counter": "0,1,2,3,4,5,6,7",
561        "EventCode": "0xb2",
562        "EventName": "FP_VINT_UOPS_EXECUTED.STD",
563        "SampleAfterValue": "1000003",
564        "UMask": "0x1",
565        "Unit": "cpu_atom"
566    },
567    {
568        "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",
569        "Counter": "0,1,2,3,4,5,6,7",
570        "EventCode": "0xc3",
571        "EventName": "MACHINE_CLEARS.FP_ASSIST",
572        "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.",
573        "SampleAfterValue": "20003",
574        "UMask": "0x4",
575        "Unit": "cpu_atom"
576    },
577    {
578        "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",
579        "Counter": "0,1,2,3,4,5,6,7",
580        "EventCode": "0xc3",
581        "EventName": "MACHINE_CLEARS.FP_ASSIST",
582        "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.",
583        "SampleAfterValue": "20003",
584        "UMask": "0x4",
585        "Unit": "cpu_lowpower"
586    },
587    {
588        "BriefDescription": "Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt)",
589        "Counter": "0,1,2,3,4,5,6,7",
590        "EventCode": "0xc2",
591        "EventName": "UOPS_RETIRED.FPDIV",
592        "SampleAfterValue": "2000003",
593        "UMask": "0x8",
594        "Unit": "cpu_atom"
595    },
596    {
597        "BriefDescription": "Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt).",
598        "Counter": "0,1,2,3,4,5,6,7",
599        "EventCode": "0xc2",
600        "EventName": "UOPS_RETIRED.FPDIV",
601        "SampleAfterValue": "2000003",
602        "UMask": "0x8",
603        "Unit": "cpu_lowpower"
604    }
605]
~/ Read-only file preview.