memory.json

  1[
  2  {
  3    "EventName": "ls_bad_status2.stli_other",
  4    "EventCode": "0x24",
  5    "BriefDescription": "Store-to-load conflicts (load unable to complete due to a non-forwardable conflict with an older store).",
  6    "UMask": "0x02"
  7  },
  8  {
  9    "EventName": "ls_dispatch.ld_dispatch",
 10    "EventCode": "0x29",
 11    "BriefDescription": "Number of memory load operations dispatched to the load-store unit.",
 12    "UMask": "0x01"
 13  },
 14  {
 15    "EventName": "ls_dispatch.store_dispatch",
 16    "EventCode": "0x29",
 17    "BriefDescription": "Number of memory store operations dispatched to the load-store unit.",
 18    "UMask": "0x02"
 19  },
 20  {
 21    "EventName": "ls_dispatch.ld_st_dispatch",
 22    "EventCode": "0x29",
 23    "BriefDescription": "Number of memory load-store operations dispatched to the load-store unit.",
 24    "UMask": "0x04"
 25  },
 26  {
 27    "EventName": "ls_stlf",
 28    "EventCode": "0x35",
 29    "BriefDescription": "Store-to-load-forward (STLF) hits."
 30  },
 31  {
 32    "EventName": "ls_st_commit_cancel2.st_commit_cancel_wcb_full",
 33    "EventCode": "0x37",
 34    "BriefDescription": "Non-cacheable store commits cancelled due to the non-cacheable commit buffer being full.",
 35    "UMask": "0x01"
 36  },
 37  {
 38    "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit",
 39    "EventCode": "0x45",
 40    "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 4k pages.",
 41    "UMask": "0x01"
 42  },
 43  {
 44    "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit",
 45    "EventCode": "0x45",
 46    "BriefDescription": "L1 DTLB misses with L2 DTLB hits for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
 47    "UMask": "0x02"
 48  },
 49  {
 50    "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit",
 51    "EventCode": "0x45",
 52    "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 2M pages.",
 53    "UMask": "0x04"
 54  },
 55  {
 56    "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit",
 57    "EventCode": "0x45",
 58    "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 1G pages.",
 59    "UMask": "0x08"
 60  },
 61  {
 62    "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss",
 63    "EventCode": "0x45",
 64    "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 4k pages.",
 65    "UMask": "0x10"
 66  },
 67  {
 68    "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss",
 69    "EventCode": "0x45",
 70    "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
 71    "UMask": "0x20"
 72  },
 73  {
 74    "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss",
 75    "EventCode": "0x45",
 76    "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 2M pages.",
 77    "UMask": "0x40"
 78  },
 79  {
 80    "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss",
 81    "EventCode": "0x45",
 82    "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 1G pages.",
 83    "UMask": "0x80"
 84  },
 85  {
 86    "EventName": "ls_l1_d_tlb_miss.all_l2_miss",
 87    "EventCode": "0x45",
 88    "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for all page sizes.",
 89    "UMask": "0xf0"
 90  },
 91  {
 92    "EventName": "ls_l1_d_tlb_miss.all",
 93    "EventCode": "0x45",
 94    "BriefDescription": "L1 DTLB misses for all page sizes.",
 95    "UMask": "0xff"
 96  },
 97  {
 98    "EventName": "ls_misal_loads.ma64",
 99    "EventCode": "0x47",
100    "BriefDescription": "64B misaligned (cacheline crossing) loads.",
101    "UMask": "0x01"
102  },
103  {
104    "EventName": "ls_misal_loads.ma4k",
105    "EventCode": "0x47",
106    "BriefDescription": "4kB misaligned (page crossing) loads.",
107    "UMask": "0x02"
108  },
109  {
110    "EventName": "ls_tlb_flush.all",
111    "EventCode": "0x78",
112    "BriefDescription": "All TLB Flushes.",
113    "UMask": "0xff"
114  },
115  {
116    "EventName": "bp_l1_tlb_miss_l2_tlb_hit",
117    "EventCode": "0x84",
118    "BriefDescription": "Instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
119  },
120  {
121    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if4k",
122    "EventCode": "0x85",
123    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 4k pages.",
124    "UMask": "0x01"
125  },
126  {
127    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if2m",
128    "EventCode": "0x85",
129    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 2M pages.",
130    "UMask": "0x02"
131  },
132  {
133    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if1g",
134    "EventCode": "0x85",
135    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 1G pages.",
136    "UMask": "0x04"
137  },
138  {
139    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k",
140    "EventCode": "0x85",
141    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
142    "UMask": "0x08"
143  },
144  {
145    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.all",
146    "EventCode": "0x85",
147    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for all page sizes.",
148    "UMask": "0x0f"
149  },
150  {
151    "EventName": "bp_l1_tlb_fetch_hit.if4k",
152    "EventCode": "0x94",
153    "BriefDescription": "Instruction fetches that hit in the L1 ITLB for 4k or coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
154    "UMask": "0x01"
155  },
156  {
157    "EventName": "bp_l1_tlb_fetch_hit.if2m",
158    "EventCode": "0x94",
159    "BriefDescription": "Instruction fetches that hit in the L1 ITLB for 2M pages.",
160    "UMask": "0x02"
161  },
162  {
163    "EventName": "bp_l1_tlb_fetch_hit.if1g",
164    "EventCode": "0x94",
165    "BriefDescription": "Instruction fetches that hit in the L1 ITLB for 1G pages.",
166    "UMask": "0x04"
167  },
168  {
169    "EventName": "bp_l1_tlb_fetch_hit.all",
170    "EventCode": "0x94",
171    "BriefDescription": "Instruction fetches that hit in the L1 ITLB for all page sizes.",
172    "UMask": "0x07"
173  }
174]