floating-point.json

  1[
  2    {
  3        "BriefDescription": "Counts the number of cycles the floating point divider is in the loop stage.",
  4        "Counter": "0,1,2,3,4,5",
  5        "EventCode": "0xcd",
  6        "EventName": "ARITH.FPDIV_ACTIVE",
  7        "SampleAfterValue": "1000003",
  8        "UMask": "0x2",
  9        "Unit": "cpu_atom"
 10    },
 11    {
 12        "BriefDescription": "ARITH.FPDIV_ACTIVE",
 13        "Counter": "0,1,2,3,4,5,6,7",
 14        "CounterMask": "1",
 15        "EventCode": "0xb0",
 16        "EventName": "ARITH.FPDIV_ACTIVE",
 17        "SampleAfterValue": "1000003",
 18        "UMask": "0x1",
 19        "Unit": "cpu_core"
 20    },
 21    {
 22        "BriefDescription": "Counts the number of floating point divider uops executed per cycle.",
 23        "Counter": "0,1,2,3,4,5",
 24        "EventCode": "0xcd",
 25        "EventName": "ARITH.FPDIV_UOPS",
 26        "SampleAfterValue": "1000003",
 27        "UMask": "0x8",
 28        "Unit": "cpu_atom"
 29    },
 30    {
 31        "BriefDescription": "Counts all microcode FP assists.",
 32        "Counter": "0,1,2,3,4,5,6,7",
 33        "EventCode": "0xc1",
 34        "EventName": "ASSISTS.FP",
 35        "PublicDescription": "Counts all microcode Floating Point assists.",
 36        "SampleAfterValue": "100003",
 37        "UMask": "0x2",
 38        "Unit": "cpu_core"
 39    },
 40    {
 41        "BriefDescription": "ASSISTS.SSE_AVX_MIX",
 42        "Counter": "0,1,2,3,4,5,6,7",
 43        "EventCode": "0xc1",
 44        "EventName": "ASSISTS.SSE_AVX_MIX",
 45        "SampleAfterValue": "1000003",
 46        "UMask": "0x10",
 47        "Unit": "cpu_core"
 48    },
 49    {
 50        "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0]",
 51        "Counter": "0,1,2,3,4,5,6,7",
 52        "EventCode": "0xb3",
 53        "EventName": "FP_ARITH_DISPATCHED.PORT_0",
 54        "SampleAfterValue": "2000003",
 55        "UMask": "0x1",
 56        "Unit": "cpu_core"
 57    },
 58    {
 59        "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1]",
 60        "Counter": "0,1,2,3,4,5,6,7",
 61        "EventCode": "0xb3",
 62        "EventName": "FP_ARITH_DISPATCHED.PORT_1",
 63        "SampleAfterValue": "2000003",
 64        "UMask": "0x2",
 65        "Unit": "cpu_core"
 66    },
 67    {
 68        "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2]",
 69        "Counter": "0,1,2,3,4,5,6,7",
 70        "EventCode": "0xb3",
 71        "EventName": "FP_ARITH_DISPATCHED.PORT_5",
 72        "SampleAfterValue": "2000003",
 73        "UMask": "0x4",
 74        "Unit": "cpu_core"
 75    },
 76    {
 77        "BriefDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0]",
 78        "Counter": "0,1,2,3,4,5,6,7",
 79        "EventCode": "0xb3",
 80        "EventName": "FP_ARITH_DISPATCHED.V0",
 81        "SampleAfterValue": "2000003",
 82        "UMask": "0x1",
 83        "Unit": "cpu_core"
 84    },
 85    {
 86        "BriefDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1]",
 87        "Counter": "0,1,2,3,4,5,6,7",
 88        "EventCode": "0xb3",
 89        "EventName": "FP_ARITH_DISPATCHED.V1",
 90        "SampleAfterValue": "2000003",
 91        "UMask": "0x2",
 92        "Unit": "cpu_core"
 93    },
 94    {
 95        "BriefDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5]",
 96        "Counter": "0,1,2,3,4,5,6,7",
 97        "EventCode": "0xb3",
 98        "EventName": "FP_ARITH_DISPATCHED.V2",
 99        "SampleAfterValue": "2000003",
100        "UMask": "0x4",
101        "Unit": "cpu_core"
102    },
103    {
104        "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
105        "Counter": "0,1,2,3,4,5,6,7",
106        "EventCode": "0xc7",
107        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
108        "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
109        "SampleAfterValue": "100003",
110        "UMask": "0x4",
111        "Unit": "cpu_core"
112    },
113    {
114        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
115        "Counter": "0,1,2,3,4,5,6,7",
116        "EventCode": "0xc7",
117        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
118        "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
119        "SampleAfterValue": "100003",
120        "UMask": "0x8",
121        "Unit": "cpu_core"
122    },
123    {
124        "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
125        "Counter": "0,1,2,3,4,5,6,7",
126        "EventCode": "0xc7",
127        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
128        "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
129        "SampleAfterValue": "100003",
130        "UMask": "0x10",
131        "Unit": "cpu_core"
132    },
133    {
134        "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
135        "Counter": "0,1,2,3,4,5,6,7",
136        "EventCode": "0xc7",
137        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
138        "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
139        "SampleAfterValue": "100003",
140        "UMask": "0x20",
141        "Unit": "cpu_core"
142    },
143    {
144        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, 1 for each element.  Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",
145        "Counter": "0,1,2,3,4,5,6,7",
146        "EventCode": "0xc7",
147        "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS",
148        "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision  floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
149        "SampleAfterValue": "100003",
150        "UMask": "0x18",
151        "Unit": "cpu_core"
152    },
153    {
154        "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below.  Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
155        "Counter": "0,1,2,3,4,5,6,7",
156        "EventCode": "0xc7",
157        "EventName": "FP_ARITH_INST_RETIRED.SCALAR",
158        "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
159        "SampleAfterValue": "1000003",
160        "UMask": "0x3",
161        "Unit": "cpu_core"
162    },
163    {
164        "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
165        "Counter": "0,1,2,3,4,5,6,7",
166        "EventCode": "0xc7",
167        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
168        "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
169        "SampleAfterValue": "100003",
170        "UMask": "0x1",
171        "Unit": "cpu_core"
172    },
173    {
174        "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
175        "Counter": "0,1,2,3,4,5,6,7",
176        "EventCode": "0xc7",
177        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
178        "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
179        "SampleAfterValue": "100003",
180        "UMask": "0x2",
181        "Unit": "cpu_core"
182    },
183    {
184        "BriefDescription": "Number of any Vector retired FP arithmetic instructions",
185        "Counter": "0,1,2,3,4,5,6,7",
186        "EventCode": "0xc7",
187        "EventName": "FP_ARITH_INST_RETIRED.VECTOR",
188        "PublicDescription": "Number of any Vector retired FP arithmetic instructions.  The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
189        "SampleAfterValue": "1000003",
190        "UMask": "0xfc",
191        "Unit": "cpu_core"
192    },
193    {
194        "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",
195        "Counter": "0,1,2,3,4,5",
196        "EventCode": "0xc3",
197        "EventName": "MACHINE_CLEARS.FP_ASSIST",
198        "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.",
199        "SampleAfterValue": "20003",
200        "UMask": "0x4",
201        "Unit": "cpu_atom"
202    },
203    {
204        "BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).",
205        "Counter": "0,1,2,3,4,5",
206        "EventCode": "0xc2",
207        "EventName": "UOPS_RETIRED.FPDIV",
208        "SampleAfterValue": "2000003",
209        "UMask": "0x8",
210        "Unit": "cpu_atom"
211    }
212]