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linux-6.19.14/tools/perf/pmu-events/arch/s390/cf_z13/extended.json JSON 
  1[
  2	{
  3		"Unit": "CPU-M-CF",
  4		"EventCode": "128",
  5		"EventName": "L1D_RO_EXCL_WRITES",
  6		"BriefDescription": "L1D Read-only Exclusive Writes",
  7		"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line."
  8	},
  9	{
 10		"Unit": "CPU-M-CF",
 11		"EventCode": "129",
 12		"EventName": "DTLB1_WRITES",
 13		"BriefDescription": "DTLB1 Writes",
 14		"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer (DTLB1)."
 15	},
 16	{
 17		"Unit": "CPU-M-CF",
 18		"EventCode": "130",
 19		"EventName": "DTLB1_MISSES",
 20		"BriefDescription": "DTLB1 Misses",
 21		"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB1 miss is in progress."
 22	},
 23	{
 24		"Unit": "CPU-M-CF",
 25		"EventCode": "131",
 26		"EventName": "DTLB1_HPAGE_WRITES",
 27		"BriefDescription": "DTLB1 One-Megabyte Page Writes",
 28		"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page."
 29	},
 30	{
 31		"Unit": "CPU-M-CF",
 32		"EventCode": "132",
 33		"EventName": "DTLB1_GPAGE_WRITES",
 34		"BriefDescription": "DTLB1 Two-Gigabyte Page Writes",
 35		"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a two-gigabyte page."
 36	},
 37	{
 38		"Unit": "CPU-M-CF",
 39		"EventCode": "133",
 40		"EventName": "L1D_L2D_SOURCED_WRITES",
 41		"BriefDescription": "L1D L2D Sourced Writes",
 42		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache."
 43	},
 44	{
 45		"Unit": "CPU-M-CF",
 46		"EventCode": "134",
 47		"EventName": "ITLB1_WRITES",
 48		"BriefDescription": "ITLB1 Writes",
 49		"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer (ITLB1)."
 50	},
 51	{
 52		"Unit": "CPU-M-CF",
 53		"EventCode": "135",
 54		"EventName": "ITLB1_MISSES",
 55		"BriefDescription": "ITLB1 Misses",
 56		"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle an ITLB1 miss is in progress."
 57	},
 58	{
 59		"Unit": "CPU-M-CF",
 60		"EventCode": "136",
 61		"EventName": "L1I_L2I_SOURCED_WRITES",
 62		"BriefDescription": "L1I L2I Sourced Writes",
 63		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache."
 64	},
 65	{
 66		"Unit": "CPU-M-CF",
 67		"EventCode": "137",
 68		"EventName": "TLB2_PTE_WRITES",
 69		"BriefDescription": "TLB2 PTE Writes",
 70		"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays."
 71	},
 72	{
 73		"Unit": "CPU-M-CF",
 74		"EventCode": "138",
 75		"EventName": "TLB2_CRSTE_HPAGE_WRITES",
 76		"BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
 77		"PublicDescription": "A translation entry has been written to the Level-2 TLB Combined Region Segment Table Entry arrays for a one-megabyte large page translation."
 78	},
 79	{
 80		"Unit": "CPU-M-CF",
 81		"EventCode": "139",
 82		"EventName": "TLB2_CRSTE_WRITES",
 83		"BriefDescription": "TLB2 CRSTE Writes",
 84		"PublicDescription": "A translation entry has been written to the Level-2 TLB Combined Region Segment Table Entry arrays."
 85	},
 86	{
 87		"Unit": "CPU-M-CF",
 88		"EventCode": "140",
 89		"EventName": "TX_C_TEND",
 90		"BriefDescription": "Completed TEND instructions in constrained TX mode",
 91		"PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode."
 92	},
 93	{
 94		"Unit": "CPU-M-CF",
 95		"EventCode": "141",
 96		"EventName": "TX_NC_TEND",
 97		"BriefDescription": "Completed TEND instructions in non-constrained TX mode",
 98		"PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode."
 99	},
100	{
101		"Unit": "CPU-M-CF",
102		"EventCode": "143",
103		"EventName": "L1C_TLB1_MISSES",
104		"BriefDescription": "L1C TLB1 Misses",
105		"PublicDescription": "Increments by one for any cycle where a Level-1 cache or Level-1 TLB miss is in progress."
106	},
107	{
108		"Unit": "CPU-M-CF",
109		"EventCode": "144",
110		"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
111		"BriefDescription": "L1D On-Chip L3 Sourced Writes",
112		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention."
113	},
114	{
115		"Unit": "CPU-M-CF",
116		"EventCode": "145",
117		"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV",
118		"BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention",
119		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention."
120	},
121	{
122		"Unit": "CPU-M-CF",
123		"EventCode": "146",
124		"EventName": "L1D_ONNODE_L4_SOURCED_WRITES",
125		"BriefDescription": "L1D On-Node L4 Sourced Writes",
126		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-4 cache."
127	},
128	{
129		"Unit": "CPU-M-CF",
130		"EventCode": "147",
131		"EventName": "L1D_ONNODE_L3_SOURCED_WRITES_IV",
132		"BriefDescription": "L1D On-Node L3 Sourced Writes with Intervention",
133		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-3 cache with intervention."
134	},
135	{
136		"Unit": "CPU-M-CF",
137		"EventCode": "148",
138		"EventName": "L1D_ONNODE_L3_SOURCED_WRITES",
139		"BriefDescription": "L1D On-Node L3 Sourced Writes",
140		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-3 cache without intervention."
141	},
142	{
143		"Unit": "CPU-M-CF",
144		"EventCode": "149",
145		"EventName": "L1D_ONDRAWER_L4_SOURCED_WRITES",
146		"BriefDescription": "L1D On-Drawer L4 Sourced Writes",
147		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-4 cache."
148	},
149	{
150		"Unit": "CPU-M-CF",
151		"EventCode": "150",
152		"EventName": "L1D_ONDRAWER_L3_SOURCED_WRITES_IV",
153		"BriefDescription": "L1D On-Drawer L3 Sourced Writes with Intervention",
154		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache with intervention."
155	},
156	{
157		"Unit": "CPU-M-CF",
158		"EventCode": "151",
159		"EventName": "L1D_ONDRAWER_L3_SOURCED_WRITES",
160		"BriefDescription": "L1D On-Drawer L3 Sourced Writes",
161		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache without intervention."
162	},
163	{
164		"Unit": "CPU-M-CF",
165		"EventCode": "152",
166		"EventName": "L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES",
167		"BriefDescription": "L1D Off-Drawer Same-Column L4 Sourced Writes",
168		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-4 cache."
169	},
170	{
171		"Unit": "CPU-M-CF",
172		"EventCode": "153",
173		"EventName": "L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV",
174		"BriefDescription": "L1D Off-Drawer Same-Column L3 Sourced Writes with Intervention",
175		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache with intervention."
176	},
177	{
178		"Unit": "CPU-M-CF",
179		"EventCode": "154",
180		"EventName": "L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES",
181		"BriefDescription": "L1D Off-Drawer Same-Column L3 Sourced Writes",
182		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache without intervention."
183	},
184	{
185		"Unit": "CPU-M-CF",
186		"EventCode": "155",
187		"EventName": "L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES",
188		"BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes",
189		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-4 cache."
190	},
191	{
192		"Unit": "CPU-M-CF",
193		"EventCode": "156",
194		"EventName": "L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV",
195		"BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes with Intervention",
196		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache with intervention."
197	},
198	{
199		"Unit": "CPU-M-CF",
200		"EventCode": "157",
201		"EventName": "L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES",
202		"BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes",
203		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache without intervention."
204	},
205	{
206		"Unit": "CPU-M-CF",
207		"EventCode": "158",
208		"EventName": "L1D_ONNODE_MEM_SOURCED_WRITES",
209		"BriefDescription": "L1D On-Node Memory Sourced Writes",
210		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Node memory."
211	},
212	{
213		"Unit": "CPU-M-CF",
214		"EventCode": "159",
215		"EventName": "L1D_ONDRAWER_MEM_SOURCED_WRITES",
216		"BriefDescription": "L1D On-Drawer Memory Sourced Writes",
217		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer memory."
218	},
219	{
220		"Unit": "CPU-M-CF",
221		"EventCode": "160",
222		"EventName": "L1D_OFFDRAWER_MEM_SOURCED_WRITES",
223		"BriefDescription": "L1D Off-Drawer Memory Sourced Writes",
224		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory."
225	},
226	{
227		"Unit": "CPU-M-CF",
228		"EventCode": "161",
229		"EventName": "L1D_ONCHIP_MEM_SOURCED_WRITES",
230		"BriefDescription": "L1D On-Chip Memory Sourced Writes",
231		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory."
232	},
233	{
234		"Unit": "CPU-M-CF",
235		"EventCode": "162",
236		"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
237		"BriefDescription": "L1I On-Chip L3 Sourced Writes",
238		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention."
239	},
240	{
241		"Unit": "CPU-M-CF",
242		"EventCode": "163",
243		"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV",
244		"BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention",
245		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache with intervention."
246	},
247	{
248		"Unit": "CPU-M-CF",
249		"EventCode": "164",
250		"EventName": "L1I_ONNODE_L4_SOURCED_WRITES",
251		"BriefDescription": "L1I On-Chip L4 Sourced Writes",
252		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-4 cache."
253	},
254	{
255		"Unit": "CPU-M-CF",
256		"EventCode": "165",
257		"EventName": "L1I_ONNODE_L3_SOURCED_WRITES_IV",
258		"BriefDescription": "L1I On-Node L3 Sourced Writes with Intervention",
259		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-3 cache with intervention."
260	},
261	{
262		"Unit": "CPU-M-CF",
263		"EventCode": "166",
264		"EventName": "L1I_ONNODE_L3_SOURCED_WRITES",
265		"BriefDescription": "L1I On-Node L3 Sourced Writes",
266		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-3 cache without intervention."
267	},
268	{
269		"Unit": "CPU-M-CF",
270		"EventCode": "167",
271		"EventName": "L1I_ONDRAWER_L4_SOURCED_WRITES",
272		"BriefDescription": "L1I On-Drawer L4 Sourced Writes",
273		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-4 cache."
274	},
275	{
276		"Unit": "CPU-M-CF",
277		"EventCode": "168",
278		"EventName": "L1I_ONDRAWER_L3_SOURCED_WRITES_IV",
279		"BriefDescription": "L1I On-Drawer L3 Sourced Writes with Intervention",
280		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache with intervention."
281	},
282	{
283		"Unit": "CPU-M-CF",
284		"EventCode": "169",
285		"EventName": "L1I_ONDRAWER_L3_SOURCED_WRITES",
286		"BriefDescription": "L1I On-Drawer L3 Sourced Writes",
287		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache without intervention."
288	},
289	{
290		"Unit": "CPU-M-CF",
291		"EventCode": "170",
292		"EventName": "L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES",
293		"BriefDescription": "L1I Off-Drawer Same-Column L4 Sourced Writes",
294		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-4 cache."
295	},
296	{
297		"Unit": "CPU-M-CF",
298		"EventCode": "171",
299		"EventName": "L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV",
300		"BriefDescription": "L1I Off-Drawer Same-Column L3 Sourced Writes with Intervention",
301		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache with intervention."
302	},
303	{
304		"Unit": "CPU-M-CF",
305		"EventCode": "172",
306		"EventName": "L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES",
307		"BriefDescription": "L1I Off-Drawer Same-Column L3 Sourced Writes",
308		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache without intervention."
309	},
310	{
311		"Unit": "CPU-M-CF",
312		"EventCode": "173",
313		"EventName": "L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES",
314		"BriefDescription": "L1I Off-Drawer Far-Column L4 Sourced Writes",
315		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-4 cache."
316	},
317	{
318		"Unit": "CPU-M-CF",
319		"EventCode": "174",
320		"EventName": "L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV",
321		"BriefDescription": "L1I Off-Drawer Far-Column L3 Sourced Writes with Intervention",
322		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache with intervention."
323	},
324	{
325		"Unit": "CPU-M-CF",
326		"EventCode": "175",
327		"EventName": "L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES",
328		"BriefDescription": "L1I Off-Drawer Far-Column L3 Sourced Writes",
329		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache without intervention."
330	},
331	{
332		"Unit": "CPU-M-CF",
333		"EventCode": "176",
334		"EventName": "L1I_ONNODE_MEM_SOURCED_WRITES",
335		"BriefDescription": "L1I On-Node Memory Sourced Writes",
336		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Node memory."
337	},
338	{
339		"Unit": "CPU-M-CF",
340		"EventCode": "177",
341		"EventName": "L1I_ONDRAWER_MEM_SOURCED_WRITES",
342		"BriefDescription": "L1I On-Drawer Memory Sourced Writes",
343		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory."
344	},
345	{
346		"Unit": "CPU-M-CF",
347		"EventCode": "178",
348		"EventName": "L1I_OFFDRAWER_MEM_SOURCED_WRITES",
349		"BriefDescription": "L1I Off-Drawer Memory Sourced Writes",
350		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory."
351	},
352	{
353		"Unit": "CPU-M-CF",
354		"EventCode": "179",
355		"EventName": "L1I_ONCHIP_MEM_SOURCED_WRITES",
356		"BriefDescription": "L1I On-Chip Memory Sourced Writes",
357		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Chip memory."
358	},
359	{
360		"Unit": "CPU-M-CF",
361		"EventCode": "218",
362		"EventName": "TX_NC_TABORT",
363		"BriefDescription": "Aborted transactions in non-constrained TX mode",
364		"PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode."
365	},
366	{
367		"Unit": "CPU-M-CF",
368		"EventCode": "219",
369		"EventName": "TX_C_TABORT_NO_SPECIAL",
370		"BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic",
371		"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete."
372	},
373	{
374		"Unit": "CPU-M-CF",
375		"EventCode": "220",
376		"EventName": "TX_C_TABORT_SPECIAL",
377		"BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
378		"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete."
379	},
380	{
381		"Unit": "CPU-M-CF",
382		"EventCode": "448",
383		"EventName": "MT_DIAG_CYCLES_ONE_THR_ACTIVE",
384		"BriefDescription": "Cycle count with one thread active",
385		"PublicDescription": "Cycle count with one thread active"
386	},
387	{
388		"Unit": "CPU-M-CF",
389		"EventCode": "449",
390		"EventName": "MT_DIAG_CYCLES_TWO_THR_ACTIVE",
391		"BriefDescription": "Cycle count with two threads active",
392		"PublicDescription": "Cycle count with two threads active"
393	}
394]
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