memory.json

 1[
 2  {
 3    "EventName": "ICACHE_MISS",
 4    "EventCode": "0x102",
 5    "BriefDescription": "Counts instruction cache misses"
 6  },
 7  {
 8    "EventName": "DCACHE_MISS",
 9    "EventCode": "0x202",
10    "BriefDescription": "Counts data cache misses"
11  },
12  {
13    "EventName": "DCACHE_RELEASE",
14    "EventCode": "0x402",
15    "BriefDescription": "Counts writeback requests from the data cache"
16  },
17  {
18    "EventName": "ITLB_MISS",
19    "EventCode": "0x802",
20    "BriefDescription": "Counts Instruction TLB misses caused by instruction address translation requests"
21  },
22  {
23    "EventName": "DTLB_MISS",
24    "EventCode": "0x1002",
25    "BriefDescription": "Counts Data TLB misses caused by data address translation requests"
26  },
27  {
28    "EventName": "UTLB_MISS",
29    "EventCode": "0x2002",
30    "BriefDescription": "Counts Unified TLB misses caused by address translation requests"
31  },
32  {
33    "EventName": "UTLB_HIT",
34    "EventCode": "0x4002",
35    "BriefDescription": "Counts Unified TLB hits for address translation requests"
36  },
37  {
38    "EventName": "PTE_CACHE_MISS",
39    "EventCode": "0x8002",
40    "BriefDescription": "Counts Page Table Entry cache misses"
41  },
42  {
43    "EventName": "PTE_CACHE_HIT",
44    "EventCode": "0x10002",
45    "BriefDescription": "Counts Page Table Entry cache hits"
46  },
47  {
48    "EventName": "ITLB_MULTI_HIT",
49    "EventCode": "0x20002",
50    "BriefDescription": "Counts Instruction TLB multi-hits"
51  },
52  {
53    "EventName": "DTLB_MULTI_HIT",
54    "EventCode": "0x40002",
55    "BriefDescription": "Counts Data TLB multi-hits"
56  }
57]