microarch.json

 1[
 2  {
 3    "EventName": "ADDRESSGEN_INTERLOCK",
 4    "EventCode": "0x101",
 5    "BriefDescription": "Counts cycles with an address-generation interlock"
 6  },
 7  {
 8    "EventName": "LONGLATENCY_INTERLOCK",
 9    "EventCode": "0x201",
10    "BriefDescription": "Counts cycles with a long-latency interlock"
11  },
12  {
13    "EventName": "CSR_INTERLOCK",
14    "EventCode": "0x401",
15    "BriefDescription": "Counts cycles with a CSR interlock"
16  },
17  {
18    "EventName": "ICACHE_BLOCKED",
19    "EventCode": "0x801",
20    "BriefDescription": "Counts cycles in which the instruction cache was not able to provide an instruction"
21  },
22  {
23    "EventName": "DCACHE_BLOCKED",
24    "EventCode": "0x1001",
25    "BriefDescription": "Counts cycles in which the data cache blocked an instruction"
26  },
27  {
28    "EventName": "BRANCH_DIRECTION_MISPREDICTION",
29    "EventCode": "0x2001",
30    "BriefDescription": "Counts mispredictions of conditional branch direction (taken/not taken)"
31  },
32  {
33    "EventName": "BRANCH_TARGET_MISPREDICTION",
34    "EventCode": "0x4001",
35    "BriefDescription": "Counts mispredictions of the target PC of control-flow instructions"
36  },
37  {
38    "EventName": "PIPELINE_FLUSH",
39    "EventCode": "0x8001",
40    "BriefDescription": "Counts flushes of the core pipeline. Common causes include fence.i and CSR accesses"
41  },
42  {
43    "EventName": "REPLAY",
44    "EventCode": "0x10001",
45    "BriefDescription": "Counts instruction replays"
46  },
47  {
48    "EventName": "INTEGER_MUL_DIV_INTERLOCK",
49    "EventCode": "0x20001",
50    "BriefDescription": "Counts cycles with a multiply or divide interlock"
51  },
52  {
53    "EventName": "FP_INTERLOCK",
54    "EventCode": "0x40001",
55    "BriefDescription": "Counts cycles with a floating-point interlock"
56  }
57]