datasource.json

   1[
   2  {
   3    "EventCode": "0x1505E",
   4    "EventName": "PM_LD_HIT_L1",
   5    "BriefDescription": "Load  finished without experiencing an L1 miss."
   6  },
   7  {
   8    "EventCode": "0x100FC",
   9    "EventName": "PM_LD_REF_L1",
  10    "BriefDescription": "All L1 D cache load references counted at finish, gated by reject. In P9 and earlier this event counted only cacheable loads but in P10 both cacheable and non-cacheable loads are included."
  11  },
  12  {
  13    "EventCode": "0x200FE",
  14    "EventName": "PM_DATA_FROM_L2MISS",
  15    "BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss."
  16  },
  17  {
  18    "EventCode": "0x300FE",
  19    "EventName": "PM_DATA_FROM_L3MISS",
  20    "BriefDescription": "The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss."
  21  },
  22  {
  23    "EventCode": "0x400F0",
  24    "EventName": "PM_LD_DEMAND_MISS_L1_FIN",
  25    "BriefDescription": "Load missed L1, counted at finish time."
  26  },
  27  {
  28    "EventCode": "0x400FE",
  29    "EventName": "PM_DATA_FROM_MEMORY",
  30    "BriefDescription": "The processor's data cache was reloaded from local, remote, or distant memory due to a demand miss."
  31  },
  32  {
  33    "EventCode": "0x0000004080",
  34    "EventName": "PM_INST_FROM_L1",
  35    "BriefDescription": "An instruction fetch hit in the L1. Each fetch group contains 8 instructions. The same line can hit 4 times if 32 sequential instructions are fetched."
  36  },
  37  {
  38    "EventCode": "0x000000026080",
  39    "EventName": "PM_L2_LD_MISS",
  40    "BriefDescription": "All successful D-Side Load dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2."
  41  },
  42  {
  43    "EventCode": "0x000000026880",
  44    "EventName": "PM_L2_ST_MISS",
  45    "BriefDescription": "All successful D-Side Store dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2."
  46  },
  47  {
  48    "EventCode": "0x010000046880",
  49    "EventName": "PM_L2_ST_HIT",
  50    "BriefDescription": "All successful D-side store dispatches for this thread that were L2 hits. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2."
  51  },
  52  {
  53    "EventCode": "0x000000036880",
  54    "EventName": "PM_L2_INST_MISS",
  55    "BriefDescription": "All successful instruction (demand and prefetch) dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2."
  56  },
  57  {
  58    "EventCode": "0x000300000000C040",
  59    "EventName": "PM_INST_FROM_L2",
  60    "BriefDescription": "The processor's instruction cache was reloaded from the local core's L2 due to a demand miss."
  61  },
  62  {
  63    "EventCode": "0x000340000000C040",
  64    "EventName": "PM_DATA_FROM_L2",
  65    "BriefDescription": "The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss."
  66  },
  67  {
  68    "EventCode": "0x000300000010C040",
  69    "EventName": "PM_INST_FROM_L2_ALL",
  70    "BriefDescription": "The processor's instruction cache was reloaded from the local core's L2 due to a demand miss or prefetch reload."
  71  },
  72  {
  73    "EventCode": "0x000340000020C040",
  74    "EventName": "PM_DATA_FROM_L2_ALL",
  75    "BriefDescription": "The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss or prefetch reload."
  76  },
  77  {
  78    "EventCode": "0x003F00000000C040",
  79    "EventName": "PM_INST_FROM_L1MISS",
  80    "BriefDescription": "The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss."
  81  },
  82  {
  83    "EventCode": "0x003F40000000C040",
  84    "EventName": "PM_DATA_FROM_L1MISS",
  85    "BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss."
  86  },
  87  {
  88    "EventCode": "0x003F00000010C040",
  89    "EventName": "PM_INST_FROM_L1MISS_ALL",
  90    "BriefDescription": "The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload."
  91  },
  92  {
  93    "EventCode": "0x003F40000020C040",
  94    "EventName": "PM_DATA_FROM_L1MISS_ALL",
  95    "BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload."
  96  },
  97  {
  98    "EventCode": "0x000040000000C040",
  99    "EventName": "PM_DATA_FROM_L2_NO_CONFLICT",
 100    "BriefDescription": "The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss."
 101  },
 102  {
 103    "EventCode": "0x000040000020C040",
 104    "EventName": "PM_DATA_FROM_L2_NO_CONFLICT_ALL",
 105    "BriefDescription": "The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload."
 106  },
 107  {
 108    "EventCode": "0x004040000000C040",
 109    "EventName": "PM_DATA_FROM_L2_MEPF",
 110    "BriefDescription": "The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss."
 111  },
 112  {
 113    "EventCode": "0x004040000020C040",
 114    "EventName": "PM_DATA_FROM_L2_MEPF_ALL",
 115    "BriefDescription": "The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload."
 116  },
 117  {
 118    "EventCode": "0x008040000000C040",
 119    "EventName": "PM_DATA_FROM_L2_LDHITST_CONFLICT",
 120    "BriefDescription": "The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss."
 121  },
 122  {
 123    "EventCode": "0x008040000020C040",
 124    "EventName": "PM_DATA_FROM_L2_LDHITST_CONFLICT_ALL",
 125    "BriefDescription": "The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload."
 126  },
 127  {
 128    "EventCode": "0x00C040000000C040",
 129    "EventName": "PM_DATA_FROM_L2_OTHER_CONFLICT",
 130    "BriefDescription": "The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss."
 131  },
 132  {
 133    "EventCode": "0x00C040000020C040",
 134    "EventName": "PM_DATA_FROM_L2_OTHER_CONFLICT_ALL",
 135    "BriefDescription": "The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload."
 136  },
 137  {
 138    "EventCode": "0x000380000000C040",
 139    "EventName": "PM_INST_FROM_L2MISS",
 140    "BriefDescription": "The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss."
 141  },
 142  {
 143    "EventCode": "0x0003C0000000C040",
 144    "EventName": "PM_DATA_FROM_L2MISS_DSRC",
 145    "BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss."
 146  },
 147  {
 148    "EventCode": "0x000380000010C040",
 149    "EventName": "PM_INST_FROM_L2MISS_ALL",
 150    "BriefDescription": "The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload."
 151  },
 152  {
 153    "EventCode": "0x0003C0000020C040",
 154    "EventName": "PM_DATA_FROM_L2MISS_ALL",
 155    "BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload."
 156  },
 157  {
 158    "EventCode": "0x010300000000C040",
 159    "EventName": "PM_INST_FROM_L3",
 160    "BriefDescription": "The processor's instruction cache was reloaded from the local core's L3 due to a demand miss."
 161  },
 162  {
 163    "EventCode": "0x010340000000C040",
 164    "EventName": "PM_DATA_FROM_L3",
 165    "BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss."
 166  },
 167  {
 168    "EventCode": "0x010300000010C040",
 169    "EventName": "PM_INST_FROM_L3_ALL",
 170    "BriefDescription": "The processor's instruction cache was reloaded from the local core's L3 due to a demand miss or prefetch reload."
 171  },
 172  {
 173    "EventCode": "0x010340000020C040",
 174    "EventName": "PM_DATA_FROM_L3_ALL",
 175    "BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload."
 176  },
 177  {
 178    "EventCode": "0x010040000000C040",
 179    "EventName": "PM_DATA_FROM_L3_NO_CONFLICT",
 180    "BriefDescription": "The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss."
 181  },
 182  {
 183    "EventCode": "0x010040000020C040",
 184    "EventName": "PM_DATA_FROM_L3_NO_CONFLICT_ALL",
 185    "BriefDescription": "The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload."
 186  },
 187  {
 188    "EventCode": "0x014040000000C040",
 189    "EventName": "PM_DATA_FROM_L3_MEPF",
 190    "BriefDescription": "The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss."
 191  },
 192  {
 193    "EventCode": "0x014040000020C040",
 194    "EventName": "PM_DATA_FROM_L3_MEPF_ALL",
 195    "BriefDescription": "The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload."
 196  },
 197  {
 198    "EventCode": "0x01C040000000C040",
 199    "EventName": "PM_DATA_FROM_L3_CONFLICT",
 200    "BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss."
 201  },
 202  {
 203    "EventCode": "0x01C040000020C040",
 204    "EventName": "PM_DATA_FROM_L3_CONFLICT_ALL",
 205    "BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload."
 206  },
 207  {
 208    "EventCode": "0x000780000000C040",
 209    "EventName": "PM_INST_FROM_L3MISS_DSRC",
 210    "BriefDescription": "The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss."
 211  },
 212  {
 213    "EventCode": "0x0007C0000000C040",
 214    "EventName": "PM_DATA_FROM_L3MISS_DSRC",
 215    "BriefDescription": "The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss."
 216  },
 217  {
 218    "EventCode": "0x000780000010C040",
 219    "EventName": "PM_INST_FROM_L3MISS_ALL",
 220    "BriefDescription": "The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload."
 221  },
 222  {
 223    "EventCode": "0x0007C0000020C040",
 224    "EventName": "PM_DATA_FROM_L3MISS_ALL",
 225    "BriefDescription": "The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload."
 226  },
 227  {
 228    "EventCode": "0x080040000000C040",
 229    "EventName": "PM_DATA_FROM_L21_REGENT_SHR",
 230    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss."
 231  },
 232  {
 233    "EventCode": "0x080040000020C040",
 234    "EventName": "PM_DATA_FROM_L21_REGENT_SHR_ALL",
 235    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload."
 236  },
 237  {
 238    "EventCode": "0x084040000000C040",
 239    "EventName": "PM_DATA_FROM_L21_REGENT_MOD",
 240    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss."
 241  },
 242  {
 243    "EventCode": "0x084040000020C040",
 244    "EventName": "PM_DATA_FROM_L21_REGENT_MOD_ALL",
 245    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload."
 246  },
 247  {
 248    "EventCode": "0x080100000000C040",
 249    "EventName": "PM_INST_FROM_L21_REGENT",
 250    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss."
 251  },
 252  {
 253    "EventCode": "0x080140000000C040",
 254    "EventName": "PM_DATA_FROM_L21_REGENT",
 255    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss."
 256  },
 257  {
 258    "EventCode": "0x080100000010C040",
 259    "EventName": "PM_INST_FROM_L21_REGENT_ALL",
 260    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload."
 261  },
 262  {
 263    "EventCode": "0x080140000020C040",
 264    "EventName": "PM_DATA_FROM_L21_REGENT_ALL",
 265    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload."
 266  },
 267  {
 268    "EventCode": "0x088040000000C040",
 269    "EventName": "PM_DATA_FROM_L31_REGENT_SHR",
 270    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss."
 271  },
 272  {
 273    "EventCode": "0x088040000020C040",
 274    "EventName": "PM_DATA_FROM_L31_REGENT_SHR_ALL",
 275    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload."
 276  },
 277  {
 278    "EventCode": "0x08C040000000C040",
 279    "EventName": "PM_DATA_FROM_L31_REGENT_MOD",
 280    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss."
 281  },
 282  {
 283    "EventCode": "0x08C040000020C040",
 284    "EventName": "PM_DATA_FROM_L31_REGENT_MOD_ALL",
 285    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload."
 286  },
 287  {
 288    "EventCode": "0x088100000000C040",
 289    "EventName": "PM_INST_FROM_L31_REGENT",
 290    "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss."
 291  },
 292  {
 293    "EventCode": "0x088140000000C040",
 294    "EventName": "PM_DATA_FROM_L31_REGENT",
 295    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss."
 296  },
 297  {
 298    "EventCode": "0x088100000010C040",
 299    "EventName": "PM_INST_FROM_L31_REGENT_ALL",
 300    "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload."
 301  },
 302  {
 303    "EventCode": "0x088140000020C040",
 304    "EventName": "PM_DATA_FROM_L31_REGENT_ALL",
 305    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload."
 306  },
 307  {
 308    "EventCode": "0x080240000000C040",
 309    "EventName": "PM_DATA_FROM_REGENT_L2L3_SHR",
 310    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss."
 311  },
 312  {
 313    "EventCode": "0x080240000020C040",
 314    "EventName": "PM_DATA_FROM_REGENT_L2L3_SHR_ALL",
 315    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload."
 316  },
 317  {
 318    "EventCode": "0x084240000000C040",
 319    "EventName": "PM_DATA_FROM_REGENT_L2L3_MOD",
 320    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss."
 321  },
 322  {
 323    "EventCode": "0x084240000020C040",
 324    "EventName": "PM_DATA_FROM_REGENT_L2L3_MOD_ALL",
 325    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload."
 326  },
 327  {
 328    "EventCode": "0x080300000000C040",
 329    "EventName": "PM_INST_FROM_REGENT_L2L3",
 330    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss."
 331  },
 332  {
 333    "EventCode": "0x080340000000C040",
 334    "EventName": "PM_DATA_FROM_REGENT_L2L3",
 335    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss."
 336  },
 337  {
 338    "EventCode": "0x080300000010C040",
 339    "EventName": "PM_INST_FROM_REGENT_L2L3_ALL",
 340    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload."
 341  },
 342  {
 343    "EventCode": "0x080340000020C040",
 344    "EventName": "PM_DATA_FROM_REGENT_L2L3_ALL",
 345    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload."
 346  },
 347  {
 348    "EventCode": "0x0A0040000000C040",
 349    "EventName": "PM_DATA_FROM_L21_NON_REGENT_SHR",
 350    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss."
 351  },
 352  {
 353    "EventCode": "0x0A0040000020C040",
 354    "EventName": "PM_DATA_FROM_L21_NON_REGENT_SHR_ALL",
 355    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload."
 356  },
 357  {
 358    "EventCode": "0x0A4040000000C040",
 359    "EventName": "PM_DATA_FROM_L21_NON_REGENT_MOD",
 360    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss."
 361  },
 362  {
 363    "EventCode": "0x0A4040000020C040",
 364    "EventName": "PM_DATA_FROM_L21_NON_REGENT_MOD_ALL",
 365    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload."
 366  },
 367  {
 368    "EventCode": "0x0A0100000000C040",
 369    "EventName": "PM_INST_FROM_L21_NON_REGENT",
 370    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss."
 371  },
 372  {
 373    "EventCode": "0x0A0140000000C040",
 374    "EventName": "PM_DATA_FROM_L21_NON_REGENT",
 375    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss."
 376  },
 377  {
 378    "EventCode": "0x0A0100000010C040",
 379    "EventName": "PM_INST_FROM_L21_NON_REGENT_ALL",
 380    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload."
 381  },
 382  {
 383    "EventCode": "0x0A0140000020C040",
 384    "EventName": "PM_DATA_FROM_L21_NON_REGENT_ALL",
 385    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload."
 386  },
 387  {
 388    "EventCode": "0x0A8040000000C040",
 389    "EventName": "PM_DATA_FROM_L31_NON_REGENT_SHR",
 390    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss."
 391  },
 392  {
 393    "EventCode": "0x0A8040000020C040",
 394    "EventName": "PM_DATA_FROM_L31_NON_REGENT_SHR_ALL",
 395    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload."
 396  },
 397  {
 398    "EventCode": "0x0AC040000000C040",
 399    "EventName": "PM_DATA_FROM_L31_NON_REGENT_MOD",
 400    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss."
 401  },
 402  {
 403    "EventCode": "0x0AC040000020C040",
 404    "EventName": "PM_DATA_FROM_L31_NON_REGENT_MOD_ALL",
 405    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload."
 406  },
 407  {
 408    "EventCode": "0x0A8100000000C040",
 409    "EventName": "PM_INST_FROM_L31_NON_REGENT",
 410    "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss."
 411  },
 412  {
 413    "EventCode": "0x0A8140000000C040",
 414    "EventName": "PM_DATA_FROM_L31_NON_REGENT",
 415    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss."
 416  },
 417  {
 418    "EventCode": "0x0A8100000010C040",
 419    "EventName": "PM_INST_FROM_L31_NON_REGENT_ALL",
 420    "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload."
 421  },
 422  {
 423    "EventCode": "0x0A8140000020C040",
 424    "EventName": "PM_DATA_FROM_L31_NON_REGENT_ALL",
 425    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload."
 426  },
 427  {
 428    "EventCode": "0x0A0240000000C040",
 429    "EventName": "PM_DATA_FROM_NON_REGENT_L2L3_SHR",
 430    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss."
 431  },
 432  {
 433    "EventCode": "0x0A0240000020C040",
 434    "EventName": "PM_DATA_FROM_NON_REGENT_L2L3_SHR_ALL",
 435    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload."
 436  },
 437  {
 438    "EventCode": "0x0A4240000000C040",
 439    "EventName": "PM_DATA_FROM_NON_REGENT_L2L3_MOD",
 440    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss."
 441  },
 442  {
 443    "EventCode": "0x0A4240000020C040",
 444    "EventName": "PM_DATA_FROM_NON_REGENT_L2L3_MOD_ALL",
 445    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload."
 446  },
 447  {
 448    "EventCode": "0x0A0300000000C040",
 449    "EventName": "PM_INST_FROM_NON_REGENT_L2L3",
 450    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss."
 451  },
 452  {
 453    "EventCode": "0x0A0340000000C040",
 454    "EventName": "PM_DATA_FROM_NON_REGENT_L2L3",
 455    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss."
 456  },
 457  {
 458    "EventCode": "0x0A0300000010C040",
 459    "EventName": "PM_INST_FROM_NON_REGENT_L2L3_ALL",
 460    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload."
 461  },
 462  {
 463    "EventCode": "0x0A0340000020C040",
 464    "EventName": "PM_DATA_FROM_NON_REGENT_L2L3_ALL",
 465    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload."
 466  },
 467  {
 468    "EventCode": "0x094100000000C040",
 469    "EventName": "PM_INST_FROM_LMEM",
 470    "BriefDescription": "The processor's instruction cache was reloaded from the local chip's memory due to a demand miss."
 471  },
 472  {
 473    "EventCode": "0x094040000000C040",
 474    "EventName": "PM_DATA_FROM_LMEM",
 475    "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss."
 476  },
 477  {
 478    "EventCode": "0x094100000010C040",
 479    "EventName": "PM_INST_FROM_LMEM_ALL",
 480    "BriefDescription": "The processor's instruction cache was reloaded from the local chip's memory due to a demand miss or prefetch reload."
 481  },
 482  {
 483    "EventCode": "0x094040000020C040",
 484    "EventName": "PM_DATA_FROM_LMEM_ALL",
 485    "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss or prefetch reload."
 486  },
 487  {
 488    "EventCode": "0x098040000000C040",
 489    "EventName": "PM_DATA_FROM_L_OC_CACHE",
 490    "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI cache due to a demand miss."
 491  },
 492  {
 493    "EventCode": "0x098040000020C040",
 494    "EventName": "PM_DATA_FROM_L_OC_CACHE_ALL",
 495    "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI cache due to a demand miss or prefetch reload."
 496  },
 497  {
 498    "EventCode": "0x09C040000000C040",
 499    "EventName": "PM_DATA_FROM_L_OC_MEM",
 500    "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI memory due to a demand miss."
 501  },
 502  {
 503    "EventCode": "0x09C040000020C040",
 504    "EventName": "PM_DATA_FROM_L_OC_MEM_ALL",
 505    "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI memory due to a demand miss or prefetch reload."
 506  },
 507  {
 508    "EventCode": "0x098100000000C040",
 509    "EventName": "PM_INST_FROM_L_OC_ANY",
 510    "BriefDescription": "The processor's instruction cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss."
 511  },
 512  {
 513    "EventCode": "0x098140000000C040",
 514    "EventName": "PM_DATA_FROM_L_OC_ANY",
 515    "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss."
 516  },
 517  {
 518    "EventCode": "0x098100000010C040",
 519    "EventName": "PM_INST_FROM_L_OC_ANY_ALL",
 520    "BriefDescription": "The processor's instruction cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss or prefetch reload."
 521  },
 522  {
 523    "EventCode": "0x098140000020C040",
 524    "EventName": "PM_DATA_FROM_L_OC_ANY_ALL",
 525    "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss or prefetch reload."
 526  },
 527  {
 528    "EventCode": "0x0C0040000000C040",
 529    "EventName": "PM_DATA_FROM_RL2_SHR",
 530    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss."
 531  },
 532  {
 533    "EventCode": "0x0C0040000020C040",
 534    "EventName": "PM_DATA_FROM_RL2_SHR_ALL",
 535    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload."
 536  },
 537  {
 538    "EventCode": "0x0C4040000000C040",
 539    "EventName": "PM_DATA_FROM_RL2_MOD",
 540    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss."
 541  },
 542  {
 543    "EventCode": "0x0C4040000020C040",
 544    "EventName": "PM_DATA_FROM_RL2_MOD_ALL",
 545    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload."
 546  },
 547  {
 548    "EventCode": "0x0C0100000000C040",
 549    "EventName": "PM_INST_FROM_RL2",
 550    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss."
 551  },
 552  {
 553    "EventCode": "0x0C0140000000C040",
 554    "EventName": "PM_DATA_FROM_RL2",
 555    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss."
 556  },
 557  {
 558    "EventCode": "0x0C0100000010C040",
 559    "EventName": "PM_INST_FROM_RL2_ALL",
 560    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload."
 561  },
 562  {
 563    "EventCode": "0x0C0140000020C040",
 564    "EventName": "PM_DATA_FROM_RL2_ALL",
 565    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload."
 566  },
 567  {
 568    "EventCode": "0x0C8040000000C040",
 569    "EventName": "PM_DATA_FROM_RL3_SHR",
 570    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss."
 571  },
 572  {
 573    "EventCode": "0x0C8040000020C040",
 574    "EventName": "PM_DATA_FROM_RL3_SHR_ALL",
 575    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload."
 576  },
 577  {
 578    "EventCode": "0x0CC040000000C040",
 579    "EventName": "PM_DATA_FROM_RL3_MOD",
 580    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss."
 581  },
 582  {
 583    "EventCode": "0x0CC040000020C040",
 584    "EventName": "PM_DATA_FROM_RL3_MOD_ALL",
 585    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload."
 586  },
 587  {
 588    "EventCode": "0x0C8100000000C040",
 589    "EventName": "PM_INST_FROM_RL3",
 590    "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss."
 591  },
 592  {
 593    "EventCode": "0x0C8140000000C040",
 594    "EventName": "PM_DATA_FROM_RL3",
 595    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss."
 596  },
 597  {
 598    "EventCode": "0x0C8100000010C040",
 599    "EventName": "PM_INST_FROM_RL3_ALL",
 600    "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload."
 601  },
 602  {
 603    "EventCode": "0x0C8140000020C040",
 604    "EventName": "PM_DATA_FROM_RL3_ALL",
 605    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload."
 606  },
 607  {
 608    "EventCode": "0x0C0240000000C040",
 609    "EventName": "PM_DATA_FROM_RL2L3_SHR",
 610    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss."
 611  },
 612  {
 613    "EventCode": "0x0C0240000020C040",
 614    "EventName": "PM_DATA_FROM_RL2L3_SHR_ALL",
 615    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload."
 616  },
 617  {
 618    "EventCode": "0x0C4240000000C040",
 619    "EventName": "PM_DATA_FROM_RL2L3_MOD",
 620    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss."
 621  },
 622  {
 623    "EventCode": "0x0C4240000020C040",
 624    "EventName": "PM_DATA_FROM_RL2L3_MOD_ALL",
 625    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload."
 626  },
 627  {
 628    "EventCode": "0x0C0300000000C040",
 629    "EventName": "PM_INST_FROM_RL2L3",
 630    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss."
 631  },
 632  {
 633    "EventCode": "0x0C0340000000C040",
 634    "EventName": "PM_DATA_FROM_RL2L3",
 635    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss."
 636  },
 637  {
 638    "EventCode": "0x0C0300000010C040",
 639    "EventName": "PM_INST_FROM_RL2L3_ALL",
 640    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload."
 641  },
 642  {
 643    "EventCode": "0x0C0340000020C040",
 644    "EventName": "PM_DATA_FROM_RL2L3_ALL",
 645    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload."
 646  },
 647  {
 648    "EventCode": "0x0D4100000000C040",
 649    "EventName": "PM_INST_FROM_RMEM",
 650    "BriefDescription": "The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss."
 651  },
 652  {
 653    "EventCode": "0x0D4040000000C040",
 654    "EventName": "PM_DATA_FROM_RMEM",
 655    "BriefDescription": "The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss."
 656  },
 657  {
 658    "EventCode": "0x0D4100000010C040",
 659    "EventName": "PM_INST_FROM_RMEM_ALL",
 660    "BriefDescription": "The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload."
 661  },
 662  {
 663    "EventCode": "0x0D4040000020C040",
 664    "EventName": "PM_DATA_FROM_RMEM_ALL",
 665    "BriefDescription": "The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload."
 666  },
 667  {
 668    "EventCode": "0x0D8040000000C040",
 669    "EventName": "PM_DATA_FROM_R_OC_CACHE",
 670    "BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI cache due to a demand miss."
 671  },
 672  {
 673    "EventCode": "0x0D8040000020C040",
 674    "EventName": "PM_DATA_FROM_R_OC_CACHE_ALL",
 675    "BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI cache due to a demand miss or prefetch reload."
 676  },
 677  {
 678    "EventCode": "0x0DC040000000C040",
 679    "EventName": "PM_DATA_FROM_R_OC_MEM",
 680    "BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI memory due to a demand miss."
 681  },
 682  {
 683    "EventCode": "0x0DC040000020C040",
 684    "EventName": "PM_DATA_FROM_R_OC_MEM_ALL",
 685    "BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI memory due to a demand miss or prefetch reload."
 686  },
 687  {
 688    "EventCode": "0x0D8100000000C040",
 689    "EventName": "PM_INST_FROM_R_OC_ANY",
 690    "BriefDescription": "The processor's instruction cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss."
 691  },
 692  {
 693    "EventCode": "0x0D8140000000C040",
 694    "EventName": "PM_DATA_FROM_R_OC_ANY",
 695    "BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss."
 696  },
 697  {
 698    "EventCode": "0x0D8100000010C040",
 699    "EventName": "PM_INST_FROM_R_OC_ANY_ALL",
 700    "BriefDescription": "The processor's instruction cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss or prefetch reload."
 701  },
 702  {
 703    "EventCode": "0x0D8140000020C040",
 704    "EventName": "PM_DATA_FROM_R_OC_ANY_ALL",
 705    "BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss or prefetch reload."
 706  },
 707  {
 708    "EventCode": "0x0E0040000000C040",
 709    "EventName": "PM_DATA_FROM_DL2_SHR",
 710    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss."
 711  },
 712  {
 713    "EventCode": "0x0E0040000020C040",
 714    "EventName": "PM_DATA_FROM_DL2_SHR_ALL",
 715    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload."
 716  },
 717  {
 718    "EventCode": "0x0E4040000000C040",
 719    "EventName": "PM_DATA_FROM_DL2_MOD",
 720    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss."
 721  },
 722  {
 723    "EventCode": "0x0E4040000020C040",
 724    "EventName": "PM_DATA_FROM_DL2_MOD_ALL",
 725    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload."
 726  },
 727  {
 728    "EventCode": "0x0E0100000000C040",
 729    "EventName": "PM_INST_FROM_DL2",
 730    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss."
 731  },
 732  {
 733    "EventCode": "0x0E0140000000C040",
 734    "EventName": "PM_DATA_FROM_DL2",
 735    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss."
 736  },
 737  {
 738    "EventCode": "0x0E0100000010C040",
 739    "EventName": "PM_INST_FROM_DL2_ALL",
 740    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload."
 741  },
 742  {
 743    "EventCode": "0x0E0140000020C040",
 744    "EventName": "PM_DATA_FROM_DL2_ALL",
 745    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload."
 746  },
 747  {
 748    "EventCode": "0x0E8040000000C040",
 749    "EventName": "PM_DATA_FROM_DL3_SHR",
 750    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss."
 751  },
 752  {
 753    "EventCode": "0x0E8040000020C040",
 754    "EventName": "PM_DATA_FROM_DL3_SHR_ALL",
 755    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload."
 756  },
 757  {
 758    "EventCode": "0x0EC040000000C040",
 759    "EventName": "PM_DATA_FROM_DL3_MOD",
 760    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss."
 761  },
 762  {
 763    "EventCode": "0x0EC040000020C040",
 764    "EventName": "PM_DATA_FROM_DL3_MOD_ALL",
 765    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload."
 766  },
 767  {
 768    "EventCode": "0x0E8100000000C040",
 769    "EventName": "PM_INST_FROM_DL3",
 770    "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss."
 771  },
 772  {
 773    "EventCode": "0x0E8140000000C040",
 774    "EventName": "PM_DATA_FROM_DL3",
 775    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss."
 776  },
 777  {
 778    "EventCode": "0x0E8100000010C040",
 779    "EventName": "PM_INST_FROM_DL3_ALL",
 780    "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload."
 781  },
 782  {
 783    "EventCode": "0x0E8140000020C040",
 784    "EventName": "PM_DATA_FROM_DL3_ALL",
 785    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload."
 786  },
 787  {
 788    "EventCode": "0x0E0240000000C040",
 789    "EventName": "PM_DATA_FROM_DL2L3_SHR",
 790    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss."
 791  },
 792  {
 793    "EventCode": "0x0E0240000020C040",
 794    "EventName": "PM_DATA_FROM_DL2L3_SHR_ALL",
 795    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload."
 796  },
 797  {
 798    "EventCode": "0x0E4240000000C040",
 799    "EventName": "PM_DATA_FROM_DL2L3_MOD",
 800    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss."
 801  },
 802  {
 803    "EventCode": "0x0E4240000020C040",
 804    "EventName": "PM_DATA_FROM_DL2L3_MOD_ALL",
 805    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload."
 806  },
 807  {
 808    "EventCode": "0x0E0300000000C040",
 809    "EventName": "PM_INST_FROM_DL2L3",
 810    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss."
 811  },
 812  {
 813    "EventCode": "0x0E0340000000C040",
 814    "EventName": "PM_DATA_FROM_DL2L3",
 815    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss."
 816  },
 817  {
 818    "EventCode": "0x0E0300000010C040",
 819    "EventName": "PM_INST_FROM_DL2L3_ALL",
 820    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload."
 821  },
 822  {
 823    "EventCode": "0x0E0340000020C040",
 824    "EventName": "PM_DATA_FROM_DL2L3_ALL",
 825    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload."
 826  },
 827  {
 828    "EventCode": "0x0F4100000000C040",
 829    "EventName": "PM_INST_FROM_DMEM",
 830    "BriefDescription": "The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss."
 831  },
 832  {
 833    "EventCode": "0x0F4040000000C040",
 834    "EventName": "PM_DATA_FROM_DMEM",
 835    "BriefDescription": "The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss."
 836  },
 837  {
 838    "EventCode": "0x0F4100000010C040",
 839    "EventName": "PM_INST_FROM_DMEM_ALL",
 840    "BriefDescription": "The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload."
 841  },
 842  {
 843    "EventCode": "0x0F4040000020C040",
 844    "EventName": "PM_DATA_FROM_DMEM_ALL",
 845    "BriefDescription": "The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload."
 846  },
 847  {
 848    "EventCode": "0x0F8040000000C040",
 849    "EventName": "PM_DATA_FROM_D_OC_CACHE",
 850    "BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI cache due to a demand miss."
 851  },
 852  {
 853    "EventCode": "0x0F8040000020C040",
 854    "EventName": "PM_DATA_FROM_D_OC_CACHE_ALL",
 855    "BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI cache due to a demand miss or prefetch reload."
 856  },
 857  {
 858    "EventCode": "0x0FC040000000C040",
 859    "EventName": "PM_DATA_FROM_D_OC_MEM",
 860    "BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI memory due to a demand miss."
 861  },
 862  {
 863    "EventCode": "0x0FC040000020C040",
 864    "EventName": "PM_DATA_FROM_D_OC_MEM_ALL",
 865    "BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI memory due to a demand miss or prefetch reload."
 866  },
 867  {
 868    "EventCode": "0x0F8100000000C040",
 869    "EventName": "PM_INST_FROM_D_OC_ANY",
 870    "BriefDescription": "The processor's instruction cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss."
 871  },
 872  {
 873    "EventCode": "0x0F8140000000C040",
 874    "EventName": "PM_DATA_FROM_D_OC_ANY",
 875    "BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss."
 876  },
 877  {
 878    "EventCode": "0x0F8100000010C040",
 879    "EventName": "PM_INST_FROM_D_OC_ANY_ALL",
 880    "BriefDescription": "The processor's instruction cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss or prefetch reload."
 881  },
 882  {
 883    "EventCode": "0x0F8140000020C040",
 884    "EventName": "PM_DATA_FROM_D_OC_ANY_ALL",
 885    "BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss or prefetch reload."
 886  },
 887  {
 888    "EventCode": "0x080B00000000C040",
 889    "EventName": "PM_INST_FROM_ONCHIP_CACHE",
 890    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss."
 891  },
 892  {
 893    "EventCode": "0x080B40000000C040",
 894    "EventName": "PM_DATA_FROM_ONCHIP_CACHE",
 895    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss."
 896  },
 897  {
 898    "EventCode": "0x080B00000010C040",
 899    "EventName": "PM_INST_FROM_ONCHIP_CACHE_ALL",
 900    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload."
 901  },
 902  {
 903    "EventCode": "0x080B40000020C040",
 904    "EventName": "PM_DATA_FROM_ONCHIP_CACHE_ALL",
 905    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload."
 906  },
 907  {
 908    "EventCode": "0x0C0B00000000C040",
 909    "EventName": "PM_INST_FROM_OFFCHIP_CACHE",
 910    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss."
 911  },
 912  {
 913    "EventCode": "0x0C0B40000000C040",
 914    "EventName": "PM_DATA_FROM_OFFCHIP_CACHE",
 915    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss."
 916  },
 917  {
 918    "EventCode": "0x0C0B00000010C040",
 919    "EventName": "PM_INST_FROM_OFFCHIP_CACHE_ALL",
 920    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload."
 921  },
 922  {
 923    "EventCode": "0x0C0B40000020C040",
 924    "EventName": "PM_DATA_FROM_OFFCHIP_CACHE_ALL",
 925    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload."
 926  },
 927  {
 928    "EventCode": "0x095900000000C040",
 929    "EventName": "PM_INST_FROM_ANY_MEMORY",
 930    "BriefDescription": "The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss."
 931  },
 932  {
 933    "EventCode": "0x095840000000C040",
 934    "EventName": "PM_DATA_FROM_ANY_MEMORY",
 935    "BriefDescription": "The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss."
 936  },
 937  {
 938    "EventCode": "0x095900000010C040",
 939    "EventName": "PM_INST_FROM_ANY_MEMORY_ALL",
 940    "BriefDescription": "The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload."
 941  },
 942  {
 943    "EventCode": "0x095840000020C040",
 944    "EventName": "PM_DATA_FROM_ANY_MEMORY_ALL",
 945    "BriefDescription": "The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload."
 946  },
 947  {
 948    "EventCode": "0x000300000000C142",
 949    "EventName": "PM_MRK_INST_FROM_L2",
 950    "BriefDescription": "The processor's instruction cache was reloaded from the local core's L2 due to a demand miss for a marked instruction."
 951  },
 952  {
 953    "EventCode": "0x000340000000C142",
 954    "EventName": "PM_MRK_DATA_FROM_L2",
 955    "BriefDescription": "The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss for a marked instruction."
 956  },
 957  {
 958    "EventCode": "0x000300000010C142",
 959    "EventName": "PM_MRK_INST_FROM_L2_ALL",
 960    "BriefDescription": "The processor's instruction cache was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction."
 961  },
 962  {
 963    "EventCode": "0x000340000020C142",
 964    "EventName": "PM_MRK_DATA_FROM_L2_ALL",
 965    "BriefDescription": "The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss or prefetch reload for a marked instruction."
 966  },
 967  {
 968    "EventCode": "0x003F00000000C142",
 969    "EventName": "PM_MRK_INST_FROM_L1MISS",
 970    "BriefDescription": "The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction."
 971  },
 972  {
 973    "EventCode": "0x003F40000000C142",
 974    "EventName": "PM_MRK_DATA_FROM_L1MISS",
 975    "BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss for a marked instruction."
 976  },
 977  {
 978    "EventCode": "0x003F00000010C142",
 979    "EventName": "PM_MRK_INST_FROM_L1MISS_ALL",
 980    "BriefDescription": "The processor's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction."
 981  },
 982  {
 983    "EventCode": "0x003F40000020C142",
 984    "EventName": "PM_MRK_DATA_FROM_L1MISS_ALL",
 985    "BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss or prefetch reload for a marked instruction."
 986  },
 987  {
 988    "EventCode": "0x000040000000C142",
 989    "EventName": "PM_MRK_DATA_FROM_L2_NO_CONFLICT",
 990    "BriefDescription": "The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss for a marked instruction."
 991  },
 992  {
 993    "EventCode": "0x000040000020C142",
 994    "EventName": "PM_MRK_DATA_FROM_L2_NO_CONFLICT_ALL",
 995    "BriefDescription": "The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss or prefetch reload for a marked instruction."
 996  },
 997  {
 998    "EventCode": "0x004040000000C142",
 999    "EventName": "PM_MRK_DATA_FROM_L2_MEPF",
1000    "BriefDescription": "The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss for a marked instruction."
1001  },
1002  {
1003    "EventCode": "0x004040000020C142",
1004    "EventName": "PM_MRK_DATA_FROM_L2_MEPF_ALL",
1005    "BriefDescription": "The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss or prefetch reload for a marked instruction."
1006  },
1007  {
1008    "EventCode": "0x008040000000C142",
1009    "EventName": "PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT",
1010    "BriefDescription": "The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss for a marked instruction."
1011  },
1012  {
1013    "EventCode": "0x008040000020C142",
1014    "EventName": "PM_MRK_DATA_FROM_L2_LDHITST_CONFLICT_ALL",
1015    "BriefDescription": "The processor's L1 data cache was reloaded with data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction."
1016  },
1017  {
1018    "EventCode": "0x00C040000000C142",
1019    "EventName": "PM_MRK_DATA_FROM_L2_OTHER_CONFLICT",
1020    "BriefDescription": "The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss for a marked instruction."
1021  },
1022  {
1023    "EventCode": "0x00C040000020C142",
1024    "EventName": "PM_MRK_DATA_FROM_L2_OTHER_CONFLICT_ALL",
1025    "BriefDescription": "The processor's L1 data cache was reloaded with data that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss or prefetch reload for a marked instruction."
1026  },
1027  {
1028    "EventCode": "0x000380000000C142",
1029    "EventName": "PM_MRK_INST_FROM_L2MISS",
1030    "BriefDescription": "The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction."
1031  },
1032  {
1033    "EventCode": "0x0003C0000000C142",
1034    "EventName": "PM_MRK_DATA_FROM_L2MISS_DSRC",
1035    "BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction."
1036  },
1037  {
1038    "EventCode": "0x000380000010C142",
1039    "EventName": "PM_MRK_INST_FROM_L2MISS_ALL",
1040    "BriefDescription": "The processor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction."
1041  },
1042  {
1043    "EventCode": "0x0003C0000020C142",
1044    "EventName": "PM_MRK_DATA_FROM_L2MISS_ALL",
1045    "BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss or prefetch reload for a marked instruction."
1046  },
1047  {
1048    "EventCode": "0x010300000000C142",
1049    "EventName": "PM_MRK_INST_FROM_L3",
1050    "BriefDescription": "The processor's instruction cache was reloaded from the local core's L3 due to a demand miss for a marked instruction."
1051  },
1052  {
1053    "EventCode": "0x010340000000C142",
1054    "EventName": "PM_MRK_DATA_FROM_L3",
1055    "BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss for a marked instruction."
1056  },
1057  {
1058    "EventCode": "0x010300000010C142",
1059    "EventName": "PM_MRK_INST_FROM_L3_ALL",
1060    "BriefDescription": "The processor's instruction cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction."
1061  },
1062  {
1063    "EventCode": "0x010340000020C142",
1064    "EventName": "PM_MRK_DATA_FROM_L3_ALL",
1065    "BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction."
1066  },
1067  {
1068    "EventCode": "0x010040000000C142",
1069    "EventName": "PM_MRK_DATA_FROM_L3_NO_CONFLICT",
1070    "BriefDescription": "The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss for a marked instruction."
1071  },
1072  {
1073    "EventCode": "0x010040000020C142",
1074    "EventName": "PM_MRK_DATA_FROM_L3_NO_CONFLICT_ALL",
1075    "BriefDescription": "The processor's L1 data cache was reloaded without dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss or prefetch reload for a marked instruction."
1076  },
1077  {
1078    "EventCode": "0x014040000000C142",
1079    "EventName": "PM_MRK_DATA_FROM_L3_MEPF",
1080    "BriefDescription": "The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss for a marked instruction."
1081  },
1082  {
1083    "EventCode": "0x014040000020C142",
1084    "EventName": "PM_MRK_DATA_FROM_L3_MEPF_ALL",
1085    "BriefDescription": "The processor's L1 data cache was reloaded with data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss or prefetch reload for a marked instruction."
1086  },
1087  {
1088    "EventCode": "0x01C040000000C142",
1089    "EventName": "PM_MRK_DATA_FROM_L3_CONFLICT",
1090    "BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss for a marked instruction."
1091  },
1092  {
1093    "EventCode": "0x01C040000020C142",
1094    "EventName": "PM_MRK_DATA_FROM_L3_CONFLICT_ALL",
1095    "BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a demand miss or prefetch reload for a marked instruction."
1096  },
1097  {
1098    "EventCode": "0x000780000000C142",
1099    "EventName": "PM_MRK_INST_FROM_L3MISS_DSRC",
1100    "BriefDescription": "The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction."
1101  },
1102  {
1103    "EventCode": "0x0007C0000000C142",
1104    "EventName": "PM_MRK_DATA_FROM_L3MISS_DSRC",
1105    "BriefDescription": "The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction."
1106  },
1107  {
1108    "EventCode": "0x000780000010C142",
1109    "EventName": "PM_MRK_INST_FROM_L3MISS_ALL",
1110    "BriefDescription": "The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction."
1111  },
1112  {
1113    "EventCode": "0x0007C0000020C142",
1114    "EventName": "PM_MRK_DATA_FROM_L3MISS_ALL",
1115    "BriefDescription": "The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss or prefetch reload for a marked instruction."
1116  },
1117  {
1118    "EventCode": "0x080040000000C142",
1119    "EventName": "PM_MRK_DATA_FROM_L21_REGENT_SHR",
1120    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction."
1121  },
1122  {
1123    "EventCode": "0x080040000020C142",
1124    "EventName": "PM_MRK_DATA_FROM_L21_REGENT_SHR_ALL",
1125    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction."
1126  },
1127  {
1128    "EventCode": "0x084040000000C142",
1129    "EventName": "PM_MRK_DATA_FROM_L21_REGENT_MOD",
1130    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction."
1131  },
1132  {
1133    "EventCode": "0x084040000020C142",
1134    "EventName": "PM_MRK_DATA_FROM_L21_REGENT_MOD_ALL",
1135    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction."
1136  },
1137  {
1138    "EventCode": "0x080100000000C142",
1139    "EventName": "PM_MRK_INST_FROM_L21_REGENT",
1140    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction."
1141  },
1142  {
1143    "EventCode": "0x080140000000C142",
1144    "EventName": "PM_MRK_DATA_FROM_L21_REGENT",
1145    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss for a marked instruction."
1146  },
1147  {
1148    "EventCode": "0x080100000010C142",
1149    "EventName": "PM_MRK_INST_FROM_L21_REGENT_ALL",
1150    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction."
1151  },
1152  {
1153    "EventCode": "0x080140000020C142",
1154    "EventName": "PM_MRK_DATA_FROM_L21_REGENT_ALL",
1155    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction."
1156  },
1157  {
1158    "EventCode": "0x088040000000C142",
1159    "EventName": "PM_MRK_DATA_FROM_L31_REGENT_SHR",
1160    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction."
1161  },
1162  {
1163    "EventCode": "0x088040000020C142",
1164    "EventName": "PM_MRK_DATA_FROM_L31_REGENT_SHR_ALL",
1165    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction."
1166  },
1167  {
1168    "EventCode": "0x08C040000000C142",
1169    "EventName": "PM_MRK_DATA_FROM_L31_REGENT_MOD",
1170    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction."
1171  },
1172  {
1173    "EventCode": "0x08C040000020C142",
1174    "EventName": "PM_MRK_DATA_FROM_L31_REGENT_MOD_ALL",
1175    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction."
1176  },
1177  {
1178    "EventCode": "0x088100000000C142",
1179    "EventName": "PM_MRK_INST_FROM_L31_REGENT",
1180    "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction."
1181  },
1182  {
1183    "EventCode": "0x088140000000C142",
1184    "EventName": "PM_MRK_DATA_FROM_L31_REGENT",
1185    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss for a marked instruction."
1186  },
1187  {
1188    "EventCode": "0x088100000010C142",
1189    "EventName": "PM_MRK_INST_FROM_L31_REGENT_ALL",
1190    "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction."
1191  },
1192  {
1193    "EventCode": "0x088140000020C142",
1194    "EventName": "PM_MRK_DATA_FROM_L31_REGENT_ALL",
1195    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction."
1196  },
1197  {
1198    "EventCode": "0x080240000000C142",
1199    "EventName": "PM_MRK_DATA_FROM_REGENT_L2L3_SHR",
1200    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction."
1201  },
1202  {
1203    "EventCode": "0x080240000020C142",
1204    "EventName": "PM_MRK_DATA_FROM_REGENT_L2L3_SHR_ALL",
1205    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction."
1206  },
1207  {
1208    "EventCode": "0x084240000000C142",
1209    "EventName": "PM_MRK_DATA_FROM_REGENT_L2L3_MOD",
1210    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction."
1211  },
1212  {
1213    "EventCode": "0x084240000020C142",
1214    "EventName": "PM_MRK_DATA_FROM_REGENT_L2L3_MOD_ALL",
1215    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction."
1216  },
1217  {
1218    "EventCode": "0x080300000000C142",
1219    "EventName": "PM_MRK_INST_FROM_REGENT_L2L3",
1220    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction."
1221  },
1222  {
1223    "EventCode": "0x080340000000C142",
1224    "EventName": "PM_MRK_DATA_FROM_REGENT_L2L3",
1225    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss for a marked instruction."
1226  },
1227  {
1228    "EventCode": "0x080300000010C142",
1229    "EventName": "PM_MRK_INST_FROM_REGENT_L2L3_ALL",
1230    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction."
1231  },
1232  {
1233    "EventCode": "0x080340000020C142",
1234    "EventName": "PM_MRK_DATA_FROM_REGENT_L2L3_ALL",
1235    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in the same regent due to a demand miss or prefetch reload for a marked instruction."
1236  },
1237  {
1238    "EventCode": "0x0A0040000000C142",
1239    "EventName": "PM_MRK_DATA_FROM_L21_NON_REGENT_SHR",
1240    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction."
1241  },
1242  {
1243    "EventCode": "0x0A0040000020C142",
1244    "EventName": "PM_MRK_DATA_FROM_L21_NON_REGENT_SHR_ALL",
1245    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction."
1246  },
1247  {
1248    "EventCode": "0x0A4040000000C142",
1249    "EventName": "PM_MRK_DATA_FROM_L21_NON_REGENT_MOD",
1250    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction."
1251  },
1252  {
1253    "EventCode": "0x0A4040000020C142",
1254    "EventName": "PM_MRK_DATA_FROM_L21_NON_REGENT_MOD_ALL",
1255    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction."
1256  },
1257  {
1258    "EventCode": "0x0A0100000000C142",
1259    "EventName": "PM_MRK_INST_FROM_L21_NON_REGENT",
1260    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction."
1261  },
1262  {
1263    "EventCode": "0x0A0140000000C142",
1264    "EventName": "PM_MRK_DATA_FROM_L21_NON_REGENT",
1265    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss for a marked instruction."
1266  },
1267  {
1268    "EventCode": "0x0A0100000010C142",
1269    "EventName": "PM_MRK_INST_FROM_L21_NON_REGENT_ALL",
1270    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction."
1271  },
1272  {
1273    "EventCode": "0x0A0140000020C142",
1274    "EventName": "PM_MRK_DATA_FROM_L21_NON_REGENT_ALL",
1275    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction."
1276  },
1277  {
1278    "EventCode": "0x0A8040000000C142",
1279    "EventName": "PM_MRK_DATA_FROM_L31_NON_REGENT_SHR",
1280    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction."
1281  },
1282  {
1283    "EventCode": "0x0A8040000020C142",
1284    "EventName": "PM_MRK_DATA_FROM_L31_NON_REGENT_SHR_ALL",
1285    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction."
1286  },
1287  {
1288    "EventCode": "0x0AC040000000C142",
1289    "EventName": "PM_MRK_DATA_FROM_L31_NON_REGENT_MOD",
1290    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction."
1291  },
1292  {
1293    "EventCode": "0x0AC040000020C142",
1294    "EventName": "PM_MRK_DATA_FROM_L31_NON_REGENT_MOD_ALL",
1295    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction."
1296  },
1297  {
1298    "EventCode": "0x0A8100000000C142",
1299    "EventName": "PM_MRK_INST_FROM_L31_NON_REGENT",
1300    "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction."
1301  },
1302  {
1303    "EventCode": "0x0A8140000000C142",
1304    "EventName": "PM_MRK_DATA_FROM_L31_NON_REGENT",
1305    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss for a marked instruction."
1306  },
1307  {
1308    "EventCode": "0x0A8100000010C142",
1309    "EventName": "PM_MRK_INST_FROM_L31_NON_REGENT_ALL",
1310    "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction."
1311  },
1312  {
1313    "EventCode": "0x0A8140000020C142",
1314    "EventName": "PM_MRK_DATA_FROM_L31_NON_REGENT_ALL",
1315    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction."
1316  },
1317  {
1318    "EventCode": "0x0A0240000000C142",
1319    "EventName": "PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR",
1320    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction."
1321  },
1322  {
1323    "EventCode": "0x0A0240000020C142",
1324    "EventName": "PM_MRK_DATA_FROM_NON_REGENT_L2L3_SHR_ALL",
1325    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction."
1326  },
1327  {
1328    "EventCode": "0x0A4240000000C142",
1329    "EventName": "PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD",
1330    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction."
1331  },
1332  {
1333    "EventCode": "0x0A4240000020C142",
1334    "EventName": "PM_MRK_DATA_FROM_NON_REGENT_L2L3_MOD_ALL",
1335    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction."
1336  },
1337  {
1338    "EventCode": "0x0A0300000000C142",
1339    "EventName": "PM_MRK_INST_FROM_NON_REGENT_L2L3",
1340    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction."
1341  },
1342  {
1343    "EventCode": "0x0A0340000000C142",
1344    "EventName": "PM_MRK_DATA_FROM_NON_REGENT_L2L3",
1345    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss for a marked instruction."
1346  },
1347  {
1348    "EventCode": "0x0A0300000010C142",
1349    "EventName": "PM_MRK_INST_FROM_NON_REGENT_L2L3_ALL",
1350    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction."
1351  },
1352  {
1353    "EventCode": "0x0A0340000020C142",
1354    "EventName": "PM_MRK_DATA_FROM_NON_REGENT_L2L3_ALL",
1355    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 on the same chip in a different regent due to a demand miss or prefetch reload for a marked instruction."
1356  },
1357  {
1358    "EventCode": "0x094100000000C142",
1359    "EventName": "PM_MRK_INST_FROM_LMEM",
1360    "BriefDescription": "The processor's instruction cache was reloaded from the local chip's memory due to a demand miss for a marked instruction."
1361  },
1362  {
1363    "EventCode": "0x094040000000C142",
1364    "EventName": "PM_MRK_DATA_FROM_LMEM",
1365    "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss for a marked instruction."
1366  },
1367  {
1368    "EventCode": "0x094100000010C142",
1369    "EventName": "PM_MRK_INST_FROM_LMEM_ALL",
1370    "BriefDescription": "The processor's instruction cache was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction."
1371  },
1372  {
1373    "EventCode": "0x094040000020C142",
1374    "EventName": "PM_MRK_DATA_FROM_LMEM_ALL",
1375    "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's memory due to a demand miss or prefetch reload for a marked instruction."
1376  },
1377  {
1378    "EventCode": "0x098040000000C142",
1379    "EventName": "PM_MRK_DATA_FROM_L_OC_CACHE",
1380    "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI cache due to a demand miss for a marked instruction."
1381  },
1382  {
1383    "EventCode": "0x098040000020C142",
1384    "EventName": "PM_MRK_DATA_FROM_L_OC_CACHE_ALL",
1385    "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI cache due to a demand miss or prefetch reload for a marked instruction."
1386  },
1387  {
1388    "EventCode": "0x09C040000000C142",
1389    "EventName": "PM_MRK_DATA_FROM_L_OC_MEM",
1390    "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI memory due to a demand miss for a marked instruction."
1391  },
1392  {
1393    "EventCode": "0x09C040000020C142",
1394    "EventName": "PM_MRK_DATA_FROM_L_OC_MEM_ALL",
1395    "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI memory due to a demand miss or prefetch reload for a marked instruction."
1396  },
1397  {
1398    "EventCode": "0x098100000000C142",
1399    "EventName": "PM_MRK_INST_FROM_L_OC_ANY",
1400    "BriefDescription": "The processor's instruction cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss for a marked instruction."
1401  },
1402  {
1403    "EventCode": "0x098140000000C142",
1404    "EventName": "PM_MRK_DATA_FROM_L_OC_ANY",
1405    "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss for a marked instruction."
1406  },
1407  {
1408    "EventCode": "0x098100000010C142",
1409    "EventName": "PM_MRK_INST_FROM_L_OC_ANY_ALL",
1410    "BriefDescription": "The processor's instruction cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss or prefetch reload for a marked instruction."
1411  },
1412  {
1413    "EventCode": "0x098140000020C142",
1414    "EventName": "PM_MRK_DATA_FROM_L_OC_ANY_ALL",
1415    "BriefDescription": "The processor's L1 data cache was reloaded from the local chip's OpenCAPI cache or memory due to a demand miss or prefetch reload for a marked instruction."
1416  },
1417  {
1418    "EventCode": "0x0C0040000000C142",
1419    "EventName": "PM_MRK_DATA_FROM_RL2_SHR",
1420    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction."
1421  },
1422  {
1423    "EventCode": "0x0C0040000020C142",
1424    "EventName": "PM_MRK_DATA_FROM_RL2_SHR_ALL",
1425    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction."
1426  },
1427  {
1428    "EventCode": "0x0C4040000000C142",
1429    "EventName": "PM_MRK_DATA_FROM_RL2_MOD",
1430    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss for a marked instruction."
1431  },
1432  {
1433    "EventCode": "0x0C4040000020C142",
1434    "EventName": "PM_MRK_DATA_FROM_RL2_MOD_ALL",
1435    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction."
1436  },
1437  {
1438    "EventCode": "0x0C0100000000C142",
1439    "EventName": "PM_MRK_INST_FROM_RL2",
1440    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction."
1441  },
1442  {
1443    "EventCode": "0x0C0140000000C142",
1444    "EventName": "PM_MRK_DATA_FROM_RL2",
1445    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss for a marked instruction."
1446  },
1447  {
1448    "EventCode": "0x0C0100000010C142",
1449    "EventName": "PM_MRK_INST_FROM_RL2_ALL",
1450    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction."
1451  },
1452  {
1453    "EventCode": "0x0C0140000020C142",
1454    "EventName": "PM_MRK_DATA_FROM_RL2_ALL",
1455    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 from a remote chip due to a demand miss or prefetch reload for a marked instruction."
1456  },
1457  {
1458    "EventCode": "0x0C8040000000C142",
1459    "EventName": "PM_MRK_DATA_FROM_RL3_SHR",
1460    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction."
1461  },
1462  {
1463    "EventCode": "0x0C8040000020C142",
1464    "EventName": "PM_MRK_DATA_FROM_RL3_SHR_ALL",
1465    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction."
1466  },
1467  {
1468    "EventCode": "0x0CC040000000C142",
1469    "EventName": "PM_MRK_DATA_FROM_RL3_MOD",
1470    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss for a marked instruction."
1471  },
1472  {
1473    "EventCode": "0x0CC040000020C142",
1474    "EventName": "PM_MRK_DATA_FROM_RL3_MOD_ALL",
1475    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction."
1476  },
1477  {
1478    "EventCode": "0x0C8100000000C142",
1479    "EventName": "PM_MRK_INST_FROM_RL3",
1480    "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction."
1481  },
1482  {
1483    "EventCode": "0x0C8140000000C142",
1484    "EventName": "PM_MRK_DATA_FROM_RL3",
1485    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss for a marked instruction."
1486  },
1487  {
1488    "EventCode": "0x0C8100000010C142",
1489    "EventName": "PM_MRK_INST_FROM_RL3_ALL",
1490    "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction."
1491  },
1492  {
1493    "EventCode": "0x0C8140000020C142",
1494    "EventName": "PM_MRK_DATA_FROM_RL3_ALL",
1495    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction."
1496  },
1497  {
1498    "EventCode": "0x0C0240000000C142",
1499    "EventName": "PM_MRK_DATA_FROM_RL2L3_SHR",
1500    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction."
1501  },
1502  {
1503    "EventCode": "0x0C0240000020C142",
1504    "EventName": "PM_MRK_DATA_FROM_RL2L3_SHR_ALL",
1505    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction."
1506  },
1507  {
1508    "EventCode": "0x0C4240000000C142",
1509    "EventName": "PM_MRK_DATA_FROM_RL2L3_MOD",
1510    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction."
1511  },
1512  {
1513    "EventCode": "0x0C4240000020C142",
1514    "EventName": "PM_MRK_DATA_FROM_RL2L3_MOD_ALL",
1515    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction."
1516  },
1517  {
1518    "EventCode": "0x0C0300000000C142",
1519    "EventName": "PM_MRK_INST_FROM_RL2L3",
1520    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction."
1521  },
1522  {
1523    "EventCode": "0x0C0340000000C142",
1524    "EventName": "PM_MRK_DATA_FROM_RL2L3",
1525    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss for a marked instruction."
1526  },
1527  {
1528    "EventCode": "0x0C0300000010C142",
1529    "EventName": "PM_MRK_INST_FROM_RL2L3_ALL",
1530    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction."
1531  },
1532  {
1533    "EventCode": "0x0C0340000020C142",
1534    "EventName": "PM_MRK_DATA_FROM_RL2L3_ALL",
1535    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from a remote chip due to a demand miss or prefetch reload for a marked instruction."
1536  },
1537  {
1538    "EventCode": "0x0D4100000000C142",
1539    "EventName": "PM_MRK_INST_FROM_RMEM",
1540    "BriefDescription": "The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction."
1541  },
1542  {
1543    "EventCode": "0x0D4040000000C142",
1544    "EventName": "PM_MRK_DATA_FROM_RMEM",
1545    "BriefDescription": "The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss for a marked instruction."
1546  },
1547  {
1548    "EventCode": "0x0D4100000010C142",
1549    "EventName": "PM_MRK_INST_FROM_RMEM_ALL",
1550    "BriefDescription": "The processor's instruction cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction."
1551  },
1552  {
1553    "EventCode": "0x0D4040000020C142",
1554    "EventName": "PM_MRK_DATA_FROM_RMEM_ALL",
1555    "BriefDescription": "The processor's L1 data cache was reloaded from remote memory (MC slow) due to a demand miss or prefetch reload for a marked instruction."
1556  },
1557  {
1558    "EventCode": "0x0D8040000000C142",
1559    "EventName": "PM_MRK_DATA_FROM_R_OC_CACHE",
1560    "BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI cache due to a demand miss for a marked instruction."
1561  },
1562  {
1563    "EventCode": "0x0D8040000020C142",
1564    "EventName": "PM_MRK_DATA_FROM_R_OC_CACHE_ALL",
1565    "BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI cache due to a demand miss or prefetch reload for a marked instruction."
1566  },
1567  {
1568    "EventCode": "0x0DC040000000C142",
1569    "EventName": "PM_MRK_DATA_FROM_R_OC_MEM",
1570    "BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI memory due to a demand miss for a marked instruction."
1571  },
1572  {
1573    "EventCode": "0x0DC040000020C142",
1574    "EventName": "PM_MRK_DATA_FROM_R_OC_MEM_ALL",
1575    "BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI memory due to a demand miss or prefetch reload for a marked instruction."
1576  },
1577  {
1578    "EventCode": "0x0D8100000000C142",
1579    "EventName": "PM_MRK_INST_FROM_R_OC_ANY",
1580    "BriefDescription": "The processor's instruction cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss for a marked instruction."
1581  },
1582  {
1583    "EventCode": "0x0D8140000000C142",
1584    "EventName": "PM_MRK_DATA_FROM_R_OC_ANY",
1585    "BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss for a marked instruction."
1586  },
1587  {
1588    "EventCode": "0x0D8100000010C142",
1589    "EventName": "PM_MRK_INST_FROM_R_OC_ANY_ALL",
1590    "BriefDescription": "The processor's instruction cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss or prefetch reload for a marked instruction."
1591  },
1592  {
1593    "EventCode": "0x0D8140000020C142",
1594    "EventName": "PM_MRK_DATA_FROM_R_OC_ANY_ALL",
1595    "BriefDescription": "The processor's L1 data cache was reloaded from a remote chip's OpenCAPI cache or memory due to a demand miss or prefetch reload for a marked instruction."
1596  },
1597  {
1598    "EventCode": "0x0E0040000000C142",
1599    "EventName": "PM_MRK_DATA_FROM_DL2_SHR",
1600    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction."
1601  },
1602  {
1603    "EventCode": "0x0E0040000020C142",
1604    "EventName": "PM_MRK_DATA_FROM_DL2_SHR_ALL",
1605    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction."
1606  },
1607  {
1608    "EventCode": "0x0E4040000000C142",
1609    "EventName": "PM_MRK_DATA_FROM_DL2_MOD",
1610    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss for a marked instruction."
1611  },
1612  {
1613    "EventCode": "0x0E4040000020C142",
1614    "EventName": "PM_MRK_DATA_FROM_DL2_MOD_ALL",
1615    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction."
1616  },
1617  {
1618    "EventCode": "0x0E0100000000C142",
1619    "EventName": "PM_MRK_INST_FROM_DL2",
1620    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction."
1621  },
1622  {
1623    "EventCode": "0x0E0140000000C142",
1624    "EventName": "PM_MRK_DATA_FROM_DL2",
1625    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss for a marked instruction."
1626  },
1627  {
1628    "EventCode": "0x0E0100000010C142",
1629    "EventName": "PM_MRK_INST_FROM_DL2_ALL",
1630    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction."
1631  },
1632  {
1633    "EventCode": "0x0E0140000020C142",
1634    "EventName": "PM_MRK_DATA_FROM_DL2_ALL",
1635    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 from a distant chip due to a demand miss or prefetch reload for a marked instruction."
1636  },
1637  {
1638    "EventCode": "0x0E8040000000C142",
1639    "EventName": "PM_MRK_DATA_FROM_DL3_SHR",
1640    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction."
1641  },
1642  {
1643    "EventCode": "0x0E8040000020C142",
1644    "EventName": "PM_MRK_DATA_FROM_DL3_SHR_ALL",
1645    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction."
1646  },
1647  {
1648    "EventCode": "0x0EC040000000C142",
1649    "EventName": "PM_MRK_DATA_FROM_DL3_MOD",
1650    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss for a marked instruction."
1651  },
1652  {
1653    "EventCode": "0x0EC040000020C142",
1654    "EventName": "PM_MRK_DATA_FROM_DL3_MOD_ALL",
1655    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction."
1656  },
1657  {
1658    "EventCode": "0x0E8100000000C142",
1659    "EventName": "PM_MRK_INST_FROM_DL3",
1660    "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction."
1661  },
1662  {
1663    "EventCode": "0x0E8140000000C142",
1664    "EventName": "PM_MRK_DATA_FROM_DL3",
1665    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss for a marked instruction."
1666  },
1667  {
1668    "EventCode": "0x0E8100000010C142",
1669    "EventName": "PM_MRK_INST_FROM_DL3_ALL",
1670    "BriefDescription": "The processor's instruction cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction."
1671  },
1672  {
1673    "EventCode": "0x0E8140000020C142",
1674    "EventName": "PM_MRK_DATA_FROM_DL3_ALL",
1675    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction."
1676  },
1677  {
1678    "EventCode": "0x0E0240000000C142",
1679    "EventName": "PM_MRK_DATA_FROM_DL2L3_SHR",
1680    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction."
1681  },
1682  {
1683    "EventCode": "0x0E0240000020C142",
1684    "EventName": "PM_MRK_DATA_FROM_DL2L3_SHR_ALL",
1685    "BriefDescription": "The processor's L1 data cache was reloaded with a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction."
1686  },
1687  {
1688    "EventCode": "0x0E4240000000C142",
1689    "EventName": "PM_MRK_DATA_FROM_DL2L3_MOD",
1690    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction."
1691  },
1692  {
1693    "EventCode": "0x0E4240000020C142",
1694    "EventName": "PM_MRK_DATA_FROM_DL2L3_MOD_ALL",
1695    "BriefDescription": "The processor's L1 data cache was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction."
1696  },
1697  {
1698    "EventCode": "0x0E0300000000C142",
1699    "EventName": "PM_MRK_INST_FROM_DL2L3",
1700    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction."
1701  },
1702  {
1703    "EventCode": "0x0E0340000000C142",
1704    "EventName": "PM_MRK_DATA_FROM_DL2L3",
1705    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss for a marked instruction."
1706  },
1707  {
1708    "EventCode": "0x0E0300000010C142",
1709    "EventName": "PM_MRK_INST_FROM_DL2L3_ALL",
1710    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction."
1711  },
1712  {
1713    "EventCode": "0x0E0340000020C142",
1714    "EventName": "PM_MRK_DATA_FROM_DL2L3_ALL",
1715    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from a distant chip due to a demand miss or prefetch reload for a marked instruction."
1716  },
1717  {
1718    "EventCode": "0x0F4100000000C142",
1719    "EventName": "PM_MRK_INST_FROM_DMEM",
1720    "BriefDescription": "The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction."
1721  },
1722  {
1723    "EventCode": "0x0F4040000000C142",
1724    "EventName": "PM_MRK_DATA_FROM_DMEM",
1725    "BriefDescription": "The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss for a marked instruction."
1726  },
1727  {
1728    "EventCode": "0x0F4100000010C142",
1729    "EventName": "PM_MRK_INST_FROM_DMEM_ALL",
1730    "BriefDescription": "The processor's instruction cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction."
1731  },
1732  {
1733    "EventCode": "0x0F4040000020C142",
1734    "EventName": "PM_MRK_DATA_FROM_DMEM_ALL",
1735    "BriefDescription": "The processor's L1 data cache was reloaded from distant memory (MC slow) due to a demand miss or prefetch reload for a marked instruction."
1736  },
1737  {
1738    "EventCode": "0x0F8040000000C142",
1739    "EventName": "PM_MRK_DATA_FROM_D_OC_CACHE",
1740    "BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI cache due to a demand miss for a marked instruction."
1741  },
1742  {
1743    "EventCode": "0x0F8040000020C142",
1744    "EventName": "PM_MRK_DATA_FROM_D_OC_CACHE_ALL",
1745    "BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI cache due to a demand miss or prefetch reload for a marked instruction."
1746  },
1747  {
1748    "EventCode": "0x0FC040000000C142",
1749    "EventName": "PM_MRK_DATA_FROM_D_OC_MEM",
1750    "BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI memory due to a demand miss for a marked instruction."
1751  },
1752  {
1753    "EventCode": "0x0FC040000020C142",
1754    "EventName": "PM_MRK_DATA_FROM_D_OC_MEM_ALL",
1755    "BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI memory due to a demand miss or prefetch reload for a marked instruction."
1756  },
1757  {
1758    "EventCode": "0x0F8100000000C142",
1759    "EventName": "PM_MRK_INST_FROM_D_OC_ANY",
1760    "BriefDescription": "The processor's instruction cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss for a marked instruction."
1761  },
1762  {
1763    "EventCode": "0x0F8140000000C142",
1764    "EventName": "PM_MRK_DATA_FROM_D_OC_ANY",
1765    "BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss for a marked instruction."
1766  },
1767  {
1768    "EventCode": "0x0F8100000010C142",
1769    "EventName": "PM_MRK_INST_FROM_D_OC_ANY_ALL",
1770    "BriefDescription": "The processor's instruction cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss or prefetch reload for a marked instruction."
1771  },
1772  {
1773    "EventCode": "0x0F8140000020C142",
1774    "EventName": "PM_MRK_DATA_FROM_D_OC_ANY_ALL",
1775    "BriefDescription": "The processor's L1 data cache was reloaded from a distant chip's OpenCAPI cache or memory due to a demand miss or prefetch reload for a marked instruction."
1776  },
1777  {
1778    "EventCode": "0x080B00000000C142",
1779    "EventName": "PM_MRK_INST_FROM_ONCHIP_CACHE",
1780    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction."
1781  },
1782  {
1783    "EventCode": "0x080B40000000C142",
1784    "EventName": "PM_MRK_DATA_FROM_ONCHIP_CACHE",
1785    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss for a marked instruction."
1786  },
1787  {
1788    "EventCode": "0x080B00000010C142",
1789    "EventName": "PM_MRK_INST_FROM_ONCHIP_CACHE_ALL",
1790    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction."
1791  },
1792  {
1793    "EventCode": "0x080B40000020C142",
1794    "EventName": "PM_MRK_DATA_FROM_ONCHIP_CACHE_ALL",
1795    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from the same chip due to a demand miss or prefetch reload for a marked instruction."
1796  },
1797  {
1798    "EventCode": "0x0C0B00000000C142",
1799    "EventName": "PM_MRK_INST_FROM_OFFCHIP_CACHE",
1800    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction."
1801  },
1802  {
1803    "EventCode": "0x0C0B40000000C142",
1804    "EventName": "PM_MRK_DATA_FROM_OFFCHIP_CACHE",
1805    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss for a marked instruction."
1806  },
1807  {
1808    "EventCode": "0x0C0B00000010C142",
1809    "EventName": "PM_MRK_INST_FROM_OFFCHIP_CACHE_ALL",
1810    "BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction."
1811  },
1812  {
1813    "EventCode": "0x0C0B40000020C142",
1814    "EventName": "PM_MRK_DATA_FROM_OFFCHIP_CACHE_ALL",
1815    "BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from a different chip due to a demand miss or prefetch reload for a marked instruction."
1816  },
1817  {
1818    "EventCode": "0x095900000000C142",
1819    "EventName": "PM_MRK_INST_FROM_ANY_MEMORY",
1820    "BriefDescription": "The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction."
1821  },
1822  {
1823    "EventCode": "0x095840000000C142",
1824    "EventName": "PM_MRK_DATA_FROM_ANY_MEMORY",
1825    "BriefDescription": "The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss for a marked instruction."
1826  },
1827  {
1828    "EventCode": "0x095900000010C142",
1829    "EventName": "PM_MRK_INST_FROM_ANY_MEMORY_ALL",
1830    "BriefDescription": "The processor's instruction cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction."
1831  },
1832  {
1833    "EventCode": "0x095840000020C142",
1834    "EventName": "PM_MRK_DATA_FROM_ANY_MEMORY_ALL",
1835    "BriefDescription": "The processor's L1 data cache was reloaded from any chip's memory (MC slow) due to a demand miss or prefetch reload for a marked instruction."
1836  }
1837]