sve.json

  1[
  2    {
  3        "ArchStdEvent": "SIMD_INST_RETIRED",
  4        "BriefDescription": "This event counts architecturally executed SIMD instructions, excluding the Advanced SIMD scalar instructions and the instructions listed in Non-SIMD SVE instructions section of ARMv9 Reference Manual."
  5    },
  6    {
  7        "ArchStdEvent": "SVE_INST_RETIRED",
  8        "BriefDescription": "This event counts architecturally executed SVE instructions, including the instructions listed in Non-SIMD SVE instructions section of ARMv9 Reference Manual."
  9    },
 10    {
 11        "ArchStdEvent": "SVE_INST_SPEC",
 12        "BriefDescription": "This event counts architecturally executed SVE instructions, including the instructions listed in Non-SIMD SVE instructions section of ARMv9 Reference Manual."
 13    },
 14    {
 15        "ArchStdEvent": "ASE_SVE_INST_SPEC",
 16        "BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE operation."
 17    },
 18    {
 19        "ArchStdEvent": "UOP_SPEC",
 20        "BriefDescription": "This event counts all architecturally executed micro-operation."
 21    },
 22    {
 23        "ArchStdEvent": "SVE_MATH_SPEC",
 24        "BriefDescription": "This event counts architecturally executed math function operations due to the SVE FTSMUL, FTMAD, FTSSEL, and FEXPA instructions."
 25    },
 26    {
 27        "ArchStdEvent": "FP_SPEC",
 28        "BriefDescription": "This event counts architecturally executed operations due to scalar, Advanced SIMD, and SVE instructions listed in Floating-point instructions section of ARMv9 Reference Manual."
 29    },
 30    {
 31        "ArchStdEvent": "FP_FMA_SPEC",
 32        "BriefDescription": "This event counts architecturally executed floating-point fused multiply-add and multiply-subtract operation."
 33    },
 34    {
 35        "ArchStdEvent": "FP_RECPE_SPEC",
 36        "BriefDescription": "This event counts architecturally executed floating-point reciprocal estimate operations due to the Advanced SIMD scalar, Advanced SIMD vector, and SVE FRECPE and FRSQRTE instructions."
 37    },
 38    {
 39        "ArchStdEvent": "FP_CVT_SPEC",
 40        "BriefDescription": "This event counts architecturally executed floating-point convert operations due to the scalar, Advanced SIMD, and SVE floating-point conversion instructions listed in Floating-point conversions section of ARMv9 Reference Manual."
 41    },
 42    {
 43        "ArchStdEvent": "ASE_INT_SPEC",
 44        "BriefDescription": "This event counts architecturally executed Advanced SIMD integer operation."
 45    },
 46    {
 47        "ArchStdEvent": "SVE_INT_SPEC",
 48        "BriefDescription": "This event counts architecturally executed SVE integer operation."
 49    },
 50    {
 51        "ArchStdEvent": "ASE_SVE_INT_SPEC",
 52        "BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE integer operation."
 53    },
 54    {
 55        "ArchStdEvent": "SVE_INT_DIV_SPEC",
 56        "BriefDescription": "This event counts architecturally executed SVE integer divide operation."
 57    },
 58    {
 59        "ArchStdEvent": "SVE_INT_DIV64_SPEC",
 60        "BriefDescription": "This event counts architecturally executed SVE 64-bit integer divide operation."
 61    },
 62    {
 63        "ArchStdEvent": "ASE_INT_MUL_SPEC",
 64        "BriefDescription": "This event counts architecturally executed Advanced SIMD integer multiply operation."
 65    },
 66    {
 67        "ArchStdEvent": "SVE_INT_MUL_SPEC",
 68        "BriefDescription": "This event counts architecturally executed SVE integer multiply operation."
 69    },
 70    {
 71        "ArchStdEvent": "ASE_SVE_INT_MUL_SPEC",
 72        "BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE integer multiply operation."
 73    },
 74    {
 75        "ArchStdEvent": "SVE_INT_MUL64_SPEC",
 76        "BriefDescription": "This event counts architecturally executed SVE integer 64-bit x 64-bit multiply operation."
 77    },
 78    {
 79        "ArchStdEvent": "SVE_INT_MULH64_SPEC",
 80        "BriefDescription": "This event counts architecturally executed SVE integer 64-bit x 64-bit multiply returning high part operation."
 81    },
 82    {
 83        "ArchStdEvent": "ASE_NONFP_SPEC",
 84        "BriefDescription": "This event counts architecturally executed Advanced SIMD non-floating-point operation."
 85    },
 86    {
 87        "ArchStdEvent": "SVE_NONFP_SPEC",
 88        "BriefDescription": "This event counts architecturally executed SVE non-floating-point operation."
 89    },
 90    {
 91        "ArchStdEvent": "ASE_SVE_NONFP_SPEC",
 92        "BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE non-floating-point operation."
 93    },
 94    {
 95        "ArchStdEvent": "ASE_INT_VREDUCE_SPEC",
 96        "BriefDescription": "This event counts architecturally executed Advanced SIMD integer reduction operation."
 97    },
 98    {
 99        "ArchStdEvent": "SVE_INT_VREDUCE_SPEC",
100        "BriefDescription": "This event counts architecturally executed SVE integer reduction operation."
101    },
102    {
103        "ArchStdEvent": "ASE_SVE_INT_VREDUCE_SPEC",
104        "BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE integer reduction operation."
105    },
106    {
107        "ArchStdEvent": "SVE_PERM_SPEC",
108        "BriefDescription": "This event counts architecturally executed vector or predicate permute operation."
109    },
110    {
111        "ArchStdEvent": "SVE_XPIPE_Z2R_SPEC",
112        "BriefDescription": "This event counts architecturally executed vector to general-purpose scalar cross-pipeline transfer operation."
113    },
114    {
115        "ArchStdEvent": "SVE_XPIPE_R2Z_SPEC",
116        "BriefDescription": "This event counts architecturally executed general-purpose scalar to vector cross-pipeline transfer operation."
117    },
118    {
119        "ArchStdEvent": "SVE_PGEN_SPEC",
120        "BriefDescription": "This event counts architecturally executed predicate-generating operation."
121    },
122    {
123        "ArchStdEvent": "SVE_PGEN_FLG_SPEC",
124        "BriefDescription": "This event counts architecturally executed predicate-generating operation that sets condition flags."
125    },
126    {
127        "ArchStdEvent": "SVE_PPERM_SPEC",
128        "BriefDescription": "This event counts architecturally executed predicate permute operation."
129    },
130    {
131        "ArchStdEvent": "SVE_PRED_SPEC",
132        "BriefDescription": "This event counts architecturally executed SIMD data-processing and load/store operations due to SVE instructions with a Governing predicate operand that determines the Active elements."
133    },
134    {
135        "ArchStdEvent": "SVE_MOVPRFX_SPEC",
136        "BriefDescription": "This event counts architecturally executed operations due to MOVPRFX instructions, whether or not they were fused with the prefixed instruction."
137    },
138    {
139        "ArchStdEvent": "SVE_MOVPRFX_Z_SPEC",
140        "BriefDescription": "This event counts architecturally executed operation counted by SVE_MOVPRFX_SPEC where the operation uses zeroing predication."
141    },
142    {
143        "ArchStdEvent": "SVE_MOVPRFX_M_SPEC",
144        "BriefDescription": "This event counts architecturally executed operation counted by SVE_MOVPRFX_SPEC where the operation uses merging predication."
145    },
146    {
147        "ArchStdEvent": "SVE_MOVPRFX_U_SPEC",
148        "BriefDescription": "This event counts architecturally executed operations due to MOVPRFX instructions that were not fused with the prefixed instruction."
149    },
150    {
151        "ArchStdEvent": "ASE_SVE_LD_SPEC",
152        "BriefDescription": "This event counts architecturally executed operations that read from memory due to Advanced SIMD or SVE load instructions."
153    },
154    {
155        "ArchStdEvent": "ASE_SVE_ST_SPEC",
156        "BriefDescription": "This event counts architecturally executed operations that write to memory due to Advanced SIMD or SVE store instructions."
157    },
158    {
159        "ArchStdEvent": "PRF_SPEC",
160        "BriefDescription": "This event counts architecturally executed prefetch operations due to scalar PRFM, PRFUM and SVE PRF instructions."
161    },
162    {
163        "ArchStdEvent": "BASE_LD_REG_SPEC",
164        "BriefDescription": "This event counts architecturally executed operations that read from memory due to an instruction that loads a general-purpose register."
165    },
166    {
167        "ArchStdEvent": "BASE_ST_REG_SPEC",
168        "BriefDescription": "This event counts architecturally executed operations that write to memory due to an instruction that stores a general-purpose register, excluding the DC ZVA instruction."
169    },
170    {
171        "ArchStdEvent": "SVE_LDR_REG_SPEC",
172        "BriefDescription": "This event counts architecturally executed operations that read from memory due to an SVE LDR instruction."
173    },
174    {
175        "ArchStdEvent": "SVE_STR_REG_SPEC",
176        "BriefDescription": "This event counts architecturally executed operations that write to memory due to an SVE STR instruction."
177    },
178    {
179        "ArchStdEvent": "SVE_LDR_PREG_SPEC",
180        "BriefDescription": "This event counts architecturally executed operations that read from memory due to an SVE LDR (predicate) instruction."
181    },
182    {
183        "ArchStdEvent": "SVE_STR_PREG_SPEC",
184        "BriefDescription": "This event counts architecturally executed operations that write to memory due to an SVE STR (predicate) instruction."
185    },
186    {
187        "ArchStdEvent": "SVE_PRF_CONTIG_SPEC",
188        "BriefDescription": "This event counts architecturally executed operations that prefetch memory due to an SVE predicated single contiguous element prefetch instruction."
189    },
190    {
191        "ArchStdEvent": "SVE_LDNT_CONTIG_SPEC",
192        "BriefDescription": "This event counts architecturally executed operation that reads from memory with a non-temporal hint due to an SVE non-temporal contiguous element load instruction."
193    },
194    {
195        "ArchStdEvent": "SVE_STNT_CONTIG_SPEC",
196        "BriefDescription": "This event counts architecturally executed operation that writes to memory with a non-temporal hint due to an SVE non-temporal contiguous element store instruction."
197    },
198    {
199        "ArchStdEvent": "ASE_SVE_LD_MULTI_SPEC",
200        "BriefDescription": "This event counts architecturally executed operations that read from memory due to Advanced SIMD or SVE multiple vector contiguous structure load instructions."
201    },
202    {
203        "ArchStdEvent": "ASE_SVE_ST_MULTI_SPEC",
204        "BriefDescription": "This event counts architecturally executed operations that write to memory due to Advanced SIMD or SVE multiple vector contiguous structure store instructions."
205    },
206    {
207        "ArchStdEvent": "SVE_LD_GATHER_SPEC",
208        "BriefDescription": "This event counts architecturally executed operations that read from memory due to SVE non-contiguous gather-load instructions."
209    },
210    {
211        "ArchStdEvent": "SVE_ST_SCATTER_SPEC",
212        "BriefDescription": "This event counts architecturally executed operations that write to memory due to SVE non-contiguous scatter-store instructions."
213    },
214    {
215        "ArchStdEvent": "SVE_PRF_GATHER_SPEC",
216        "BriefDescription": "This event counts architecturally executed operations that prefetch memory due to SVE non-contiguous gather-prefetch instructions."
217    },
218    {
219        "ArchStdEvent": "SVE_LDFF_SPEC",
220        "BriefDescription": "This event counts architecturally executed memory read operations due to SVE First-fault and Non-fault load instructions."
221    },
222    {
223        "ArchStdEvent": "FP_HP_SCALE_OPS_SPEC",
224        "BriefDescription": "This event counts architecturally executed SVE half-precision arithmetic operation. See FP_HP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 8, or by 16 for operations that would also be counted by SVE_FP_FMA_SPEC."
225    },
226    {
227        "ArchStdEvent": "FP_HP_FIXED_OPS_SPEC",
228        "BriefDescription": "This event counts architecturally executed v8SIMD&FP half-precision arithmetic operation. See FP_HP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by the number of 16-bit elements for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC."
229    },
230    {
231        "ArchStdEvent": "FP_SP_SCALE_OPS_SPEC",
232        "BriefDescription": "This event counts architecturally executed SVE single-precision arithmetic operation. See FP_SP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 4, or by 8 for operations that would also be counted by SVE_FP_FMA_SPEC."
233    },
234    {
235        "ArchStdEvent": "FP_SP_FIXED_OPS_SPEC",
236        "BriefDescription": "This event counts architecturally executed v8SIMD&FP single-precision arithmetic operation. See FP_SP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by the number of 32-bit elements for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC."
237    },
238    {
239        "ArchStdEvent": "FP_DP_SCALE_OPS_SPEC",
240        "BriefDescription": "This event counts architecturally executed SVE double-precision arithmetic operation. See FP_DP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 2, or by 4 for operations that would also be counted by SVE_FP_FMA_SPEC."
241    },
242    {
243        "ArchStdEvent": "FP_DP_FIXED_OPS_SPEC",
244        "BriefDescription": "This event counts architecturally executed v8SIMD&FP double-precision arithmetic operation. See FP_DP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 2 for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC."
245    },
246    {
247        "ArchStdEvent": "ASE_SVE_INT_DOT_SPEC",
248        "BriefDescription": "This event counts architecturally executed microarchitectural Advanced SIMD or SVE integer dot-product operation."
249    },
250    {
251        "ArchStdEvent": "ASE_SVE_INT_MMLA_SPEC",
252        "BriefDescription": "This event counts architecturally executed microarchitectural Advanced SIMD or SVE integer matrix multiply operation."
253    }
254]