stall.json

 1[
 2    {
 3        "ArchStdEvent": "STALL_FRONTEND",
 4        "BriefDescription": "This event counts every cycle counted by the CPU_CYCLES event on that no operation was issued because there are no operations available to issue for this PE from the frontend."
 5    },
 6    {
 7        "ArchStdEvent": "STALL_BACKEND",
 8        "BriefDescription": "This event counts every cycle counted by the CPU_CYCLES event on that no operation was issued because the backend is unable to accept any operation."
 9    },
10    {
11        "ArchStdEvent": "STALL",
12        "BriefDescription": "This event counts every cycle that no instruction was dispatched from decode unit."
13    },
14    {
15        "ArchStdEvent": "STALL_SLOT_BACKEND",
16        "BriefDescription": "This event counts every cycle that no instruction was dispatched from decode unit due to the backend."
17    },
18    {
19        "ArchStdEvent": "STALL_SLOT_FRONTEND",
20        "BriefDescription": "This event counts every cycle that no instruction was dispatched from decode unit due to the frontend."
21    },
22    {
23        "ArchStdEvent": "STALL_SLOT",
24        "BriefDescription": "This event counts every cycle that no instruction or operation Slot was dispatched from decode unit."
25    },
26    {
27        "ArchStdEvent": "STALL_BACKEND_MEM",
28        "BriefDescription": "This event counts every cycle that no instruction was dispatched from decode unit due to memory stall."
29    },
30    {
31        "ArchStdEvent": "STALL_FRONTEND_MEMBOUND",
32        "BriefDescription": "This event counts every cycle counted by STALL_FRONTEND when no instructions are delivered from the memory system."
33    },
34    {
35        "ArchStdEvent": "STALL_FRONTEND_L1I",
36        "BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_MEMBOUND when there is a demand instruction miss in the first level of instruction cache."
37    },
38    {
39        "ArchStdEvent": "STALL_FRONTEND_L2I",
40        "BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_MEMBOUND when there is a demand instruction miss in the second level of instruction cache."
41    },
42    {
43        "ArchStdEvent": "STALL_FRONTEND_MEM",
44        "BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_MEMBOUND when there is a demand instruction miss in the last level of instruction cache within the PE clock domain or a non-cacheable instruction fetch in progress."
45    },
46    {
47        "ArchStdEvent": "STALL_FRONTEND_CPUBOUND",
48        "BriefDescription": "This event counts every cycle counted by STALL_FRONTEND when the frontend is stalled on a frontend processor resource, not including memory."
49    },
50    {
51        "ArchStdEvent": "STALL_FRONTEND_FLOW",
52        "BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_CPUBOUND when the frontend is stalled on unavailability of prediction flow resources."
53    },
54    {
55        "ArchStdEvent": "STALL_FRONTEND_FLUSH",
56        "BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_CPUBOUND when the frontend is recovering from a pipeline flush."
57    },
58    {
59        "ArchStdEvent": "STALL_FRONTEND_RENAME",
60        "BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_CPUBOUND when operations are available from the frontend but at least one is not ready to be sent to the backend because no rename register is available."
61    },
62    {
63        "ArchStdEvent": "STALL_BACKEND_MEMBOUND",
64        "BriefDescription": "This event counts every cycle counted by STALL_BACKEND when the backend is waiting for a memory access to complete."
65    },
66    {
67        "ArchStdEvent": "STALL_BACKEND_L1D",
68        "BriefDescription": "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when there is a demand data miss in L1D cache."
69    },
70    {
71        "ArchStdEvent": "STALL_BACKEND_L2D",
72        "BriefDescription": "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when there is a demand data miss in L2 cache."
73    },
74    {
75        "ArchStdEvent": "STALL_BACKEND_CPUBOUND",
76        "BriefDescription": "This event counts every cycle counted by STALL_BACKEND when the backend is stalled on a processor resource, not including memory."
77    },
78    {
79        "ArchStdEvent": "STALL_BACKEND_BUSY",
80        "BriefDescription": "This event counts every cycle counted by STALL_BACKEND when operations are available from the frontend but the backend is not able to accept an operation because an execution unit is busy."
81    },
82    {
83        "ArchStdEvent": "STALL_BACKEND_RENAME",
84        "BriefDescription": "This event counts every cycle counted by STALL_BACKEND_CPUBOUND when operations are available from the frontend but at least one is not ready to be sent to the backend because no rename register is available."
85    },
86    {
87        "ArchStdEvent": "STALL_BACKEND_ATOMIC",
88        "BriefDescription": "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when the backend is processing an Atomic operation."
89    },
90    {
91        "ArchStdEvent": "STALL_BACKEND_MEMCPYSET",
92        "BriefDescription": "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when the backend is processing a Memory Copy or Set instruction."
93    }
94]