spec_operation.json

  1[
  2    {
  3        "ArchStdEvent": "BR_MIS_PRED",
  4        "BriefDescription": "This event counts each correction to the predicted program flow that occurs because of a misprediction from, or no prediction from, the branch prediction resources and that relates to instructions that the branch prediction resources are capable of predicting."
  5    },
  6    {
  7        "ArchStdEvent": "BR_PRED",
  8        "BriefDescription": "This event counts every branch or other change in the program flow that the branch prediction resources are capable of predicting."
  9    },
 10    {
 11        "ArchStdEvent": "INST_SPEC",
 12        "BriefDescription": "This event counts every architecturally executed instruction."
 13    },
 14    {
 15        "ArchStdEvent": "OP_SPEC",
 16        "BriefDescription": "This event counts every speculatively executed micro-operation."
 17    },
 18    {
 19        "ArchStdEvent": "LDREX_SPEC",
 20        "BriefDescription": "This event counts architecturally executed load-exclusive instructions."
 21    },
 22    {
 23        "ArchStdEvent": "STREX_SPEC",
 24        "BriefDescription": "This event counts architecturally executed store-exclusive instructions."
 25    },
 26    {
 27        "ArchStdEvent": "LD_SPEC",
 28        "BriefDescription": "This event counts architecturally executed memory-reading instructions, as defined by the LD_RETIRED event."
 29    },
 30    {
 31        "ArchStdEvent": "ST_SPEC",
 32        "BriefDescription": "This event counts architecturally executed memory-writing instructions, as defined by the ST_RETIRED event. This event counts DCZVA as a store operation."
 33    },
 34    {
 35        "ArchStdEvent": "LDST_SPEC",
 36        "BriefDescription": "This event counts architecturally executed memory-reading instructions and memory-writing instructions, as defined by the LD_RETIRED and ST_RETIRED events."
 37    },
 38    {
 39        "ArchStdEvent": "DP_SPEC",
 40        "BriefDescription": "This event counts architecturally executed integer data-processing instructions. See DP_SPEC of ARMv9 Reference Manual for more information."
 41    },
 42    {
 43        "ArchStdEvent": "ASE_SPEC",
 44        "BriefDescription": "This event counts architecturally executed Advanced SIMD data-processing instructions."
 45    },
 46    {
 47        "ArchStdEvent": "VFP_SPEC",
 48        "BriefDescription": "This event counts architecturally executed floating-point data-processing instructions."
 49    },
 50    {
 51        "ArchStdEvent": "PC_WRITE_SPEC",
 52        "BriefDescription": "This event counts only software changes of the PC that defined by the instruction architecturally executed, condition code check pass, software change of the PC event."
 53    },
 54    {
 55        "ArchStdEvent": "CRYPTO_SPEC",
 56        "BriefDescription": "This event counts architecturally executed cryptographic instructions, except PMULL and VMULL."
 57    },
 58    {
 59        "ArchStdEvent": "BR_IMMED_SPEC",
 60        "BriefDescription": "This event counts architecturally executed immediate branch instructions."
 61    },
 62    {
 63        "ArchStdEvent": "BR_RETURN_SPEC",
 64        "BriefDescription": "This event counts architecturally executed procedure return operations that defined by the BR_RETURN_RETIRED event."
 65    },
 66    {
 67        "ArchStdEvent": "BR_INDIRECT_SPEC",
 68        "BriefDescription": "This event counts architecturally executed indirect branch instructions that includes software change of the PC other than exception-generating instructions and immediate branch instructions."
 69    },
 70    {
 71        "ArchStdEvent": "ISB_SPEC",
 72        "BriefDescription": "This event counts architecturally executed Instruction Synchronization Barrier instructions."
 73    },
 74    {
 75        "ArchStdEvent": "DSB_SPEC",
 76        "BriefDescription": "This event counts architecturally executed Data Synchronization Barrier instructions."
 77    },
 78    {
 79        "ArchStdEvent": "DMB_SPEC",
 80        "BriefDescription": "This event counts architecturally executed Data Memory Barrier instructions, excluding the implied barrier operations of load/store operations with release consistency semantics."
 81    },
 82    {
 83        "ArchStdEvent": "CSDB_SPEC",
 84        "BriefDescription": "This event counts architecturally executed control speculation barrier instructions."
 85    },
 86    {
 87        "EventCode": "0x0108",
 88        "EventName": "PRD_SPEC",
 89        "BriefDescription": "This event counts architecturally executed operations that using predicate register."
 90    },
 91    {
 92        "EventCode": "0x0109",
 93        "EventName": "IEL_SPEC",
 94        "BriefDescription": "This event counts architecturally executed inter-element manipulation operation."
 95    },
 96    {
 97        "EventCode": "0x010A",
 98        "EventName": "IREG_SPEC",
 99        "BriefDescription": "This event counts architecturally executed inter-register manipulation operation."
100    },
101    {
102        "EventCode": "0x011A",
103        "EventName": "BC_LD_SPEC",
104        "BriefDescription": "This event counts architecturally executed SIMD broadcast floating-point load operation."
105    },
106    {
107        "EventCode": "0x011B",
108        "EventName": "DCZVA_SPEC",
109        "BriefDescription": "This event counts architecturally executed zero blocking operations due to the DC ZVA instruction."
110    },
111    {
112        "EventCode": "0x0121",
113        "EventName": "EFFECTIVE_INST_SPEC",
114        "BriefDescription": "This event counts architecturally executed instructions, excluding the MOVPRFX instruction."
115    },
116    {
117        "EventCode": "0x0123",
118        "EventName": "PRE_INDEX_SPEC",
119        "BriefDescription": "This event counts architecturally executed operations that uses pre-index as its addressing mode."
120    },
121    {
122        "EventCode": "0x0124",
123        "EventName": "POST_INDEX_SPEC",
124        "BriefDescription": "This event counts architecturally executed operations that uses post-index as its addressing mode."
125    },
126    {
127        "EventCode": "0x0139",
128        "EventName": "UOP_SPLIT",
129        "BriefDescription": "This event counts the occurrence count of the micro-operation split."
130    },
131    {
132        "ArchStdEvent": "ASE_INST_SPEC",
133        "BriefDescription": "This event counts architecturally executed Advanced SIMD operation."
134    },
135    {
136        "ArchStdEvent": "INT_SPEC",
137        "BriefDescription": "This event counts architecturally executed operations due to scalar, Advanced SIMD, and SVE instructions listed in Integer instructions section of ARMv9 Reference Manual."
138    },
139    {
140        "ArchStdEvent": "INT_DIV_SPEC",
141        "BriefDescription": "This event counts architecturally executed integer divide operation."
142    },
143    {
144        "ArchStdEvent": "INT_DIV64_SPEC",
145        "BriefDescription": "This event counts architecturally executed 64-bit integer divide operation."
146    },
147    {
148        "ArchStdEvent": "INT_MUL_SPEC",
149        "BriefDescription": "This event counts architecturally executed integer multiply operation."
150    },
151    {
152        "ArchStdEvent": "INT_MUL64_SPEC",
153        "BriefDescription": "This event counts architecturally executed integer 64-bit x 64-bit multiply operation."
154    },
155    {
156        "ArchStdEvent": "INT_MULH64_SPEC",
157        "BriefDescription": "This event counts architecturally executed integer 64-bit x 64-bit multiply returning high part operation."
158    },
159    {
160        "ArchStdEvent": "NONFP_SPEC",
161        "BriefDescription": "This event counts architecturally executed non-floating-point operation."
162    },
163    {
164        "ArchStdEvent": "INT_SCALE_OPS_SPEC",
165        "BriefDescription": "This event counts each integer ALU operation counted by SVE_INT_SPEC. See ALU operation counts section of ARMv9 Reference Manual for information on the counter increment for different types of instruction."
166    },
167    {
168        "ArchStdEvent": "INT_FIXED_OPS_SPEC",
169        "BriefDescription": "This event counts each integer ALU operation counted by INT_SPEC that is not counted by SVE_INT_SPEC. See ALU operation counts section of ARMv9 Reference Manual for information on the counter increment for different types of instruction."
170    }
171]