l3_cache.json

  1[
  2    {
  3        "ArchStdEvent": "L3D_CACHE",
  4        "BriefDescription": "This event counts operations that cause a cache access to the L3 cache, as defined by the sum of L2D_CACHE_REFILL_L3D_CACHE and L2D_CACHE_WB_VICTIM_CLEAN events."
  5    },
  6    {
  7        "ArchStdEvent": "L3D_CACHE_RD",
  8        "BriefDescription": "This event counts access counted by L3D_CACHE that is a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_CACHE events."
  9    },
 10    {
 11        "EventCode": "0x0390",
 12        "EventName": "L2D_CACHE_REFILL_L3D_CACHE",
 13        "BriefDescription": "This event counts operations that cause a cache access to the L3 cache."
 14    },
 15    {
 16        "EventCode": "0x0391",
 17        "EventName": "L2D_CACHE_REFILL_L3D_CACHE_DM",
 18        "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by demand access."
 19    },
 20    {
 21        "EventCode": "0x0392",
 22        "EventName": "L2D_CACHE_REFILL_L3D_CACHE_DM_RD",
 23        "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by demand read access."
 24    },
 25    {
 26        "EventCode": "0x0393",
 27        "EventName": "L2D_CACHE_REFILL_L3D_CACHE_DM_WR",
 28        "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by demand write access."
 29    },
 30    {
 31        "EventCode": "0x0394",
 32        "EventName": "L2D_CACHE_REFILL_L3D_CACHE_PRF",
 33        "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by hardware prefetch or software prefetch."
 34    },
 35    {
 36        "EventCode": "0x0395",
 37        "EventName": "L2D_CACHE_REFILL_L3D_CACHE_HWPRF",
 38        "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by hardware prefetch."
 39    },
 40    {
 41        "EventCode": "0x0396",
 42        "EventName": "L2D_CACHE_REFILL_L3D_MISS",
 43        "BriefDescription": "This event counts operations that cause a miss of the L3 cache. Note: This event may count inaccurately."
 44    },
 45    {
 46        "EventCode": "0x0397",
 47        "EventName": "L2D_CACHE_REFILL_L3D_MISS_DM",
 48        "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by demand access."
 49    },
 50    {
 51        "EventCode": "0x0398",
 52        "EventName": "L2D_CACHE_REFILL_L3D_MISS_DM_RD",
 53        "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by demand read access."
 54    },
 55    {
 56        "EventCode": "0x0399",
 57        "EventName": "L2D_CACHE_REFILL_L3D_MISS_DM_WR",
 58        "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by demand write access."
 59    },
 60    {
 61        "EventCode": "0x039A",
 62        "EventName": "L2D_CACHE_REFILL_L3D_MISS_PRF",
 63        "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by hardware prefetch or software prefetch. Note: This event may count inaccurately."
 64    },
 65    {
 66        "EventCode": "0x039B",
 67        "EventName": "L2D_CACHE_REFILL_L3D_MISS_HWPRF",
 68        "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by hardware prefetch. Note: This event may count inaccurately."
 69    },
 70    {
 71        "EventCode": "0x039C",
 72        "EventName": "L2D_CACHE_REFILL_L3D_HIT",
 73        "BriefDescription": "This event counts operations that cause a hit of the L3 cache. Note: This event may count inaccurately."
 74    },
 75    {
 76        "EventCode": "0x039D",
 77        "EventName": "L2D_CACHE_REFILL_L3D_HIT_DM",
 78        "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_HIT caused by demand access."
 79    },
 80    {
 81        "EventCode": "0x039E",
 82        "EventName": "L2D_CACHE_REFILL_L3D_HIT_DM_RD",
 83        "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_HIT caused by demand read access."
 84    },
 85    {
 86        "EventCode": "0x039F",
 87        "EventName": "L2D_CACHE_REFILL_L3D_HIT_DM_WR",
 88        "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_HIT caused by demand write access."
 89    },
 90    {
 91        "EventCode": "0x03A0",
 92        "EventName": "L2D_CACHE_REFILL_L3D_HIT_PRF",
 93        "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_HIT caused by hardware prefetch or software prefetch. Note: This event may count inaccurately."
 94    },
 95    {
 96        "EventCode": "0x03A1",
 97        "EventName": "L2D_CACHE_REFILL_L3D_HIT_HWPRF",
 98        "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_HIT caused by hardware prefetch. Note: This event may count inaccurately."
 99    },
100    {
101        "EventCode": "0x03A3",
102        "EventName": "L2D_CACHE_REFILL_L3D_MISS_DM_PFTGT_HIT",
103        "BriefDescription": "This event counts the number of L3 cache misses caused by demand access where the requests hit the PFTGT buffer."
104    },
105    {
106        "EventCode": "0x03A4",
107        "EventName": "L2D_CACHE_REFILL_L3D_MISS_DM_RD_PFTGT_HIT",
108        "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_DM_PFTGT_HIT caused by read access."
109    },
110    {
111        "EventCode": "0x03A5",
112        "EventName": "L2D_CACHE_REFILL_L3D_MISS_DM_WR_PFTGT_HIT",
113        "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_DM_PFTGT_HIT caused by write access."
114    },
115    {
116        "EventCode": "0x03A6",
117        "EventName": "L2D_CACHE_REFILL_L3D_MISS_DM_L_MEM",
118        "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_DM where the requests access the memory in the same socket as the requests."
119    },
120    {
121        "EventCode": "0x03A7",
122        "EventName": "L2D_CACHE_REFILL_L3D_MISS_DM_FR_MEM",
123        "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_DM where the requests access the memory in the different socket from the requests."
124    },
125    {
126        "EventCode": "0x03A8",
127        "EventName": "L2D_CACHE_REFILL_L3D_MISS_DM_L_L2",
128        "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_DM where the requests access the different L2 cache from the requests in the same Numa nodes as the requests."
129    },
130    {
131        "EventCode": "0x03A9",
132        "EventName": "L2D_CACHE_REFILL_L3D_MISS_DM_NR_L2",
133        "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_DM where the requests access L2 cache in the different Numa nodes from the requests in the same socket as the requests."
134    },
135    {
136        "EventCode": "0x03AA",
137        "EventName": "L2D_CACHE_REFILL_L3D_MISS_DM_NR_L3",
138        "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_DM where the requests access L3 cache in the different Numa nodes from the requests in the same socket as the requests."
139    },
140    {
141        "EventCode": "0x03AB",
142        "EventName": "L2D_CACHE_REFILL_L3D_MISS_DM_FR_L2",
143        "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_DM where the requests access L2 cache in the different socket from the requests."
144    },
145    {
146        "EventCode": "0x03AC",
147        "EventName": "L2D_CACHE_REFILL_L3D_MISS_DM_FR_L3",
148        "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS_DM where the requests access L3 cache in the different socket from the requests."
149    },
150    {
151        "ArchStdEvent": "L3D_CACHE_LMISS_RD",
152        "BriefDescription": "This event counts access counted by L3D_CACHE that is not completed by the L3 cache, and a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_MISS events. Note: This event may count inaccurately."
153    }
154]