l1i_cache.json

 1[
 2    {
 3        "ArchStdEvent": "L1I_CACHE_REFILL",
 4        "BriefDescription": "This event counts operations that cause a refill of the L1I cache. See L1I_CACHE_REFILL of ARMv9 Reference Manual for more information."
 5    },
 6    {
 7        "ArchStdEvent": "L1I_CACHE",
 8        "BriefDescription": "This event counts operations that cause a cache access to the L1I cache. See L1I_CACHE of ARMv9 Reference Manual for more information."
 9    },
10    {
11        "EventCode": "0x0207",
12        "EventName": "L1I_CACHE_DM_RD",
13        "BriefDescription": "This event counts L1I_CACHE caused by demand read access."
14    },
15    {
16        "EventCode": "0x020F",
17        "EventName": "L1I_CACHE_REFILL_DM_RD",
18        "BriefDescription": "This event counts L1I_CACHE_REFILL caused by demand read access."
19    },
20    {
21        "ArchStdEvent": "L1I_CACHE_LMISS",
22        "BriefDescription": "This event counts operations that cause a refill of the L1I cache that incurs additional latency."
23    },
24    {
25        "ArchStdEvent": "L1I_CACHE_HWPRF",
26        "BriefDescription": "This event counts L1I_CACHE caused by hardware prefetch."
27    },
28    {
29        "ArchStdEvent": "L1I_CACHE_REFILL_HWPRF",
30        "BriefDescription": "This event counts L1I_CACHE_REFILL caused by hardware prefetch."
31    },
32    {
33        "ArchStdEvent": "L1I_CACHE_HIT_RD",
34        "BriefDescription": "This event counts demand fetch counted by L1I_CACHE_DM_RD that hits in the Level 1 instruction cache."
35    },
36    {
37        "ArchStdEvent": "L1I_CACHE_HIT",
38        "BriefDescription": "This event counts access counted by L1I_CACHE that hits in the Level 1 instruction cache."
39    },
40    {
41        "ArchStdEvent": "L1I_LFB_HIT_RD",
42        "BriefDescription": "This event counts demand access counted by L1I_CACHE_HIT_RD that hits a cache line that is in the process of being loaded into the Level 1 instruction cache."
43    },
44    {
45        "ArchStdEvent": "L1I_CACHE_REFILL_PRF",
46        "BriefDescription": "This event counts L1I_CACHE_REFILL caused by hardware prefetch or software prefetch."
47    },
48    {
49        "ArchStdEvent": "L1I_CACHE_REFILL_PERCYC",
50        "BriefDescription": "This counter counts by the number of cache refills counted by L1I_CACHE_REFILL in progress on each Processor cycle."
51    }
52]