l1i_cache.json

 1[
 2    {
 3        "ArchStdEvent": "L1I_CACHE_REFILL",
 4        "PublicDescription": "Counts cache line refills in the level 1 instruction cache caused by a missed instruction fetch. Instruction fetches may include accessing multiple instructions, but the single cache line allocation is counted once."
 5    },
 6    {
 7        "ArchStdEvent": "L1I_CACHE",
 8        "PublicDescription": "Counts instruction fetches which access the level 1 instruction cache. Instruction cache accesses caused by cache maintenance operations are not counted."
 9    },
10    {
11        "ArchStdEvent": "L1I_CACHE_LMISS",
12        "PublicDescription": "Counts cache line refills into the level 1 instruction cache, that incurred additional latency."
13    },
14    {
15        "ArchStdEvent": "L1I_CACHE_RD",
16        "PublicDescription": "Counts demand instruction fetches which access the level 1 instruction cache."
17    },
18    {
19        "ArchStdEvent": "L1I_CACHE_PRFM",
20        "PublicDescription": "Counts instruction fetches generated by software preload or prefetch instructions which access the level 1 instruction cache."
21    },
22    {
23        "ArchStdEvent": "L1I_CACHE_HWPRF",
24        "PublicDescription": "Counts instruction fetches which access the level 1 instruction cache generated by the hardware prefetcher."
25    },
26    {
27        "ArchStdEvent": "L1I_CACHE_REFILL_PRFM",
28        "PublicDescription": "Counts cache line refills in the level 1 instruction cache caused by a missed instruction fetch generated by software preload or prefetch instructions. Instruction fetches may include accessing multiple instructions, but the single cache line allocation is counted once."
29    },
30    {
31        "ArchStdEvent": "L1I_CACHE_HIT_RD",
32        "PublicDescription": "Counts demand instruction fetches that access the level 1 instruction cache and hit in the L1 instruction cache."
33    },
34    {
35        "ArchStdEvent": "L1I_CACHE_HIT_RD_FPRFM",
36        "PublicDescription": "Counts demand instruction fetches that access the level 1 instruction cache that hit in the L1 instruction cache and the line was requested by a software prefetch."
37    },
38    {
39        "ArchStdEvent": "L1I_CACHE_HIT_RD_FHWPRF",
40        "PublicDescription": "Counts demand instruction fetches generated by hardware prefetch that access the level 1 instruction cache and hit in the L1 instruction cache."
41    },
42    {
43        "ArchStdEvent": "L1I_CACHE_HIT",
44        "PublicDescription": "Counts instruction fetches that access the level 1 instruction cache and hit in the level 1 instruction cache. Instruction cache accesses caused by cache maintenance operations are not counted."
45    },
46    {
47        "ArchStdEvent": "L1I_CACHE_HIT_PRFM",
48        "PublicDescription": "Counts instruction fetches generated by software preload or prefetch instructions that access the level 1 instruction cache and hit in the level 1 instruction cache."
49    },
50    {
51        "ArchStdEvent": "L1I_LFB_HIT_RD",
52        "PublicDescription": "Counts demand instruction fetches that access the level 1 instruction cache and hit in a line that is in the process of being loaded into the level 1 instruction cache."
53    },
54    {
55        "ArchStdEvent": "L1I_LFB_HIT_RD_FPRFM",
56        "PublicDescription": "Counts demand instruction fetches generated by software prefetch instructions that access the level 1 instruction cache and hit in a line that is in the process of being loaded into the level 1 instruction cache."
57    },
58    {
59        "ArchStdEvent": "L1I_LFB_HIT_RD_FHWPRF",
60        "PublicDescription": "Counts demand instruction fetches generated by hardware prefetch that access the level 1 instruction cache and hit in a line that is in the process of being loaded into the level 1 instruction cache."
61    }
62]