bus.json

 1[
 2    {
 3        "PublicDescription": "The number of core clock cycles",
 4        "ArchStdEvent": "CPU_CYCLES",
 5        "BriefDescription": "The number of core clock cycles."
 6    },
 7    {
 8        "PublicDescription": "This event counts for every beat of data transferred over the data channels between the core and the SCU. If both read and write data beats are transferred on a given cycle, this event is counted twice on that cycle. This event counts the sum of BUS_ACCESS_RD and BUS_ACCESS_WR.",
 9        "ArchStdEvent": "BUS_ACCESS"
10    },
11    {
12        "PublicDescription": "This event duplicates CPU_CYCLES.",
13        "ArchStdEvent": "BUS_CYCLES"
14    },
15    {
16        "ArchStdEvent":  "BUS_ACCESS_RD"
17    },
18    {
19        "ArchStdEvent":  "BUS_ACCESS_WR"
20    }
21]