cache.json

  1[
  2    {
  3        "ArchStdEvent": "L1I_CACHE_REFILL"
  4    },
  5    {
  6        "ArchStdEvent": "L1I_TLB_REFILL"
  7    },
  8    {
  9        "ArchStdEvent": "L1D_CACHE_REFILL"
 10    },
 11    {
 12        "ArchStdEvent": "L1D_CACHE"
 13    },
 14    {
 15        "ArchStdEvent": "L1D_TLB_REFILL"
 16    },
 17    {
 18        "ArchStdEvent": "L1I_CACHE"
 19    },
 20    {
 21        "ArchStdEvent": "L1D_CACHE_WB"
 22    },
 23    {
 24        "ArchStdEvent": "L2D_CACHE"
 25    },
 26    {
 27        "ArchStdEvent": "L2D_CACHE_REFILL"
 28    },
 29    {
 30        "ArchStdEvent": "L2D_CACHE_WB"
 31    },
 32    {
 33        "ArchStdEvent": "L1D_CACHE_RD"
 34    },
 35    {
 36        "ArchStdEvent": "L1D_CACHE_WR"
 37    },
 38    {
 39        "ArchStdEvent": "L2D_CACHE_RD"
 40    },
 41    {
 42        "ArchStdEvent": "L2D_CACHE_WR"
 43    },
 44    {
 45        "ArchStdEvent": "L2D_CACHE_WB_VICTIM"
 46    },
 47    {
 48        "ArchStdEvent": "L2D_CACHE_WB_CLEAN"
 49    },
 50    {
 51        "ArchStdEvent": "L2D_CACHE_INVAL"
 52    },
 53    {
 54        "PublicDescription": "Number of ways read in the instruction cache - Tag RAM",
 55        "EventCode": "0xC2",
 56        "EventName": "I_TAG_RAM_RD",
 57        "BriefDescription": "Number of ways read in the instruction cache - Tag RAM"
 58    },
 59    {
 60        "PublicDescription": "Number of ways read in the instruction cache - Data RAM",
 61        "EventCode": "0xC3",
 62        "EventName": "I_DATA_RAM_RD",
 63        "BriefDescription": "Number of ways read in the instruction cache - Data RAM"
 64    },
 65    {
 66        "PublicDescription": "Number of ways read in the instruction BTAC RAM",
 67        "EventCode": "0xC4",
 68        "EventName": "I_BTAC_RAM_RD",
 69        "BriefDescription": "Number of ways read in the instruction BTAC RAM"
 70    },
 71    {
 72        "PublicDescription": "Level 1 PLD TLB refill",
 73        "EventCode": "0xE7",
 74        "EventName": "PLD_UTLB_REFILL",
 75        "BriefDescription": "Level 1 PLD TLB refill"
 76    },
 77    {
 78        "PublicDescription": "Level 1 CP15 TLB refill",
 79        "EventCode": "0xE8",
 80        "EventName": "CP15_UTLB_REFILL",
 81        "BriefDescription": "Level 1 CP15 TLB refill"
 82    },
 83    {
 84        "PublicDescription": "Level 1 TLB flush",
 85        "EventCode": "0xE9",
 86        "EventName": "UTLB_FLUSH",
 87        "BriefDescription": "Level 1 TLB flush"
 88    },
 89    {
 90        "PublicDescription": "Level 2 TLB access",
 91        "EventCode": "0xEA",
 92        "EventName": "TLB_ACCESS",
 93        "BriefDescription": "Level 2 TLB access"
 94    },
 95    {
 96        "PublicDescription": "Level 2 TLB miss",
 97        "EventCode": "0xEB",
 98        "EventName": "TLB_MISS",
 99        "BriefDescription": "Level 2 TLB miss"
100    },
101    {
102        "PublicDescription": "Data cache hit in itself due to VIPT aliasing",
103        "EventCode": "0xEC",
104        "EventName": "DCACHE_SELF_HIT_VIPT",
105        "BriefDescription": "Data cache hit in itself due to VIPT aliasing"
106    }
107]