cache.json

  1[
  2    {
  3        "ArchStdEvent": "L1D_CACHE_RD"
  4    },
  5    {
  6        "ArchStdEvent": "L1D_CACHE_WR"
  7    },
  8    {
  9        "ArchStdEvent": "L1D_CACHE_REFILL_RD"
 10    },
 11    {
 12        "ArchStdEvent": "L1D_CACHE_INVAL",
 13        "Errata": "Errata AC04_CPU_1",
 14        "BriefDescription": "L1D cache invalidate. Impacted by errata -"
 15    },
 16    {
 17        "ArchStdEvent": "L1D_TLB_REFILL_RD"
 18    },
 19    {
 20        "ArchStdEvent": "L1D_TLB_REFILL_WR"
 21    },
 22    {
 23        "ArchStdEvent": "L2D_CACHE_RD"
 24    },
 25    {
 26        "ArchStdEvent": "L2D_CACHE_WR"
 27    },
 28    {
 29        "ArchStdEvent": "L2D_CACHE_REFILL_RD"
 30    },
 31    {
 32        "ArchStdEvent": "L2D_CACHE_REFILL_WR"
 33    },
 34    {
 35        "ArchStdEvent": "L2D_CACHE_WB_VICTIM"
 36    },
 37    {
 38        "ArchStdEvent": "L2D_CACHE_WB_CLEAN"
 39    },
 40    {
 41        "ArchStdEvent": "L2D_CACHE_INVAL"
 42    },
 43    {
 44        "ArchStdEvent": "L1I_CACHE_REFILL"
 45    },
 46    {
 47        "ArchStdEvent": "L1I_TLB_REFILL"
 48    },
 49    {
 50        "ArchStdEvent": "L1D_CACHE_REFILL"
 51    },
 52    {
 53        "ArchStdEvent": "L1D_CACHE"
 54    },
 55    {
 56        "ArchStdEvent": "L1D_TLB_REFILL"
 57    },
 58    {
 59        "ArchStdEvent": "L1I_CACHE"
 60    },
 61    {
 62        "ArchStdEvent": "L2D_CACHE"
 63    },
 64    {
 65        "ArchStdEvent": "L2D_CACHE_REFILL"
 66    },
 67    {
 68        "ArchStdEvent": "L2D_CACHE_WB"
 69    },
 70    {
 71        "ArchStdEvent": "L1D_TLB"
 72    },
 73    {
 74        "ArchStdEvent": "L1I_TLB"
 75    },
 76    {
 77        "ArchStdEvent": "L2D_TLB_REFILL"
 78    },
 79    {
 80        "ArchStdEvent": "L2I_TLB_REFILL"
 81    },
 82    {
 83        "ArchStdEvent": "L2D_TLB"
 84    },
 85    {
 86        "ArchStdEvent": "L2I_TLB"
 87    },
 88    {
 89        "ArchStdEvent": "DTLB_WALK"
 90    },
 91    {
 92        "ArchStdEvent": "ITLB_WALK"
 93    },
 94    {
 95        "ArchStdEvent": "L1D_CACHE_REFILL_WR"
 96    },
 97    {
 98        "ArchStdEvent": "L1D_CACHE_LMISS_RD"
 99    },
100    {
101        "ArchStdEvent": "L1I_CACHE_LMISS"
102    },
103    {
104        "ArchStdEvent": "L2D_CACHE_LMISS_RD"
105    },
106    {
107        "PublicDescription": "Level 1 data or unified cache demand access",
108        "EventCode": "0x8140",
109        "EventName": "L1D_CACHE_RW",
110        "BriefDescription": "Level 1 data or unified cache demand access"
111    },
112    {
113        "PublicDescription": "Level 1 data or unified cache preload or prefetch",
114        "EventCode": "0x8142",
115        "EventName": "L1D_CACHE_PRFM",
116        "BriefDescription": "Level 1 data or unified cache preload or prefetch"
117    },
118    {
119        "PublicDescription": "Level 1 data or unified cache refill, preload or prefetch",
120        "EventCode": "0x8146",
121        "EventName": "L1D_CACHE_REFILL_PRFM",
122        "BriefDescription": "Level 1 data or unified cache refill, preload or prefetch"
123    },
124    {
125        "ArchStdEvent": "L1D_TLB_RD"
126    },
127    {
128        "ArchStdEvent": "L1D_TLB_WR"
129    },
130    {
131        "ArchStdEvent": "L2D_TLB_REFILL_RD"
132    },
133    {
134        "ArchStdEvent": "L2D_TLB_REFILL_WR"
135    },
136    {
137        "ArchStdEvent": "L2D_TLB_RD"
138    },
139    {
140        "ArchStdEvent": "L2D_TLB_WR"
141    },
142    {
143        "PublicDescription": "L1D TLB miss",
144        "EventCode": "0xD600",
145        "EventName": "L1D_TLB_MISS",
146        "BriefDescription": "L1D TLB miss"
147    },
148    {
149        "PublicDescription": "Level 1 prefetcher, load prefetch requests generated",
150        "EventCode": "0xd606",
151        "EventName": "L1_PREFETCH_LD_GEN",
152        "BriefDescription": "Level 1 prefetcher, load prefetch requests generated"
153    },
154    {
155        "PublicDescription": "Level 1 prefetcher, load prefetch fills into the level 1 cache",
156        "EventCode": "0xd607",
157        "EventName": "L1_PREFETCH_LD_FILL",
158        "BriefDescription": "Level 1 prefetcher, load prefetch fills into the level 1 cache"
159    },
160    {
161        "PublicDescription": "Level 1 prefetcher, load prefetch to level 2 generated",
162        "EventCode": "0xd608",
163        "EventName": "L1_PREFETCH_L2_REQ",
164        "BriefDescription": "Level 1 prefetcher, load prefetch to level 2 generated"
165    },
166    {
167        "PublicDescription": "L1 prefetcher, distance was reset",
168        "EventCode": "0xd609",
169        "EventName": "L1_PREFETCH_DIST_RST",
170        "BriefDescription": "L1 prefetcher, distance was reset"
171    },
172    {
173        "PublicDescription": "L1 prefetcher, distance was increased",
174        "EventCode": "0xd60a",
175        "EventName": "L1_PREFETCH_DIST_INC",
176        "BriefDescription": "L1 prefetcher, distance was increased"
177    },
178    {
179        "PublicDescription": "Level 1 prefetcher, table entry is trained",
180        "EventCode": "0xd60b",
181        "EventName": "L1_PREFETCH_ENTRY_TRAINED",
182        "BriefDescription": "Level 1 prefetcher, table entry is trained"
183    },
184    {
185        "PublicDescription": "L1 data cache refill - Read or Write",
186        "EventCode": "0xd60e",
187        "EventName": "L1D_CACHE_REFILL_RW",
188        "BriefDescription": "L1 data cache refill - Read or Write"
189    },
190    {
191        "PublicDescription": "Level 2 cache refill from instruction-side miss, including IMMU refills",
192        "EventCode": "0xD701",
193        "EventName": "L2C_INST_REFILL",
194        "BriefDescription": "Level 2 cache refill from instruction-side miss, including IMMU refills"
195    },
196    {
197        "PublicDescription": "Level 2 cache refill from data-side miss, including DMMU refills",
198        "EventCode": "0xD702",
199        "EventName": "L2C_DATA_REFILL",
200        "BriefDescription": "Level 2 cache refill from data-side miss, including DMMU refills"
201    },
202    {
203        "PublicDescription": "Level 2 cache prefetcher, load prefetch requests generated",
204        "EventCode": "0xD703",
205        "EventName": "L2_PREFETCH_REQ",
206        "BriefDescription": "Level 2 cache prefetcher, load prefetch requests generated"
207    }
208]