memory.json

 1[
 2    {
 3        "ArchStdEvent": "LD_RETIRED",
 4        "Errata": "Errata AC03_CPU_52",
 5        "BriefDescription": "Instruction architecturally executed, condition code check pass, load. Impacted by errata -"
 6    },
 7    {
 8        "ArchStdEvent": "MEM_ACCESS_RD"
 9    },
10    {
11        "ArchStdEvent": "MEM_ACCESS_WR"
12    },
13    {
14        "ArchStdEvent": "UNALIGNED_LD_SPEC"
15    },
16    {
17        "ArchStdEvent": "UNALIGNED_ST_SPEC"
18    },
19    {
20        "ArchStdEvent": "UNALIGNED_LDST_SPEC"
21    },
22    {
23        "ArchStdEvent": "LD_ALIGN_LAT"
24    },
25    {
26        "ArchStdEvent": "ST_ALIGN_LAT"
27    },
28    {
29        "ArchStdEvent": "MEM_ACCESS"
30    },
31    {
32        "ArchStdEvent": "MEMORY_ERROR"
33    },
34    {
35        "ArchStdEvent": "LDST_ALIGN_LAT"
36    },
37    {
38        "ArchStdEvent": "MEM_ACCESS_CHECKED"
39    },
40    {
41        "ArchStdEvent": "MEM_ACCESS_CHECKED_RD"
42    },
43    {
44        "ArchStdEvent": "MEM_ACCESS_CHECKED_WR"
45    }
46]