cache.json

  1[
  2    {
  3        "ArchStdEvent": "L1D_CACHE_RD"
  4    },
  5    {
  6        "ArchStdEvent": "L1D_CACHE_WR"
  7    },
  8    {
  9        "ArchStdEvent": "L1D_CACHE_REFILL_RD"
 10    },
 11    {
 12        "ArchStdEvent": "L1D_CACHE_INVAL",
 13        "Errata": "Errata AC03_CPU_41",
 14        "BriefDescription": "L1D cache invalidate. Impacted by errata -"
 15    },
 16    {
 17        "ArchStdEvent": "L1D_TLB_REFILL_RD"
 18    },
 19    {
 20        "ArchStdEvent": "L1D_TLB_REFILL_WR"
 21    },
 22    {
 23        "ArchStdEvent": "L2D_CACHE_RD"
 24    },
 25    {
 26        "ArchStdEvent": "L2D_CACHE_WR"
 27    },
 28    {
 29        "ArchStdEvent": "L2D_CACHE_REFILL_RD"
 30    },
 31    {
 32        "ArchStdEvent": "L2D_CACHE_REFILL_WR"
 33    },
 34    {
 35        "ArchStdEvent": "L2D_CACHE_WB_VICTIM"
 36    },
 37    {
 38        "ArchStdEvent": "L2D_CACHE_WB_CLEAN"
 39    },
 40    {
 41        "ArchStdEvent": "L2D_CACHE_INVAL"
 42    },
 43    {
 44        "ArchStdEvent": "L1I_CACHE_REFILL"
 45    },
 46    {
 47        "ArchStdEvent": "L1I_TLB_REFILL"
 48    },
 49    {
 50        "ArchStdEvent": "L1D_CACHE_REFILL"
 51    },
 52    {
 53        "ArchStdEvent": "L1D_CACHE"
 54    },
 55    {
 56        "ArchStdEvent": "L1D_TLB_REFILL"
 57    },
 58    {
 59        "ArchStdEvent": "L1I_CACHE"
 60    },
 61    {
 62        "ArchStdEvent": "L2D_CACHE"
 63    },
 64    {
 65        "ArchStdEvent": "L2D_CACHE_REFILL"
 66    },
 67    {
 68        "ArchStdEvent": "L2D_CACHE_WB"
 69    },
 70    {
 71        "ArchStdEvent": "L1D_TLB"
 72    },
 73    {
 74        "ArchStdEvent": "L1I_TLB"
 75    },
 76    {
 77        "ArchStdEvent": "L2D_TLB_REFILL"
 78    },
 79    {
 80        "ArchStdEvent": "L2I_TLB_REFILL"
 81    },
 82    {
 83        "ArchStdEvent": "L2D_TLB"
 84    },
 85    {
 86        "ArchStdEvent": "L2I_TLB"
 87    },
 88    {
 89        "ArchStdEvent": "DTLB_WALK"
 90    },
 91    {
 92        "ArchStdEvent": "ITLB_WALK"
 93    },
 94    {
 95        "ArchStdEvent": "L1D_CACHE_LMISS_RD"
 96    },
 97    {
 98        "ArchStdEvent": "L1I_CACHE_LMISS"
 99    },
100    {
101        "ArchStdEvent": "L2D_CACHE_LMISS_RD"
102    }
103]