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esr.h

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linux-6.19.14/tools/arch/arm64/include/asm/esr.h C 
  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (C) 2013 - ARM Ltd
  4 * Author: Marc Zyngier <marc.zyngier@arm.com>
  5 */
  6
  7#ifndef __ASM_ESR_H
  8#define __ASM_ESR_H
  9
 10#include <asm/sysreg.h>
 11
 12#define ESR_ELx_EC_UNKNOWN	UL(0x00)
 13#define ESR_ELx_EC_WFx		UL(0x01)
 14/* Unallocated EC: 0x02 */
 15#define ESR_ELx_EC_CP15_32	UL(0x03)
 16#define ESR_ELx_EC_CP15_64	UL(0x04)
 17#define ESR_ELx_EC_CP14_MR	UL(0x05)
 18#define ESR_ELx_EC_CP14_LS	UL(0x06)
 19#define ESR_ELx_EC_FP_ASIMD	UL(0x07)
 20#define ESR_ELx_EC_CP10_ID	UL(0x08)	/* EL2 only */
 21#define ESR_ELx_EC_PAC		UL(0x09)	/* EL2 and above */
 22/* Unallocated EC: 0x0A - 0x0B */
 23#define ESR_ELx_EC_CP14_64	UL(0x0C)
 24#define ESR_ELx_EC_BTI		UL(0x0D)
 25#define ESR_ELx_EC_ILL		UL(0x0E)
 26/* Unallocated EC: 0x0F - 0x10 */
 27#define ESR_ELx_EC_SVC32	UL(0x11)
 28#define ESR_ELx_EC_HVC32	UL(0x12)	/* EL2 only */
 29#define ESR_ELx_EC_SMC32	UL(0x13)	/* EL2 and above */
 30/* Unallocated EC: 0x14 */
 31#define ESR_ELx_EC_SVC64	UL(0x15)
 32#define ESR_ELx_EC_HVC64	UL(0x16)	/* EL2 and above */
 33#define ESR_ELx_EC_SMC64	UL(0x17)	/* EL2 and above */
 34#define ESR_ELx_EC_SYS64	UL(0x18)
 35#define ESR_ELx_EC_SVE		UL(0x19)
 36#define ESR_ELx_EC_ERET		UL(0x1a)	/* EL2 only */
 37/* Unallocated EC: 0x1B */
 38#define ESR_ELx_EC_FPAC		UL(0x1C)	/* EL1 and above */
 39#define ESR_ELx_EC_SME		UL(0x1D)
 40/* Unallocated EC: 0x1E */
 41#define ESR_ELx_EC_IMP_DEF	UL(0x1f)	/* EL3 only */
 42#define ESR_ELx_EC_IABT_LOW	UL(0x20)
 43#define ESR_ELx_EC_IABT_CUR	UL(0x21)
 44#define ESR_ELx_EC_PC_ALIGN	UL(0x22)
 45/* Unallocated EC: 0x23 */
 46#define ESR_ELx_EC_DABT_LOW	UL(0x24)
 47#define ESR_ELx_EC_DABT_CUR	UL(0x25)
 48#define ESR_ELx_EC_SP_ALIGN	UL(0x26)
 49#define ESR_ELx_EC_MOPS		UL(0x27)
 50#define ESR_ELx_EC_FP_EXC32	UL(0x28)
 51/* Unallocated EC: 0x29 - 0x2B */
 52#define ESR_ELx_EC_FP_EXC64	UL(0x2C)
 53/* Unallocated EC: 0x2D - 0x2E */
 54#define ESR_ELx_EC_SERROR	UL(0x2F)
 55#define ESR_ELx_EC_BREAKPT_LOW	UL(0x30)
 56#define ESR_ELx_EC_BREAKPT_CUR	UL(0x31)
 57#define ESR_ELx_EC_SOFTSTP_LOW	UL(0x32)
 58#define ESR_ELx_EC_SOFTSTP_CUR	UL(0x33)
 59#define ESR_ELx_EC_WATCHPT_LOW	UL(0x34)
 60#define ESR_ELx_EC_WATCHPT_CUR	UL(0x35)
 61/* Unallocated EC: 0x36 - 0x37 */
 62#define ESR_ELx_EC_BKPT32	UL(0x38)
 63/* Unallocated EC: 0x39 */
 64#define ESR_ELx_EC_VECTOR32	UL(0x3A)	/* EL2 only */
 65/* Unallocated EC: 0x3B */
 66#define ESR_ELx_EC_BRK64	UL(0x3C)
 67/* Unallocated EC: 0x3D - 0x3F */
 68#define ESR_ELx_EC_MAX		UL(0x3F)
 69
 70#define ESR_ELx_EC_SHIFT	(26)
 71#define ESR_ELx_EC_WIDTH	(6)
 72#define ESR_ELx_EC_MASK		(UL(0x3F) << ESR_ELx_EC_SHIFT)
 73#define ESR_ELx_EC(esr)		(((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
 74
 75#define ESR_ELx_IL_SHIFT	(25)
 76#define ESR_ELx_IL		(UL(1) << ESR_ELx_IL_SHIFT)
 77#define ESR_ELx_ISS_MASK	(GENMASK(24, 0))
 78#define ESR_ELx_ISS(esr)	((esr) & ESR_ELx_ISS_MASK)
 79#define ESR_ELx_ISS2_SHIFT	(32)
 80#define ESR_ELx_ISS2_MASK	(GENMASK_ULL(55, 32))
 81#define ESR_ELx_ISS2(esr)	(((esr) & ESR_ELx_ISS2_MASK) >> ESR_ELx_ISS2_SHIFT)
 82
 83/* ISS field definitions shared by different classes */
 84#define ESR_ELx_WNR_SHIFT	(6)
 85#define ESR_ELx_WNR		(UL(1) << ESR_ELx_WNR_SHIFT)
 86
 87/* Asynchronous Error Type */
 88#define ESR_ELx_IDS_SHIFT	(24)
 89#define ESR_ELx_IDS		(UL(1) << ESR_ELx_IDS_SHIFT)
 90#define ESR_ELx_AET_SHIFT	(10)
 91#define ESR_ELx_AET		(UL(0x7) << ESR_ELx_AET_SHIFT)
 92
 93#define ESR_ELx_AET_UC		(UL(0) << ESR_ELx_AET_SHIFT)
 94#define ESR_ELx_AET_UEU		(UL(1) << ESR_ELx_AET_SHIFT)
 95#define ESR_ELx_AET_UEO		(UL(2) << ESR_ELx_AET_SHIFT)
 96#define ESR_ELx_AET_UER		(UL(3) << ESR_ELx_AET_SHIFT)
 97#define ESR_ELx_AET_CE		(UL(6) << ESR_ELx_AET_SHIFT)
 98
 99/* Shared ISS field definitions for Data/Instruction aborts */
100#define ESR_ELx_SET_SHIFT	(11)
101#define ESR_ELx_SET_MASK	(UL(3) << ESR_ELx_SET_SHIFT)
102#define ESR_ELx_FnV_SHIFT	(10)
103#define ESR_ELx_FnV		(UL(1) << ESR_ELx_FnV_SHIFT)
104#define ESR_ELx_EA_SHIFT	(9)
105#define ESR_ELx_EA		(UL(1) << ESR_ELx_EA_SHIFT)
106#define ESR_ELx_S1PTW_SHIFT	(7)
107#define ESR_ELx_S1PTW		(UL(1) << ESR_ELx_S1PTW_SHIFT)
108
109/* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */
110#define ESR_ELx_FSC		(0x3F)
111#define ESR_ELx_FSC_TYPE	(0x3C)
112#define ESR_ELx_FSC_LEVEL	(0x03)
113#define ESR_ELx_FSC_EXTABT	(0x10)
114#define ESR_ELx_FSC_MTE		(0x11)
115#define ESR_ELx_FSC_SERROR	(0x11)
116#define ESR_ELx_FSC_ACCESS	(0x08)
117#define ESR_ELx_FSC_FAULT	(0x04)
118#define ESR_ELx_FSC_PERM	(0x0C)
119#define ESR_ELx_FSC_SEA_TTW(n)	(0x14 + (n))
120#define ESR_ELx_FSC_SECC	(0x18)
121#define ESR_ELx_FSC_SECC_TTW(n)	(0x1c + (n))
122
123/* Status codes for individual page table levels */
124#define ESR_ELx_FSC_ACCESS_L(n)	(ESR_ELx_FSC_ACCESS + (n))
125#define ESR_ELx_FSC_PERM_L(n)	(ESR_ELx_FSC_PERM + (n))
126
127#define ESR_ELx_FSC_FAULT_nL	(0x2C)
128#define ESR_ELx_FSC_FAULT_L(n)	(((n) < 0 ? ESR_ELx_FSC_FAULT_nL : \
129					    ESR_ELx_FSC_FAULT) + (n))
130
131/* ISS field definitions for Data Aborts */
132#define ESR_ELx_ISV_SHIFT	(24)
133#define ESR_ELx_ISV		(UL(1) << ESR_ELx_ISV_SHIFT)
134#define ESR_ELx_SAS_SHIFT	(22)
135#define ESR_ELx_SAS		(UL(3) << ESR_ELx_SAS_SHIFT)
136#define ESR_ELx_SSE_SHIFT	(21)
137#define ESR_ELx_SSE		(UL(1) << ESR_ELx_SSE_SHIFT)
138#define ESR_ELx_SRT_SHIFT	(16)
139#define ESR_ELx_SRT_MASK	(UL(0x1F) << ESR_ELx_SRT_SHIFT)
140#define ESR_ELx_SF_SHIFT	(15)
141#define ESR_ELx_SF 		(UL(1) << ESR_ELx_SF_SHIFT)
142#define ESR_ELx_AR_SHIFT	(14)
143#define ESR_ELx_AR 		(UL(1) << ESR_ELx_AR_SHIFT)
144#define ESR_ELx_VNCR_SHIFT	(13)
145#define ESR_ELx_VNCR		(UL(1) << ESR_ELx_VNCR_SHIFT)
146#define ESR_ELx_CM_SHIFT	(8)
147#define ESR_ELx_CM 		(UL(1) << ESR_ELx_CM_SHIFT)
148
149/* ISS2 field definitions for Data Aborts */
150#define ESR_ELx_TnD_SHIFT	(10)
151#define ESR_ELx_TnD 		(UL(1) << ESR_ELx_TnD_SHIFT)
152#define ESR_ELx_TagAccess_SHIFT	(9)
153#define ESR_ELx_TagAccess	(UL(1) << ESR_ELx_TagAccess_SHIFT)
154#define ESR_ELx_GCS_SHIFT	(8)
155#define ESR_ELx_GCS 		(UL(1) << ESR_ELx_GCS_SHIFT)
156#define ESR_ELx_Overlay_SHIFT	(6)
157#define ESR_ELx_Overlay		(UL(1) << ESR_ELx_Overlay_SHIFT)
158#define ESR_ELx_DirtyBit_SHIFT	(5)
159#define ESR_ELx_DirtyBit	(UL(1) << ESR_ELx_DirtyBit_SHIFT)
160#define ESR_ELx_Xs_SHIFT	(0)
161#define ESR_ELx_Xs_MASK		(GENMASK_ULL(4, 0))
162
163/* ISS field definitions for exceptions taken in to Hyp */
164#define ESR_ELx_FSC_ADDRSZ	(0x00)
165#define ESR_ELx_FSC_ADDRSZ_L(n)	(ESR_ELx_FSC_ADDRSZ + (n))
166#define ESR_ELx_CV		(UL(1) << 24)
167#define ESR_ELx_COND_SHIFT	(20)
168#define ESR_ELx_COND_MASK	(UL(0xF) << ESR_ELx_COND_SHIFT)
169#define ESR_ELx_WFx_ISS_RN	(UL(0x1F) << 5)
170#define ESR_ELx_WFx_ISS_RV	(UL(1) << 2)
171#define ESR_ELx_WFx_ISS_TI	(UL(3) << 0)
172#define ESR_ELx_WFx_ISS_WFxT	(UL(2) << 0)
173#define ESR_ELx_WFx_ISS_WFI	(UL(0) << 0)
174#define ESR_ELx_WFx_ISS_WFE	(UL(1) << 0)
175#define ESR_ELx_xVC_IMM_MASK	((UL(1) << 16) - 1)
176
177#define DISR_EL1_IDS		(UL(1) << 24)
178/*
179 * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean
180 * different things in the future...
181 */
182#define DISR_EL1_ESR_MASK	(ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC)
183
184/* ESR value templates for specific events */
185#define ESR_ELx_WFx_MASK	(ESR_ELx_EC_MASK |			\
186				 (ESR_ELx_WFx_ISS_TI & ~ESR_ELx_WFx_ISS_WFxT))
187#define ESR_ELx_WFx_WFI_VAL	((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) |	\
188				 ESR_ELx_WFx_ISS_WFI)
189
190/* BRK instruction trap from AArch64 state */
191#define ESR_ELx_BRK64_ISS_COMMENT_MASK	0xffff
192
193/* ISS field definitions for System instruction traps */
194#define ESR_ELx_SYS64_ISS_RES0_SHIFT	22
195#define ESR_ELx_SYS64_ISS_RES0_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
196#define ESR_ELx_SYS64_ISS_DIR_MASK	0x1
197#define ESR_ELx_SYS64_ISS_DIR_READ	0x1
198#define ESR_ELx_SYS64_ISS_DIR_WRITE	0x0
199
200#define ESR_ELx_SYS64_ISS_RT_SHIFT	5
201#define ESR_ELx_SYS64_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
202#define ESR_ELx_SYS64_ISS_CRM_SHIFT	1
203#define ESR_ELx_SYS64_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
204#define ESR_ELx_SYS64_ISS_CRN_SHIFT	10
205#define ESR_ELx_SYS64_ISS_CRN_MASK	(UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
206#define ESR_ELx_SYS64_ISS_OP1_SHIFT	14
207#define ESR_ELx_SYS64_ISS_OP1_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
208#define ESR_ELx_SYS64_ISS_OP2_SHIFT	17
209#define ESR_ELx_SYS64_ISS_OP2_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
210#define ESR_ELx_SYS64_ISS_OP0_SHIFT	20
211#define ESR_ELx_SYS64_ISS_OP0_MASK	(UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
212#define ESR_ELx_SYS64_ISS_SYS_MASK	(ESR_ELx_SYS64_ISS_OP0_MASK | \
213					 ESR_ELx_SYS64_ISS_OP1_MASK | \
214					 ESR_ELx_SYS64_ISS_OP2_MASK | \
215					 ESR_ELx_SYS64_ISS_CRN_MASK | \
216					 ESR_ELx_SYS64_ISS_CRM_MASK)
217#define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \
218					(((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \
219					 ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \
220					 ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \
221					 ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \
222					 ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT))
223
224#define ESR_ELx_SYS64_ISS_SYS_OP_MASK	(ESR_ELx_SYS64_ISS_SYS_MASK | \
225					 ESR_ELx_SYS64_ISS_DIR_MASK)
226#define ESR_ELx_SYS64_ISS_RT(esr) \
227	(((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT)
228/*
229 * User space cache operations have the following sysreg encoding
230 * in System instructions.
231 * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0)
232 */
233#define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC	14
234#define ESR_ELx_SYS64_ISS_CRM_DC_CVADP	13
235#define ESR_ELx_SYS64_ISS_CRM_DC_CVAP	12
236#define ESR_ELx_SYS64_ISS_CRM_DC_CVAU	11
237#define ESR_ELx_SYS64_ISS_CRM_DC_CVAC	10
238#define ESR_ELx_SYS64_ISS_CRM_IC_IVAU	5
239
240#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK	(ESR_ELx_SYS64_ISS_OP0_MASK | \
241						 ESR_ELx_SYS64_ISS_OP1_MASK | \
242						 ESR_ELx_SYS64_ISS_OP2_MASK | \
243						 ESR_ELx_SYS64_ISS_CRN_MASK | \
244						 ESR_ELx_SYS64_ISS_DIR_MASK)
245#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \
246				(ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \
247				 ESR_ELx_SYS64_ISS_DIR_WRITE)
248/*
249 * User space MRS operations which are supported for emulation
250 * have the following sysreg encoding in System instructions.
251 * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1)
252 */
253#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK	(ESR_ELx_SYS64_ISS_OP0_MASK | \
254						 ESR_ELx_SYS64_ISS_OP1_MASK | \
255						 ESR_ELx_SYS64_ISS_CRN_MASK | \
256						 ESR_ELx_SYS64_ISS_DIR_MASK)
257#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \
258				(ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \
259				 ESR_ELx_SYS64_ISS_DIR_READ)
260
261#define ESR_ELx_SYS64_ISS_SYS_CTR	ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0)
262#define ESR_ELx_SYS64_ISS_SYS_CTR_READ	(ESR_ELx_SYS64_ISS_SYS_CTR | \
263					 ESR_ELx_SYS64_ISS_DIR_READ)
264
265#define ESR_ELx_SYS64_ISS_SYS_CNTVCT	(ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \
266					 ESR_ELx_SYS64_ISS_DIR_READ)
267
268#define ESR_ELx_SYS64_ISS_SYS_CNTVCTSS	(ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 6, 14, 0) | \
269					 ESR_ELx_SYS64_ISS_DIR_READ)
270
271#define ESR_ELx_SYS64_ISS_SYS_CNTFRQ	(ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \
272					 ESR_ELx_SYS64_ISS_DIR_READ)
273
274#define esr_sys64_to_sysreg(e)					\
275	sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >>		\
276		 ESR_ELx_SYS64_ISS_OP0_SHIFT),			\
277		(((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >>		\
278		 ESR_ELx_SYS64_ISS_OP1_SHIFT),			\
279		(((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >>		\
280		 ESR_ELx_SYS64_ISS_CRN_SHIFT),			\
281		(((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >>		\
282		 ESR_ELx_SYS64_ISS_CRM_SHIFT),			\
283		(((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >>		\
284		 ESR_ELx_SYS64_ISS_OP2_SHIFT))
285
286#define esr_cp15_to_sysreg(e)					\
287	sys_reg(3,						\
288		(((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >>		\
289		 ESR_ELx_SYS64_ISS_OP1_SHIFT),			\
290		(((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >>		\
291		 ESR_ELx_SYS64_ISS_CRN_SHIFT),			\
292		(((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >>		\
293		 ESR_ELx_SYS64_ISS_CRM_SHIFT),			\
294		(((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >>		\
295		 ESR_ELx_SYS64_ISS_OP2_SHIFT))
296
297/* ISS field definitions for ERET/ERETAA/ERETAB trapping */
298#define ESR_ELx_ERET_ISS_ERET		0x2
299#define ESR_ELx_ERET_ISS_ERETA		0x1
300
301/*
302 * ISS field definitions for floating-point exception traps
303 * (FP_EXC_32/FP_EXC_64).
304 *
305 * (The FPEXC_* constants are used instead for common bits.)
306 */
307
308#define ESR_ELx_FP_EXC_TFV	(UL(1) << 23)
309
310/*
311 * ISS field definitions for CP15 accesses
312 */
313#define ESR_ELx_CP15_32_ISS_DIR_MASK	0x1
314#define ESR_ELx_CP15_32_ISS_DIR_READ	0x1
315#define ESR_ELx_CP15_32_ISS_DIR_WRITE	0x0
316
317#define ESR_ELx_CP15_32_ISS_RT_SHIFT	5
318#define ESR_ELx_CP15_32_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
319#define ESR_ELx_CP15_32_ISS_CRM_SHIFT	1
320#define ESR_ELx_CP15_32_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
321#define ESR_ELx_CP15_32_ISS_CRN_SHIFT	10
322#define ESR_ELx_CP15_32_ISS_CRN_MASK	(UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
323#define ESR_ELx_CP15_32_ISS_OP1_SHIFT	14
324#define ESR_ELx_CP15_32_ISS_OP1_MASK	(UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
325#define ESR_ELx_CP15_32_ISS_OP2_SHIFT	17
326#define ESR_ELx_CP15_32_ISS_OP2_MASK	(UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
327
328#define ESR_ELx_CP15_32_ISS_SYS_MASK	(ESR_ELx_CP15_32_ISS_OP1_MASK | \
329					 ESR_ELx_CP15_32_ISS_OP2_MASK | \
330					 ESR_ELx_CP15_32_ISS_CRN_MASK | \
331					 ESR_ELx_CP15_32_ISS_CRM_MASK | \
332					 ESR_ELx_CP15_32_ISS_DIR_MASK)
333#define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \
334					(((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \
335					 ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \
336					 ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \
337					 ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT))
338
339#define ESR_ELx_CP15_64_ISS_DIR_MASK	0x1
340#define ESR_ELx_CP15_64_ISS_DIR_READ	0x1
341#define ESR_ELx_CP15_64_ISS_DIR_WRITE	0x0
342
343#define ESR_ELx_CP15_64_ISS_RT_SHIFT	5
344#define ESR_ELx_CP15_64_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
345
346#define ESR_ELx_CP15_64_ISS_RT2_SHIFT	10
347#define ESR_ELx_CP15_64_ISS_RT2_MASK	(UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
348
349#define ESR_ELx_CP15_64_ISS_OP1_SHIFT	16
350#define ESR_ELx_CP15_64_ISS_OP1_MASK	(UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
351#define ESR_ELx_CP15_64_ISS_CRM_SHIFT	1
352#define ESR_ELx_CP15_64_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
353
354#define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \
355					(((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \
356					 ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT))
357
358#define ESR_ELx_CP15_64_ISS_SYS_MASK	(ESR_ELx_CP15_64_ISS_OP1_MASK |	\
359					 ESR_ELx_CP15_64_ISS_CRM_MASK | \
360					 ESR_ELx_CP15_64_ISS_DIR_MASK)
361
362#define ESR_ELx_CP15_64_ISS_SYS_CNTVCT	(ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \
363					 ESR_ELx_CP15_64_ISS_DIR_READ)
364
365#define ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS (ESR_ELx_CP15_64_ISS_SYS_VAL(9, 14) | \
366					 ESR_ELx_CP15_64_ISS_DIR_READ)
367
368#define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ	(ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\
369					 ESR_ELx_CP15_32_ISS_DIR_READ)
370
371/*
372 * ISS values for SME traps
373 */
374
375#define ESR_ELx_SME_ISS_SME_DISABLED	0
376#define ESR_ELx_SME_ISS_ILL		1
377#define ESR_ELx_SME_ISS_SM_DISABLED	2
378#define ESR_ELx_SME_ISS_ZA_DISABLED	3
379#define ESR_ELx_SME_ISS_ZT_DISABLED	4
380
381/* ISS field definitions for MOPS exceptions */
382#define ESR_ELx_MOPS_ISS_MEM_INST	(UL(1) << 24)
383#define ESR_ELx_MOPS_ISS_FROM_EPILOGUE	(UL(1) << 18)
384#define ESR_ELx_MOPS_ISS_WRONG_OPTION	(UL(1) << 17)
385#define ESR_ELx_MOPS_ISS_OPTION_A	(UL(1) << 16)
386#define ESR_ELx_MOPS_ISS_DESTREG(esr)	(((esr) & (UL(0x1f) << 10)) >> 10)
387#define ESR_ELx_MOPS_ISS_SRCREG(esr)	(((esr) & (UL(0x1f) << 5)) >> 5)
388#define ESR_ELx_MOPS_ISS_SIZEREG(esr)	(((esr) & (UL(0x1f) << 0)) >> 0)
389
390#ifndef __ASSEMBLER__
391#include <asm/types.h>
392
393static inline unsigned long esr_brk_comment(unsigned long esr)
394{
395	return esr & ESR_ELx_BRK64_ISS_COMMENT_MASK;
396}
397
398static inline bool esr_is_data_abort(unsigned long esr)
399{
400	const unsigned long ec = ESR_ELx_EC(esr);
401
402	return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR;
403}
404
405static inline bool esr_is_cfi_brk(unsigned long esr)
406{
407	return ESR_ELx_EC(esr) == ESR_ELx_EC_BRK64 &&
408	       (esr_brk_comment(esr) & ~CFI_BRK_IMM_MASK) == CFI_BRK_IMM_BASE;
409}
410
411static inline bool esr_fsc_is_translation_fault(unsigned long esr)
412{
413	esr = esr & ESR_ELx_FSC;
414
415	return (esr == ESR_ELx_FSC_FAULT_L(3)) ||
416	       (esr == ESR_ELx_FSC_FAULT_L(2)) ||
417	       (esr == ESR_ELx_FSC_FAULT_L(1)) ||
418	       (esr == ESR_ELx_FSC_FAULT_L(0)) ||
419	       (esr == ESR_ELx_FSC_FAULT_L(-1));
420}
421
422static inline bool esr_fsc_is_permission_fault(unsigned long esr)
423{
424	esr = esr & ESR_ELx_FSC;
425
426	return (esr == ESR_ELx_FSC_PERM_L(3)) ||
427	       (esr == ESR_ELx_FSC_PERM_L(2)) ||
428	       (esr == ESR_ELx_FSC_PERM_L(1)) ||
429	       (esr == ESR_ELx_FSC_PERM_L(0));
430}
431
432static inline bool esr_fsc_is_access_flag_fault(unsigned long esr)
433{
434	esr = esr & ESR_ELx_FSC;
435
436	return (esr == ESR_ELx_FSC_ACCESS_L(3)) ||
437	       (esr == ESR_ELx_FSC_ACCESS_L(2)) ||
438	       (esr == ESR_ELx_FSC_ACCESS_L(1)) ||
439	       (esr == ESR_ELx_FSC_ACCESS_L(0));
440}
441
442/* Indicate whether ESR.EC==0x1A is for an ERETAx instruction */
443static inline bool esr_iss_is_eretax(unsigned long esr)
444{
445	return esr & ESR_ELx_ERET_ISS_ERET;
446}
447
448/* Indicate which key is used for ERETAx (false: A-Key, true: B-Key) */
449static inline bool esr_iss_is_eretab(unsigned long esr)
450{
451	return esr & ESR_ELx_ERET_ISS_ERETA;
452}
453
454const char *esr_get_class_string(unsigned long esr);
455#endif /* __ASSEMBLER__ */
456
457#endif /* __ASM_ESR_H */
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