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cputype.h
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linux-6.19.14/tools/arch/arm64/include/asm/cputype.h
1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (C) 2012 ARM Ltd. 4 */ 5#ifndef __ASM_CPUTYPE_H 6#define __ASM_CPUTYPE_H 7 8#define INVALID_HWID ULONG_MAX 9 10#define MPIDR_UP_BITMASK (0x1 << 30) 11#define MPIDR_MT_BITMASK (0x1 << 24) 12#define MPIDR_HWID_BITMASK UL(0xff00ffffff) 13 14#define MPIDR_LEVEL_BITS_SHIFT 3 15#define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT) 16#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) 17 18#define MPIDR_LEVEL_SHIFT(level) \ 19 (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT) 20 21#define MPIDR_AFFINITY_LEVEL(mpidr, level) \ 22 ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK) 23 24#define MIDR_REVISION_MASK 0xf 25#define MIDR_REVISION(midr) ((midr) & MIDR_REVISION_MASK) 26#define MIDR_PARTNUM_SHIFT 4 27#define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT) 28#define MIDR_PARTNUM(midr) \ 29 (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT) 30#define MIDR_ARCHITECTURE_SHIFT 16 31#define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT) 32#define MIDR_ARCHITECTURE(midr) \ 33 (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT) 34#define MIDR_VARIANT_SHIFT 20 35#define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT) 36#define MIDR_VARIANT(midr) \ 37 (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT) 38#define MIDR_IMPLEMENTOR_SHIFT 24 39#define MIDR_IMPLEMENTOR_MASK (0xffU << MIDR_IMPLEMENTOR_SHIFT) 40#define MIDR_IMPLEMENTOR(midr) \ 41 (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT) 42 43#define MIDR_CPU_MODEL(imp, partnum) \ 44 ((_AT(u32, imp) << MIDR_IMPLEMENTOR_SHIFT) | \ 45 (0xf << MIDR_ARCHITECTURE_SHIFT) | \ 46 ((partnum) << MIDR_PARTNUM_SHIFT)) 47 48#define MIDR_CPU_VAR_REV(var, rev) \ 49 (((var) << MIDR_VARIANT_SHIFT) | (rev)) 50 51#define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \ 52 MIDR_ARCHITECTURE_MASK) 53 54#define ARM_CPU_IMP_ARM 0x41 55#define ARM_CPU_IMP_APM 0x50 56#define ARM_CPU_IMP_CAVIUM 0x43 57#define ARM_CPU_IMP_BRCM 0x42 58#define ARM_CPU_IMP_QCOM 0x51 59#define ARM_CPU_IMP_NVIDIA 0x4E 60#define ARM_CPU_IMP_FUJITSU 0x46 61#define ARM_CPU_IMP_HISI 0x48 62#define ARM_CPU_IMP_APPLE 0x61 63#define ARM_CPU_IMP_AMPERE 0xC0 64#define ARM_CPU_IMP_MICROSOFT 0x6D 65 66#define ARM_CPU_PART_AEM_V8 0xD0F 67#define ARM_CPU_PART_FOUNDATION 0xD00 68#define ARM_CPU_PART_CORTEX_A57 0xD07 69#define ARM_CPU_PART_CORTEX_A72 0xD08 70#define ARM_CPU_PART_CORTEX_A53 0xD03 71#define ARM_CPU_PART_CORTEX_A73 0xD09 72#define ARM_CPU_PART_CORTEX_A75 0xD0A 73#define ARM_CPU_PART_CORTEX_A35 0xD04 74#define ARM_CPU_PART_CORTEX_A55 0xD05 75#define ARM_CPU_PART_CORTEX_A76 0xD0B 76#define ARM_CPU_PART_NEOVERSE_N1 0xD0C 77#define ARM_CPU_PART_CORTEX_A77 0xD0D 78#define ARM_CPU_PART_CORTEX_A76AE 0xD0E 79#define ARM_CPU_PART_NEOVERSE_V1 0xD40 80#define ARM_CPU_PART_CORTEX_A78 0xD41 81#define ARM_CPU_PART_CORTEX_A78AE 0xD42 82#define ARM_CPU_PART_CORTEX_X1 0xD44 83#define ARM_CPU_PART_CORTEX_A510 0xD46 84#define ARM_CPU_PART_CORTEX_A520 0xD80 85#define ARM_CPU_PART_CORTEX_A710 0xD47 86#define ARM_CPU_PART_CORTEX_A715 0xD4D 87#define ARM_CPU_PART_CORTEX_X2 0xD48 88#define ARM_CPU_PART_NEOVERSE_N2 0xD49 89#define ARM_CPU_PART_CORTEX_A78C 0xD4B 90#define ARM_CPU_PART_CORTEX_X1C 0xD4C 91#define ARM_CPU_PART_CORTEX_X3 0xD4E 92#define ARM_CPU_PART_NEOVERSE_V2 0xD4F 93#define ARM_CPU_PART_CORTEX_A720 0xD81 94#define ARM_CPU_PART_CORTEX_X4 0xD82 95#define ARM_CPU_PART_NEOVERSE_V3AE 0xD83 96#define ARM_CPU_PART_NEOVERSE_V3 0xD84 97#define ARM_CPU_PART_CORTEX_X925 0xD85 98#define ARM_CPU_PART_CORTEX_A725 0xD87 99#define ARM_CPU_PART_CORTEX_A720AE 0xD89 100#define ARM_CPU_PART_NEOVERSE_N3 0xD8E 101 102#define APM_CPU_PART_XGENE 0x000 103#define APM_CPU_VAR_POTENZA 0x00 104 105#define CAVIUM_CPU_PART_THUNDERX 0x0A1 106#define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2 107#define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3 108#define CAVIUM_CPU_PART_THUNDERX2 0x0AF 109/* OcteonTx2 series */ 110#define CAVIUM_CPU_PART_OCTX2_98XX 0x0B1 111#define CAVIUM_CPU_PART_OCTX2_96XX 0x0B2 112#define CAVIUM_CPU_PART_OCTX2_95XX 0x0B3 113#define CAVIUM_CPU_PART_OCTX2_95XXN 0x0B4 114#define CAVIUM_CPU_PART_OCTX2_95XXMM 0x0B5 115#define CAVIUM_CPU_PART_OCTX2_95XXO 0x0B6 116 117#define BRCM_CPU_PART_BRAHMA_B53 0x100 118#define BRCM_CPU_PART_VULCAN 0x516 119 120#define QCOM_CPU_PART_FALKOR_V1 0x800 121#define QCOM_CPU_PART_FALKOR 0xC00 122#define QCOM_CPU_PART_KRYO 0x200 123#define QCOM_CPU_PART_KRYO_2XX_GOLD 0x800 124#define QCOM_CPU_PART_KRYO_2XX_SILVER 0x801 125#define QCOM_CPU_PART_KRYO_3XX_GOLD 0x802 126#define QCOM_CPU_PART_KRYO_3XX_SILVER 0x803 127#define QCOM_CPU_PART_KRYO_4XX_GOLD 0x804 128#define QCOM_CPU_PART_KRYO_4XX_SILVER 0x805 129#define QCOM_CPU_PART_ORYON_X1 0x001 130 131#define NVIDIA_CPU_PART_DENVER 0x003 132#define NVIDIA_CPU_PART_CARMEL 0x004 133#define NVIDIA_CPU_PART_OLYMPUS 0x010 134 135#define FUJITSU_CPU_PART_A64FX 0x001 136 137#define HISI_CPU_PART_TSV110 0xD01 138#define HISI_CPU_PART_HIP09 0xD02 139#define HISI_CPU_PART_HIP12 0xD06 140 141#define APPLE_CPU_PART_M1_ICESTORM 0x022 142#define APPLE_CPU_PART_M1_FIRESTORM 0x023 143#define APPLE_CPU_PART_M1_ICESTORM_PRO 0x024 144#define APPLE_CPU_PART_M1_FIRESTORM_PRO 0x025 145#define APPLE_CPU_PART_M1_ICESTORM_MAX 0x028 146#define APPLE_CPU_PART_M1_FIRESTORM_MAX 0x029 147#define APPLE_CPU_PART_M2_BLIZZARD 0x032 148#define APPLE_CPU_PART_M2_AVALANCHE 0x033 149#define APPLE_CPU_PART_M2_BLIZZARD_PRO 0x034 150#define APPLE_CPU_PART_M2_AVALANCHE_PRO 0x035 151#define APPLE_CPU_PART_M2_BLIZZARD_MAX 0x038 152#define APPLE_CPU_PART_M2_AVALANCHE_MAX 0x039 153 154#define AMPERE_CPU_PART_AMPERE1 0xAC3 155#define AMPERE_CPU_PART_AMPERE1A 0xAC4 156 157#define MICROSOFT_CPU_PART_AZURE_COBALT_100 0xD49 /* Based on r0p0 of ARM Neoverse N2 */ 158 159#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) 160#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) 161#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) 162#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) 163#define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75) 164#define MIDR_CORTEX_A35 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A35) 165#define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55) 166#define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76) 167#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1) 168#define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77) 169#define MIDR_CORTEX_A76AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76AE) 170#define MIDR_NEOVERSE_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V1) 171#define MIDR_CORTEX_A78 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78) 172#define MIDR_CORTEX_A78AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78AE) 173#define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1) 174#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510) 175#define MIDR_CORTEX_A520 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520) 176#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) 177#define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A715) 178#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) 179#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) 180#define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) 181#define MIDR_CORTEX_X1C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1C) 182#define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3) 183#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) 184#define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720) 185#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) 186#define MIDR_NEOVERSE_V3AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3AE) 187#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3) 188#define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925) 189#define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725) 190#define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE) 191#define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3) 192#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) 193#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) 194#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) 195#define MIDR_OCTX2_98XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_98XX) 196#define MIDR_OCTX2_96XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_96XX) 197#define MIDR_OCTX2_95XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XX) 198#define MIDR_OCTX2_95XXN MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXN) 199#define MIDR_OCTX2_95XXMM MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXMM) 200#define MIDR_OCTX2_95XXO MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXO) 201#define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2) 202#define MIDR_BRAHMA_B53 MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_BRAHMA_B53) 203#define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN) 204#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1) 205#define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR) 206#define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO) 207#define MIDR_QCOM_KRYO_2XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_GOLD) 208#define MIDR_QCOM_KRYO_2XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_SILVER) 209#define MIDR_QCOM_KRYO_3XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_GOLD) 210#define MIDR_QCOM_KRYO_3XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_SILVER) 211#define MIDR_QCOM_KRYO_4XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_GOLD) 212#define MIDR_QCOM_KRYO_4XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_SILVER) 213#define MIDR_QCOM_ORYON_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_ORYON_X1) 214 215/* 216 * NOTES: 217 * - Qualcomm Kryo 5XX Prime / Gold ID themselves as MIDR_CORTEX_A77 218 * - Qualcomm Kryo 5XX Silver IDs itself as MIDR_QCOM_KRYO_4XX_SILVER 219 * - Qualcomm Kryo 6XX Prime IDs itself as MIDR_CORTEX_X1 220 * - Qualcomm Kryo 6XX Gold IDs itself as ARM_CPU_PART_CORTEX_A78 221 * - Qualcomm Kryo 6XX Silver IDs itself as MIDR_CORTEX_A55 222 */ 223 224#define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER) 225#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL) 226#define MIDR_NVIDIA_OLYMPUS MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_OLYMPUS) 227#define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX) 228#define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110) 229#define MIDR_HISI_HIP09 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP09) 230#define MIDR_HISI_HIP12 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP12) 231#define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM) 232#define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM) 233#define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO) 234#define MIDR_APPLE_M1_FIRESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_PRO) 235#define MIDR_APPLE_M1_ICESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_MAX) 236#define MIDR_APPLE_M1_FIRESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_MAX) 237#define MIDR_APPLE_M2_BLIZZARD MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD) 238#define MIDR_APPLE_M2_AVALANCHE MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE) 239#define MIDR_APPLE_M2_BLIZZARD_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_PRO) 240#define MIDR_APPLE_M2_AVALANCHE_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_PRO) 241#define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX) 242#define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX) 243#define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1) 244#define MIDR_AMPERE1A MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1A) 245#define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_AZURE_COBALT_100) 246 247/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */ 248#define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX 249#define MIDR_FUJITSU_ERRATUM_010001_MASK (~MIDR_CPU_VAR_REV(1, 0)) 250#define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_EL1_NFD1 | TCR_EL1_NFD0) 251 252#ifndef __ASSEMBLER__ 253 254#include <asm/sysreg.h> 255 256#define read_cpuid(reg) read_sysreg_s(SYS_ ## reg) 257 258/* 259 * Represent a range of MIDR values for a given CPU model and a 260 * range of variant/revision values. 261 * 262 * @model - CPU model as defined by MIDR_CPU_MODEL 263 * @rv_min - Minimum value for the revision/variant as defined by 264 * MIDR_CPU_VAR_REV 265 * @rv_max - Maximum value for the variant/revision for the range. 266 */ 267struct midr_range { 268 u32 model; 269 u32 rv_min; 270 u32 rv_max; 271}; 272 273#define MIDR_RANGE(m, v_min, r_min, v_max, r_max) \ 274 { \ 275 .model = m, \ 276 .rv_min = MIDR_CPU_VAR_REV(v_min, r_min), \ 277 .rv_max = MIDR_CPU_VAR_REV(v_max, r_max), \ 278 } 279 280#define MIDR_REV_RANGE(m, v, r_min, r_max) MIDR_RANGE(m, v, r_min, v, r_max) 281#define MIDR_REV(m, v, r) MIDR_RANGE(m, v, r, v, r) 282#define MIDR_ALL_VERSIONS(m) MIDR_RANGE(m, 0, 0, 0xf, 0xf) 283 284static inline bool midr_is_cpu_model_range(u32 midr, u32 model, u32 rv_min, 285 u32 rv_max) 286{ 287 u32 _model = midr & MIDR_CPU_MODEL_MASK; 288 u32 rv = midr & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK); 289 290 return _model == model && rv >= rv_min && rv <= rv_max; 291} 292 293static inline bool is_midr_in_range(u32 midr, struct midr_range const *range) 294{ 295 return midr_is_cpu_model_range(midr, range->model, 296 range->rv_min, range->rv_max); 297} 298 299static inline bool 300is_midr_in_range_list(u32 midr, struct midr_range const *ranges) 301{ 302 while (ranges->model) 303 if (is_midr_in_range(midr, ranges++)) 304 return true; 305 return false; 306} 307 308/* 309 * The CPU ID never changes at run time, so we might as well tell the 310 * compiler that it's constant. Use this function to read the CPU ID 311 * rather than directly reading processor_id or read_cpuid() directly. 312 */ 313static inline u32 __attribute_const__ read_cpuid_id(void) 314{ 315 return read_cpuid(MIDR_EL1); 316} 317 318struct target_impl_cpu { 319 u64 midr; 320 u64 revidr; 321 u64 aidr; 322}; 323 324bool cpu_errata_set_target_impl(u64 num, void *impl_cpus); 325 326static inline u64 __attribute_const__ read_cpuid_mpidr(void) 327{ 328 return read_cpuid(MPIDR_EL1); 329} 330 331static inline unsigned int __attribute_const__ read_cpuid_implementor(void) 332{ 333 return MIDR_IMPLEMENTOR(read_cpuid_id()); 334} 335 336static inline unsigned int __attribute_const__ read_cpuid_part_number(void) 337{ 338 return MIDR_PARTNUM(read_cpuid_id()); 339} 340 341static inline u32 __attribute_const__ read_cpuid_cachetype(void) 342{ 343 return read_cpuid(CTR_EL0); 344} 345#endif /* __ASSEMBLER__ */ 346 347#endif
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