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intel_hdmi_audio.c
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linux-6.19.14/sound/x86/intel_hdmi_audio.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * intel_hdmi_audio.c - Intel HDMI audio driver 4 * 5 * Copyright (C) 2016 Intel Corp 6 * Authors: Sailaja Bandarupalli <sailaja.bandarupalli@intel.com> 7 * Ramesh Babu K V <ramesh.babu@intel.com> 8 * Vaibhav Agarwal <vaibhav.agarwal@intel.com> 9 * Jerome Anand <jerome.anand@intel.com> 10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11 * 12 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 13 * ALSA driver for Intel HDMI audio 14 */ 15 16#include <linux/types.h> 17#include <linux/platform_device.h> 18#include <linux/io.h> 19#include <linux/slab.h> 20#include <linux/module.h> 21#include <linux/interrupt.h> 22#include <linux/pm_runtime.h> 23#include <linux/dma-mapping.h> 24#include <linux/delay.h> 25#include <linux/string.h> 26#include <sound/core.h> 27#include <sound/asoundef.h> 28#include <sound/pcm.h> 29#include <sound/pcm_params.h> 30#include <sound/initval.h> 31#include <sound/control.h> 32#include <sound/jack.h> 33#include <drm/drm_edid.h> 34#include <drm/drm_eld.h> 35#include <drm/intel/intel_lpe_audio.h> 36#include "intel_hdmi_audio.h" 37 38#define INTEL_HDMI_AUDIO_SUSPEND_DELAY_MS 5000 39 40#define for_each_pipe(card_ctx, pipe) \ 41 for ((pipe) = 0; (pipe) < (card_ctx)->num_pipes; (pipe)++) 42#define for_each_port(card_ctx, port) \ 43 for ((port) = 0; (port) < (card_ctx)->num_ports; (port)++) 44 45/*standard module options for ALSA. This module supports only one card*/ 46static int hdmi_card_index = SNDRV_DEFAULT_IDX1; 47static char *hdmi_card_id = SNDRV_DEFAULT_STR1; 48static bool single_port; 49 50module_param_named(index, hdmi_card_index, int, 0444); 51MODULE_PARM_DESC(index, 52 "Index value for INTEL Intel HDMI Audio controller."); 53module_param_named(id, hdmi_card_id, charp, 0444); 54MODULE_PARM_DESC(id, 55 "ID string for INTEL Intel HDMI Audio controller."); 56module_param(single_port, bool, 0444); 57MODULE_PARM_DESC(single_port, 58 "Single-port mode (for compatibility)"); 59 60/* 61 * ELD SA bits in the CEA Speaker Allocation data block 62 */ 63static const int eld_speaker_allocation_bits[] = { 64 [0] = FL | FR, 65 [1] = LFE, 66 [2] = FC, 67 [3] = RL | RR, 68 [4] = RC, 69 [5] = FLC | FRC, 70 [6] = RLC | RRC, 71 /* the following are not defined in ELD yet */ 72 [7] = 0, 73}; 74 75/* 76 * This is an ordered list! 77 * 78 * The preceding ones have better chances to be selected by 79 * hdmi_channel_allocation(). 80 */ 81static struct cea_channel_speaker_allocation channel_allocations[] = { 82/* channel: 7 6 5 4 3 2 1 0 */ 83{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } }, 84 /* 2.1 */ 85{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } }, 86 /* Dolby Surround */ 87{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } }, 88 /* surround40 */ 89{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } }, 90 /* surround41 */ 91{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } }, 92 /* surround50 */ 93{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } }, 94 /* surround51 */ 95{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } }, 96 /* 6.1 */ 97{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } }, 98 /* surround71 */ 99{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } }, 100 101{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } }, 102{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } }, 103{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } }, 104{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } }, 105{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } }, 106{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } }, 107{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } }, 108{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } }, 109{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } }, 110{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } }, 111{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } }, 112{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } }, 113{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } }, 114{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } }, 115{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } }, 116{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } }, 117{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } }, 118{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } }, 119{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } }, 120{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } }, 121{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } }, 122{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } }, 123{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } }, 124}; 125 126static const struct channel_map_table map_tables[] = { 127 { SNDRV_CHMAP_FL, 0x00, FL }, 128 { SNDRV_CHMAP_FR, 0x01, FR }, 129 { SNDRV_CHMAP_RL, 0x04, RL }, 130 { SNDRV_CHMAP_RR, 0x05, RR }, 131 { SNDRV_CHMAP_LFE, 0x02, LFE }, 132 { SNDRV_CHMAP_FC, 0x03, FC }, 133 { SNDRV_CHMAP_RLC, 0x06, RLC }, 134 { SNDRV_CHMAP_RRC, 0x07, RRC }, 135 {} /* terminator */ 136}; 137 138/* hardware capability structure */ 139static const struct snd_pcm_hardware had_pcm_hardware = { 140 .info = (SNDRV_PCM_INFO_INTERLEAVED | 141 SNDRV_PCM_INFO_MMAP | 142 SNDRV_PCM_INFO_MMAP_VALID | 143 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP), 144 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 145 SNDRV_PCM_FMTBIT_S24_LE | 146 SNDRV_PCM_FMTBIT_S32_LE), 147 .rates = SNDRV_PCM_RATE_32000 | 148 SNDRV_PCM_RATE_44100 | 149 SNDRV_PCM_RATE_48000 | 150 SNDRV_PCM_RATE_88200 | 151 SNDRV_PCM_RATE_96000 | 152 SNDRV_PCM_RATE_176400 | 153 SNDRV_PCM_RATE_192000, 154 .rate_min = HAD_MIN_RATE, 155 .rate_max = HAD_MAX_RATE, 156 .channels_min = HAD_MIN_CHANNEL, 157 .channels_max = HAD_MAX_CHANNEL, 158 .buffer_bytes_max = HAD_MAX_BUFFER, 159 .period_bytes_min = HAD_MIN_PERIOD_BYTES, 160 .period_bytes_max = HAD_MAX_PERIOD_BYTES, 161 .periods_min = HAD_MIN_PERIODS, 162 .periods_max = HAD_MAX_PERIODS, 163 .fifo_size = HAD_FIFO_SIZE, 164}; 165 166/* Get the active PCM substream; 167 * Call had_substream_put() for unreferecing. 168 * Don't call this inside had_spinlock, as it takes by itself 169 */ 170static struct snd_pcm_substream * 171had_substream_get(struct snd_intelhad *intelhaddata) 172{ 173 struct snd_pcm_substream *substream; 174 175 guard(spinlock_irqsave)(&intelhaddata->had_spinlock); 176 substream = intelhaddata->stream_info.substream; 177 if (substream) 178 intelhaddata->stream_info.substream_refcount++; 179 return substream; 180} 181 182/* Unref the active PCM substream; 183 * Don't call this inside had_spinlock, as it takes by itself 184 */ 185static void had_substream_put(struct snd_intelhad *intelhaddata) 186{ 187 guard(spinlock_irqsave)(&intelhaddata->had_spinlock); 188 intelhaddata->stream_info.substream_refcount--; 189} 190 191static u32 had_config_offset(int pipe) 192{ 193 switch (pipe) { 194 default: 195 case 0: 196 return AUDIO_HDMI_CONFIG_A; 197 case 1: 198 return AUDIO_HDMI_CONFIG_B; 199 case 2: 200 return AUDIO_HDMI_CONFIG_C; 201 } 202} 203 204/* Register access functions */ 205static u32 had_read_register_raw(struct snd_intelhad_card *card_ctx, 206 int pipe, u32 reg) 207{ 208 return ioread32(card_ctx->mmio_start + had_config_offset(pipe) + reg); 209} 210 211static void had_write_register_raw(struct snd_intelhad_card *card_ctx, 212 int pipe, u32 reg, u32 val) 213{ 214 iowrite32(val, card_ctx->mmio_start + had_config_offset(pipe) + reg); 215} 216 217static void had_read_register(struct snd_intelhad *ctx, u32 reg, u32 *val) 218{ 219 if (!ctx->connected) 220 *val = 0; 221 else 222 *val = had_read_register_raw(ctx->card_ctx, ctx->pipe, reg); 223} 224 225static void had_write_register(struct snd_intelhad *ctx, u32 reg, u32 val) 226{ 227 if (ctx->connected) 228 had_write_register_raw(ctx->card_ctx, ctx->pipe, reg, val); 229} 230 231/* 232 * enable / disable audio configuration 233 * 234 * The normal read/modify should not directly be used on VLV2 for 235 * updating AUD_CONFIG register. 236 * This is because: 237 * Bit6 of AUD_CONFIG register is writeonly due to a silicon bug on VLV2 238 * HDMI IP. As a result a read-modify of AUD_CONFIG register will always 239 * clear bit6. AUD_CONFIG[6:4] represents the "channels" field of the 240 * register. This field should be 1xy binary for configuration with 6 or 241 * more channels. Read-modify of AUD_CONFIG (Eg. for enabling audio) 242 * causes the "channels" field to be updated as 0xy binary resulting in 243 * bad audio. The fix is to always write the AUD_CONFIG[6:4] with 244 * appropriate value when doing read-modify of AUD_CONFIG register. 245 */ 246static void had_enable_audio(struct snd_intelhad *intelhaddata, 247 bool enable) 248{ 249 /* update the cached value */ 250 intelhaddata->aud_config.regx.aud_en = enable; 251 had_write_register(intelhaddata, AUD_CONFIG, 252 intelhaddata->aud_config.regval); 253} 254 255/* forcibly ACKs to both BUFFER_DONE and BUFFER_UNDERRUN interrupts */ 256static void had_ack_irqs(struct snd_intelhad *ctx) 257{ 258 u32 status_reg; 259 260 if (!ctx->connected) 261 return; 262 had_read_register(ctx, AUD_HDMI_STATUS, &status_reg); 263 status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN; 264 had_write_register(ctx, AUD_HDMI_STATUS, status_reg); 265 had_read_register(ctx, AUD_HDMI_STATUS, &status_reg); 266} 267 268/* Reset buffer pointers */ 269static void had_reset_audio(struct snd_intelhad *intelhaddata) 270{ 271 had_write_register(intelhaddata, AUD_HDMI_STATUS, 272 AUD_HDMI_STATUSG_MASK_FUNCRST); 273 had_write_register(intelhaddata, AUD_HDMI_STATUS, 0); 274} 275 276/* 277 * initialize audio channel status registers 278 * This function is called in the prepare callback 279 */ 280static int had_prog_status_reg(struct snd_pcm_substream *substream, 281 struct snd_intelhad *intelhaddata) 282{ 283 union aud_ch_status_0 ch_stat0 = {.regval = 0}; 284 union aud_ch_status_1 ch_stat1 = {.regval = 0}; 285 286 ch_stat0.regx.lpcm_id = (intelhaddata->aes_bits & 287 IEC958_AES0_NONAUDIO) >> 1; 288 ch_stat0.regx.clk_acc = (intelhaddata->aes_bits & 289 IEC958_AES3_CON_CLOCK) >> 4; 290 291 switch (substream->runtime->rate) { 292 case AUD_SAMPLE_RATE_32: 293 ch_stat0.regx.samp_freq = CH_STATUS_MAP_32KHZ; 294 break; 295 296 case AUD_SAMPLE_RATE_44_1: 297 ch_stat0.regx.samp_freq = CH_STATUS_MAP_44KHZ; 298 break; 299 case AUD_SAMPLE_RATE_48: 300 ch_stat0.regx.samp_freq = CH_STATUS_MAP_48KHZ; 301 break; 302 case AUD_SAMPLE_RATE_88_2: 303 ch_stat0.regx.samp_freq = CH_STATUS_MAP_88KHZ; 304 break; 305 case AUD_SAMPLE_RATE_96: 306 ch_stat0.regx.samp_freq = CH_STATUS_MAP_96KHZ; 307 break; 308 case AUD_SAMPLE_RATE_176_4: 309 ch_stat0.regx.samp_freq = CH_STATUS_MAP_176KHZ; 310 break; 311 case AUD_SAMPLE_RATE_192: 312 ch_stat0.regx.samp_freq = CH_STATUS_MAP_192KHZ; 313 break; 314 315 default: 316 /* control should never come here */ 317 return -EINVAL; 318 } 319 320 had_write_register(intelhaddata, 321 AUD_CH_STATUS_0, ch_stat0.regval); 322 323 switch (substream->runtime->format) { 324 case SNDRV_PCM_FORMAT_S16_LE: 325 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_20; 326 ch_stat1.regx.wrd_len = SMPL_WIDTH_16BITS; 327 break; 328 case SNDRV_PCM_FORMAT_S24_LE: 329 case SNDRV_PCM_FORMAT_S32_LE: 330 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_24; 331 ch_stat1.regx.wrd_len = SMPL_WIDTH_24BITS; 332 break; 333 default: 334 return -EINVAL; 335 } 336 337 had_write_register(intelhaddata, 338 AUD_CH_STATUS_1, ch_stat1.regval); 339 return 0; 340} 341 342/* 343 * function to initialize audio 344 * registers and buffer configuration registers 345 * This function is called in the prepare callback 346 */ 347static int had_init_audio_ctrl(struct snd_pcm_substream *substream, 348 struct snd_intelhad *intelhaddata) 349{ 350 union aud_cfg cfg_val = {.regval = 0}; 351 union aud_buf_config buf_cfg = {.regval = 0}; 352 u8 channels; 353 354 had_prog_status_reg(substream, intelhaddata); 355 356 buf_cfg.regx.audio_fifo_watermark = FIFO_THRESHOLD; 357 buf_cfg.regx.dma_fifo_watermark = DMA_FIFO_THRESHOLD; 358 buf_cfg.regx.aud_delay = 0; 359 had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.regval); 360 361 channels = substream->runtime->channels; 362 cfg_val.regx.num_ch = channels - 2; 363 if (channels <= 2) 364 cfg_val.regx.layout = LAYOUT0; 365 else 366 cfg_val.regx.layout = LAYOUT1; 367 368 if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE) 369 cfg_val.regx.packet_mode = 1; 370 371 if (substream->runtime->format == SNDRV_PCM_FORMAT_S32_LE) 372 cfg_val.regx.left_align = 1; 373 374 cfg_val.regx.val_bit = 1; 375 376 /* fix up the DP bits */ 377 if (intelhaddata->dp_output) { 378 cfg_val.regx.dp_modei = 1; 379 cfg_val.regx.set = 1; 380 } 381 382 had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval); 383 intelhaddata->aud_config = cfg_val; 384 return 0; 385} 386 387/* 388 * Compute derived values in channel_allocations[]. 389 */ 390static void init_channel_allocations(void) 391{ 392 int i, j; 393 struct cea_channel_speaker_allocation *p; 394 395 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 396 p = channel_allocations + i; 397 p->channels = 0; 398 p->spk_mask = 0; 399 for (j = 0; j < ARRAY_SIZE(p->speakers); j++) 400 if (p->speakers[j]) { 401 p->channels++; 402 p->spk_mask |= p->speakers[j]; 403 } 404 } 405} 406 407/* 408 * The transformation takes two steps: 409 * 410 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask 411 * spk_mask => (channel_allocations[]) => ai->CA 412 * 413 * TODO: it could select the wrong CA from multiple candidates. 414 */ 415static int had_channel_allocation(struct snd_intelhad *intelhaddata, 416 int channels) 417{ 418 int i; 419 int ca = 0; 420 int spk_mask = 0; 421 422 /* 423 * CA defaults to 0 for basic stereo audio 424 */ 425 if (channels <= 2) 426 return 0; 427 428 /* 429 * expand ELD's speaker allocation mask 430 * 431 * ELD tells the speaker mask in a compact(paired) form, 432 * expand ELD's notions to match the ones used by Audio InfoFrame. 433 */ 434 435 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) { 436 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i)) 437 spk_mask |= eld_speaker_allocation_bits[i]; 438 } 439 440 /* search for the first working match in the CA table */ 441 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 442 if (channels == channel_allocations[i].channels && 443 (spk_mask & channel_allocations[i].spk_mask) == 444 channel_allocations[i].spk_mask) { 445 ca = channel_allocations[i].ca_index; 446 break; 447 } 448 } 449 450 dev_dbg(intelhaddata->dev, "select CA 0x%x for %d\n", ca, channels); 451 452 return ca; 453} 454 455/* from speaker bit mask to ALSA API channel position */ 456static int spk_to_chmap(int spk) 457{ 458 const struct channel_map_table *t = map_tables; 459 460 for (; t->map; t++) { 461 if (t->spk_mask == spk) 462 return t->map; 463 } 464 return 0; 465} 466 467static void had_build_channel_allocation_map(struct snd_intelhad *intelhaddata) 468{ 469 int i, c; 470 int spk_mask = 0; 471 struct snd_pcm_chmap_elem *chmap; 472 u8 eld_high, eld_high_mask = 0xF0; 473 u8 high_msb; 474 475 kfree(intelhaddata->chmap->chmap); 476 intelhaddata->chmap->chmap = NULL; 477 478 chmap = kzalloc(sizeof(*chmap), GFP_KERNEL); 479 if (!chmap) 480 return; 481 482 dev_dbg(intelhaddata->dev, "eld speaker = %x\n", 483 intelhaddata->eld[DRM_ELD_SPEAKER]); 484 485 /* WA: Fix the max channel supported to 8 */ 486 487 /* 488 * Sink may support more than 8 channels, if eld_high has more than 489 * one bit set. SOC supports max 8 channels. 490 * Refer eld_speaker_allocation_bits, for sink speaker allocation 491 */ 492 493 /* if 0x2F < eld < 0x4F fall back to 0x2f, else fall back to 0x4F */ 494 eld_high = intelhaddata->eld[DRM_ELD_SPEAKER] & eld_high_mask; 495 if ((eld_high & (eld_high-1)) && (eld_high > 0x1F)) { 496 /* eld_high & (eld_high-1): if more than 1 bit set */ 497 /* 0x1F: 7 channels */ 498 for (i = 1; i < 4; i++) { 499 high_msb = eld_high & (0x80 >> i); 500 if (high_msb) { 501 intelhaddata->eld[DRM_ELD_SPEAKER] &= 502 high_msb | 0xF; 503 break; 504 } 505 } 506 } 507 508 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) { 509 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i)) 510 spk_mask |= eld_speaker_allocation_bits[i]; 511 } 512 513 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { 514 if (spk_mask == channel_allocations[i].spk_mask) { 515 for (c = 0; c < channel_allocations[i].channels; c++) { 516 chmap->map[c] = spk_to_chmap( 517 channel_allocations[i].speakers[ 518 (MAX_SPEAKERS - 1) - c]); 519 } 520 chmap->channels = channel_allocations[i].channels; 521 intelhaddata->chmap->chmap = chmap; 522 break; 523 } 524 } 525 if (i >= ARRAY_SIZE(channel_allocations)) 526 kfree(chmap); 527} 528 529/* 530 * ALSA API channel-map control callbacks 531 */ 532static int had_chmap_ctl_info(struct snd_kcontrol *kcontrol, 533 struct snd_ctl_elem_info *uinfo) 534{ 535 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 536 uinfo->count = HAD_MAX_CHANNEL; 537 uinfo->value.integer.min = 0; 538 uinfo->value.integer.max = SNDRV_CHMAP_LAST; 539 return 0; 540} 541 542static int had_chmap_ctl_get(struct snd_kcontrol *kcontrol, 543 struct snd_ctl_elem_value *ucontrol) 544{ 545 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol); 546 struct snd_intelhad *intelhaddata = info->private_data; 547 int i; 548 const struct snd_pcm_chmap_elem *chmap; 549 550 memset(ucontrol->value.integer.value, 0, 551 sizeof(long) * HAD_MAX_CHANNEL); 552 guard(mutex)(&intelhaddata->mutex); 553 if (!intelhaddata->chmap->chmap) 554 return 0; 555 556 chmap = intelhaddata->chmap->chmap; 557 for (i = 0; i < chmap->channels; i++) 558 ucontrol->value.integer.value[i] = chmap->map[i]; 559 560 return 0; 561} 562 563static int had_register_chmap_ctls(struct snd_intelhad *intelhaddata, 564 struct snd_pcm *pcm) 565{ 566 int err; 567 568 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, 569 NULL, 0, (unsigned long)intelhaddata, 570 &intelhaddata->chmap); 571 if (err < 0) 572 return err; 573 574 intelhaddata->chmap->private_data = intelhaddata; 575 intelhaddata->chmap->kctl->info = had_chmap_ctl_info; 576 intelhaddata->chmap->kctl->get = had_chmap_ctl_get; 577 intelhaddata->chmap->chmap = NULL; 578 return 0; 579} 580 581/* 582 * Initialize Data Island Packets registers 583 * This function is called in the prepare callback 584 */ 585static void had_prog_dip(struct snd_pcm_substream *substream, 586 struct snd_intelhad *intelhaddata) 587{ 588 int i; 589 union aud_ctrl_st ctrl_state = {.regval = 0}; 590 union aud_info_frame2 frame2 = {.regval = 0}; 591 union aud_info_frame3 frame3 = {.regval = 0}; 592 u8 checksum = 0; 593 u32 info_frame; 594 int channels; 595 int ca; 596 597 channels = substream->runtime->channels; 598 599 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval); 600 601 ca = had_channel_allocation(intelhaddata, channels); 602 if (intelhaddata->dp_output) { 603 info_frame = DP_INFO_FRAME_WORD1; 604 frame2.regval = (substream->runtime->channels - 1) | (ca << 24); 605 } else { 606 info_frame = HDMI_INFO_FRAME_WORD1; 607 frame2.regx.chnl_cnt = substream->runtime->channels - 1; 608 frame3.regx.chnl_alloc = ca; 609 610 /* Calculte the byte wide checksum for all valid DIP words */ 611 for (i = 0; i < BYTES_PER_WORD; i++) 612 checksum += (info_frame >> (i * 8)) & 0xff; 613 for (i = 0; i < BYTES_PER_WORD; i++) 614 checksum += (frame2.regval >> (i * 8)) & 0xff; 615 for (i = 0; i < BYTES_PER_WORD; i++) 616 checksum += (frame3.regval >> (i * 8)) & 0xff; 617 618 frame2.regx.chksum = -(checksum); 619 } 620 621 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, info_frame); 622 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame2.regval); 623 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame3.regval); 624 625 /* program remaining DIP words with zero */ 626 for (i = 0; i < HAD_MAX_DIP_WORDS-VALID_DIP_WORDS; i++) 627 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, 0x0); 628 629 ctrl_state.regx.dip_freq = 1; 630 ctrl_state.regx.dip_en_sta = 1; 631 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval); 632} 633 634static int had_calculate_maud_value(u32 aud_samp_freq, u32 link_rate) 635{ 636 u32 maud_val; 637 638 /* Select maud according to DP 1.2 spec */ 639 if (link_rate == DP_2_7_GHZ) { 640 switch (aud_samp_freq) { 641 case AUD_SAMPLE_RATE_32: 642 maud_val = AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL; 643 break; 644 645 case AUD_SAMPLE_RATE_44_1: 646 maud_val = AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL; 647 break; 648 649 case AUD_SAMPLE_RATE_48: 650 maud_val = AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL; 651 break; 652 653 case AUD_SAMPLE_RATE_88_2: 654 maud_val = AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL; 655 break; 656 657 case AUD_SAMPLE_RATE_96: 658 maud_val = AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL; 659 break; 660 661 case AUD_SAMPLE_RATE_176_4: 662 maud_val = AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL; 663 break; 664 665 case HAD_MAX_RATE: 666 maud_val = HAD_MAX_RATE_DP_2_7_MAUD_VAL; 667 break; 668 669 default: 670 maud_val = -EINVAL; 671 break; 672 } 673 } else if (link_rate == DP_1_62_GHZ) { 674 switch (aud_samp_freq) { 675 case AUD_SAMPLE_RATE_32: 676 maud_val = AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL; 677 break; 678 679 case AUD_SAMPLE_RATE_44_1: 680 maud_val = AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL; 681 break; 682 683 case AUD_SAMPLE_RATE_48: 684 maud_val = AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL; 685 break; 686 687 case AUD_SAMPLE_RATE_88_2: 688 maud_val = AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL; 689 break; 690 691 case AUD_SAMPLE_RATE_96: 692 maud_val = AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL; 693 break; 694 695 case AUD_SAMPLE_RATE_176_4: 696 maud_val = AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL; 697 break; 698 699 case HAD_MAX_RATE: 700 maud_val = HAD_MAX_RATE_DP_1_62_MAUD_VAL; 701 break; 702 703 default: 704 maud_val = -EINVAL; 705 break; 706 } 707 } else 708 maud_val = -EINVAL; 709 710 return maud_val; 711} 712 713/* 714 * Program HDMI audio CTS value 715 * 716 * @aud_samp_freq: sampling frequency of audio data 717 * @tmds: sampling frequency of the display data 718 * @link_rate: DP link rate 719 * @n_param: N value, depends on aud_samp_freq 720 * @intelhaddata: substream private data 721 * 722 * Program CTS register based on the audio and display sampling frequency 723 */ 724static void had_prog_cts(u32 aud_samp_freq, u32 tmds, u32 link_rate, 725 u32 n_param, struct snd_intelhad *intelhaddata) 726{ 727 u32 cts_val; 728 u64 dividend, divisor; 729 730 if (intelhaddata->dp_output) { 731 /* Substitute cts_val with Maud according to DP 1.2 spec*/ 732 cts_val = had_calculate_maud_value(aud_samp_freq, link_rate); 733 } else { 734 /* Calculate CTS according to HDMI 1.3a spec*/ 735 dividend = (u64)tmds * n_param*1000; 736 divisor = 128 * aud_samp_freq; 737 cts_val = div64_u64(dividend, divisor); 738 } 739 dev_dbg(intelhaddata->dev, "TMDS value=%d, N value=%d, CTS Value=%d\n", 740 tmds, n_param, cts_val); 741 had_write_register(intelhaddata, AUD_HDMI_CTS, (BIT(24) | cts_val)); 742} 743 744static int had_calculate_n_value(u32 aud_samp_freq) 745{ 746 int n_val; 747 748 /* Select N according to HDMI 1.3a spec*/ 749 switch (aud_samp_freq) { 750 case AUD_SAMPLE_RATE_32: 751 n_val = 4096; 752 break; 753 754 case AUD_SAMPLE_RATE_44_1: 755 n_val = 6272; 756 break; 757 758 case AUD_SAMPLE_RATE_48: 759 n_val = 6144; 760 break; 761 762 case AUD_SAMPLE_RATE_88_2: 763 n_val = 12544; 764 break; 765 766 case AUD_SAMPLE_RATE_96: 767 n_val = 12288; 768 break; 769 770 case AUD_SAMPLE_RATE_176_4: 771 n_val = 25088; 772 break; 773 774 case HAD_MAX_RATE: 775 n_val = 24576; 776 break; 777 778 default: 779 n_val = -EINVAL; 780 break; 781 } 782 return n_val; 783} 784 785/* 786 * Program HDMI audio N value 787 * 788 * @aud_samp_freq: sampling frequency of audio data 789 * @n_param: N value, depends on aud_samp_freq 790 * @intelhaddata: substream private data 791 * 792 * This function is called in the prepare callback. 793 * It programs based on the audio and display sampling frequency 794 */ 795static int had_prog_n(u32 aud_samp_freq, u32 *n_param, 796 struct snd_intelhad *intelhaddata) 797{ 798 int n_val; 799 800 if (intelhaddata->dp_output) { 801 /* 802 * According to DP specs, Maud and Naud values hold 803 * a relationship, which is stated as: 804 * Maud/Naud = 512 * fs / f_LS_Clk 805 * where, fs is the sampling frequency of the audio stream 806 * and Naud is 32768 for Async clock. 807 */ 808 809 n_val = DP_NAUD_VAL; 810 } else 811 n_val = had_calculate_n_value(aud_samp_freq); 812 813 if (n_val < 0) 814 return n_val; 815 816 had_write_register(intelhaddata, AUD_N_ENABLE, (BIT(24) | n_val)); 817 *n_param = n_val; 818 return 0; 819} 820 821/* 822 * PCM ring buffer handling 823 * 824 * The hardware provides a ring buffer with the fixed 4 buffer descriptors 825 * (BDs). The driver maps these 4 BDs onto the PCM ring buffer. The mapping 826 * moves at each period elapsed. The below illustrates how it works: 827 * 828 * At time=0 829 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| 830 * BD | 0 | 1 | 2 | 3 | 831 * 832 * At time=1 (period elapsed) 833 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| 834 * BD | 1 | 2 | 3 | 0 | 835 * 836 * At time=2 (second period elapsed) 837 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| 838 * BD | 2 | 3 | 0 | 1 | 839 * 840 * The bd_head field points to the index of the BD to be read. It's also the 841 * position to be filled at next. The pcm_head and the pcm_filled fields 842 * point to the indices of the current position and of the next position to 843 * be filled, respectively. For PCM buffer there are both _head and _filled 844 * because they may be difference when nperiods > 4. For example, in the 845 * example above at t=1, bd_head=1 and pcm_head=1 while pcm_filled=5: 846 * 847 * pcm_head (=1) --v v-- pcm_filled (=5) 848 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| 849 * BD | 1 | 2 | 3 | 0 | 850 * bd_head (=1) --^ ^-- next to fill (= bd_head) 851 * 852 * For nperiods < 4, the remaining BDs out of 4 are marked as invalid, so that 853 * the hardware skips those BDs in the loop. 854 * 855 * An exceptional setup is the case with nperiods=1. Since we have to update 856 * BDs after finishing one BD processing, we'd need at least two BDs, where 857 * both BDs point to the same content, the same address, the same size of the 858 * whole PCM buffer. 859 */ 860 861#define AUD_BUF_ADDR(x) (AUD_BUF_A_ADDR + (x) * HAD_REG_WIDTH) 862#define AUD_BUF_LEN(x) (AUD_BUF_A_LENGTH + (x) * HAD_REG_WIDTH) 863 864/* Set up a buffer descriptor at the "filled" position */ 865static void had_prog_bd(struct snd_pcm_substream *substream, 866 struct snd_intelhad *intelhaddata) 867{ 868 int idx = intelhaddata->bd_head; 869 int ofs = intelhaddata->pcmbuf_filled * intelhaddata->period_bytes; 870 u32 addr = substream->runtime->dma_addr + ofs; 871 872 addr |= AUD_BUF_VALID; 873 if (!substream->runtime->no_period_wakeup) 874 addr |= AUD_BUF_INTR_EN; 875 had_write_register(intelhaddata, AUD_BUF_ADDR(idx), addr); 876 had_write_register(intelhaddata, AUD_BUF_LEN(idx), 877 intelhaddata->period_bytes); 878 879 /* advance the indices to the next */ 880 intelhaddata->bd_head++; 881 intelhaddata->bd_head %= intelhaddata->num_bds; 882 intelhaddata->pcmbuf_filled++; 883 intelhaddata->pcmbuf_filled %= substream->runtime->periods; 884} 885 886/* invalidate a buffer descriptor with the given index */ 887static void had_invalidate_bd(struct snd_intelhad *intelhaddata, 888 int idx) 889{ 890 had_write_register(intelhaddata, AUD_BUF_ADDR(idx), 0); 891 had_write_register(intelhaddata, AUD_BUF_LEN(idx), 0); 892} 893 894/* Initial programming of ring buffer */ 895static void had_init_ringbuf(struct snd_pcm_substream *substream, 896 struct snd_intelhad *intelhaddata) 897{ 898 struct snd_pcm_runtime *runtime = substream->runtime; 899 int i, num_periods; 900 901 num_periods = runtime->periods; 902 intelhaddata->num_bds = min(num_periods, HAD_NUM_OF_RING_BUFS); 903 /* set the minimum 2 BDs for num_periods=1 */ 904 intelhaddata->num_bds = max(intelhaddata->num_bds, 2U); 905 intelhaddata->period_bytes = 906 frames_to_bytes(runtime, runtime->period_size); 907 WARN_ON(intelhaddata->period_bytes & 0x3f); 908 909 intelhaddata->bd_head = 0; 910 intelhaddata->pcmbuf_head = 0; 911 intelhaddata->pcmbuf_filled = 0; 912 913 for (i = 0; i < HAD_NUM_OF_RING_BUFS; i++) { 914 if (i < intelhaddata->num_bds) 915 had_prog_bd(substream, intelhaddata); 916 else /* invalidate the rest */ 917 had_invalidate_bd(intelhaddata, i); 918 } 919 920 intelhaddata->bd_head = 0; /* reset at head again before starting */ 921} 922 923/* process a bd, advance to the next */ 924static void had_advance_ringbuf(struct snd_pcm_substream *substream, 925 struct snd_intelhad *intelhaddata) 926{ 927 int num_periods = substream->runtime->periods; 928 929 /* reprogram the next buffer */ 930 had_prog_bd(substream, intelhaddata); 931 932 /* proceed to next */ 933 intelhaddata->pcmbuf_head++; 934 intelhaddata->pcmbuf_head %= num_periods; 935} 936 937/* process the current BD(s); 938 * returns the current PCM buffer byte position, or -EPIPE for underrun. 939 */ 940static int had_process_ringbuf(struct snd_pcm_substream *substream, 941 struct snd_intelhad *intelhaddata) 942{ 943 int len, processed; 944 945 processed = 0; 946 guard(spinlock_irqsave)(&intelhaddata->had_spinlock); 947 for (;;) { 948 /* get the remaining bytes on the buffer */ 949 had_read_register(intelhaddata, 950 AUD_BUF_LEN(intelhaddata->bd_head), 951 &len); 952 if (len < 0 || len > intelhaddata->period_bytes) { 953 dev_dbg(intelhaddata->dev, "Invalid buf length %d\n", 954 len); 955 return -EPIPE; 956 } 957 958 if (len > 0) /* OK, this is the current buffer */ 959 break; 960 961 /* len=0 => already empty, check the next buffer */ 962 if (++processed >= intelhaddata->num_bds) 963 return -EPIPE; /* all empty? - report underrun */ 964 had_advance_ringbuf(substream, intelhaddata); 965 } 966 967 len = intelhaddata->period_bytes - len; 968 len += intelhaddata->period_bytes * intelhaddata->pcmbuf_head; 969 return len; 970} 971 972/* called from irq handler */ 973static void had_process_buffer_done(struct snd_intelhad *intelhaddata) 974{ 975 struct snd_pcm_substream *substream; 976 977 substream = had_substream_get(intelhaddata); 978 if (!substream) 979 return; /* no stream? - bail out */ 980 981 if (!intelhaddata->connected) { 982 snd_pcm_stop_xrun(substream); 983 goto out; /* disconnected? - bail out */ 984 } 985 986 /* process or stop the stream */ 987 if (had_process_ringbuf(substream, intelhaddata) < 0) 988 snd_pcm_stop_xrun(substream); 989 else 990 snd_pcm_period_elapsed(substream); 991 992 out: 993 had_substream_put(intelhaddata); 994} 995 996/* 997 * The interrupt status 'sticky' bits might not be cleared by 998 * setting '1' to that bit once... 999 */ 1000static void wait_clear_underrun_bit(struct snd_intelhad *intelhaddata) 1001{ 1002 int i; 1003 u32 val; 1004 1005 for (i = 0; i < 100; i++) { 1006 /* clear bit30, 31 AUD_HDMI_STATUS */ 1007 had_read_register(intelhaddata, AUD_HDMI_STATUS, &val); 1008 if (!(val & AUD_HDMI_STATUS_MASK_UNDERRUN)) 1009 return; 1010 udelay(100); 1011 cond_resched(); 1012 had_write_register(intelhaddata, AUD_HDMI_STATUS, val); 1013 } 1014 dev_err(intelhaddata->dev, "Unable to clear UNDERRUN bits\n"); 1015} 1016 1017/* Perform some reset procedure after stopping the stream; 1018 * this is called from prepare or hw_free callbacks once after trigger STOP 1019 * or underrun has been processed in order to settle down the h/w state. 1020 */ 1021static int had_pcm_sync_stop(struct snd_pcm_substream *substream) 1022{ 1023 struct snd_intelhad *intelhaddata = snd_pcm_substream_chip(substream); 1024 1025 if (!intelhaddata->connected) 1026 return 0; 1027 1028 /* Reset buffer pointers */ 1029 had_reset_audio(intelhaddata); 1030 wait_clear_underrun_bit(intelhaddata); 1031 return 0; 1032} 1033 1034/* called from irq handler */ 1035static void had_process_buffer_underrun(struct snd_intelhad *intelhaddata) 1036{ 1037 struct snd_pcm_substream *substream; 1038 1039 /* Report UNDERRUN error to above layers */ 1040 substream = had_substream_get(intelhaddata); 1041 if (substream) { 1042 snd_pcm_stop_xrun(substream); 1043 had_substream_put(intelhaddata); 1044 } 1045} 1046 1047/* 1048 * ALSA PCM open callback 1049 */ 1050static int had_pcm_open(struct snd_pcm_substream *substream) 1051{ 1052 struct snd_intelhad *intelhaddata; 1053 struct snd_pcm_runtime *runtime; 1054 int retval; 1055 1056 intelhaddata = snd_pcm_substream_chip(substream); 1057 runtime = substream->runtime; 1058 1059 retval = pm_runtime_resume_and_get(intelhaddata->dev); 1060 if (retval < 0) 1061 return retval; 1062 1063 /* set the runtime hw parameter with local snd_pcm_hardware struct */ 1064 runtime->hw = had_pcm_hardware; 1065 1066 retval = snd_pcm_hw_constraint_integer(runtime, 1067 SNDRV_PCM_HW_PARAM_PERIODS); 1068 if (retval < 0) 1069 goto error; 1070 1071 /* Make sure, that the period size is always aligned 1072 * 64byte boundary 1073 */ 1074 retval = snd_pcm_hw_constraint_step(substream->runtime, 0, 1075 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64); 1076 if (retval < 0) 1077 goto error; 1078 1079 retval = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 1080 if (retval < 0) 1081 goto error; 1082 1083 /* expose PCM substream */ 1084 scoped_guard(spinlock_irq, &intelhaddata->had_spinlock) { 1085 intelhaddata->stream_info.substream = substream; 1086 intelhaddata->stream_info.substream_refcount++; 1087 } 1088 1089 return retval; 1090 error: 1091 pm_runtime_put_autosuspend(intelhaddata->dev); 1092 return retval; 1093} 1094 1095/* 1096 * ALSA PCM close callback 1097 */ 1098static int had_pcm_close(struct snd_pcm_substream *substream) 1099{ 1100 struct snd_intelhad *intelhaddata; 1101 1102 intelhaddata = snd_pcm_substream_chip(substream); 1103 1104 /* unreference and sync with the pending PCM accesses */ 1105 spin_lock_irq(&intelhaddata->had_spinlock); 1106 intelhaddata->stream_info.substream = NULL; 1107 intelhaddata->stream_info.substream_refcount--; 1108 while (intelhaddata->stream_info.substream_refcount > 0) { 1109 spin_unlock_irq(&intelhaddata->had_spinlock); 1110 cpu_relax(); 1111 spin_lock_irq(&intelhaddata->had_spinlock); 1112 } 1113 spin_unlock_irq(&intelhaddata->had_spinlock); 1114 1115 pm_runtime_put_autosuspend(intelhaddata->dev); 1116 return 0; 1117} 1118 1119/* 1120 * ALSA PCM hw_params callback 1121 */ 1122static int had_pcm_hw_params(struct snd_pcm_substream *substream, 1123 struct snd_pcm_hw_params *hw_params) 1124{ 1125 struct snd_intelhad *intelhaddata; 1126 int buf_size; 1127 1128 intelhaddata = snd_pcm_substream_chip(substream); 1129 buf_size = params_buffer_bytes(hw_params); 1130 dev_dbg(intelhaddata->dev, "%s:allocated memory = %d\n", 1131 __func__, buf_size); 1132 return 0; 1133} 1134 1135/* 1136 * ALSA PCM trigger callback 1137 */ 1138static int had_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 1139{ 1140 int retval = 0; 1141 struct snd_intelhad *intelhaddata; 1142 1143 intelhaddata = snd_pcm_substream_chip(substream); 1144 1145 guard(spinlock)(&intelhaddata->had_spinlock); 1146 switch (cmd) { 1147 case SNDRV_PCM_TRIGGER_START: 1148 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1149 case SNDRV_PCM_TRIGGER_RESUME: 1150 /* Enable Audio */ 1151 had_ack_irqs(intelhaddata); /* FIXME: do we need this? */ 1152 had_enable_audio(intelhaddata, true); 1153 break; 1154 1155 case SNDRV_PCM_TRIGGER_STOP: 1156 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1157 /* Disable Audio */ 1158 had_enable_audio(intelhaddata, false); 1159 break; 1160 1161 default: 1162 retval = -EINVAL; 1163 } 1164 return retval; 1165} 1166 1167/* 1168 * ALSA PCM prepare callback 1169 */ 1170static int had_pcm_prepare(struct snd_pcm_substream *substream) 1171{ 1172 int retval; 1173 u32 disp_samp_freq, n_param; 1174 u32 link_rate = 0; 1175 struct snd_intelhad *intelhaddata; 1176 struct snd_pcm_runtime *runtime; 1177 1178 intelhaddata = snd_pcm_substream_chip(substream); 1179 runtime = substream->runtime; 1180 1181 dev_dbg(intelhaddata->dev, "period_size=%d\n", 1182 (int)frames_to_bytes(runtime, runtime->period_size)); 1183 dev_dbg(intelhaddata->dev, "periods=%d\n", runtime->periods); 1184 dev_dbg(intelhaddata->dev, "buffer_size=%d\n", 1185 (int)snd_pcm_lib_buffer_bytes(substream)); 1186 dev_dbg(intelhaddata->dev, "rate=%d\n", runtime->rate); 1187 dev_dbg(intelhaddata->dev, "channels=%d\n", runtime->channels); 1188 1189 /* Get N value in KHz */ 1190 disp_samp_freq = intelhaddata->tmds_clock_speed; 1191 1192 retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata); 1193 if (retval) { 1194 dev_err(intelhaddata->dev, 1195 "programming N value failed %#x\n", retval); 1196 goto prep_end; 1197 } 1198 1199 if (intelhaddata->dp_output) 1200 link_rate = intelhaddata->link_rate; 1201 1202 had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate, 1203 n_param, intelhaddata); 1204 1205 had_prog_dip(substream, intelhaddata); 1206 1207 retval = had_init_audio_ctrl(substream, intelhaddata); 1208 1209 /* Prog buffer address */ 1210 had_init_ringbuf(substream, intelhaddata); 1211 1212 /* 1213 * Program channel mapping in following order: 1214 * FL, FR, C, LFE, RL, RR 1215 */ 1216 1217 had_write_register(intelhaddata, AUD_BUF_CH_SWAP, SWAP_LFE_CENTER); 1218 1219prep_end: 1220 return retval; 1221} 1222 1223/* 1224 * ALSA PCM pointer callback 1225 */ 1226static snd_pcm_uframes_t had_pcm_pointer(struct snd_pcm_substream *substream) 1227{ 1228 struct snd_intelhad *intelhaddata; 1229 int len; 1230 1231 intelhaddata = snd_pcm_substream_chip(substream); 1232 1233 if (!intelhaddata->connected) 1234 return SNDRV_PCM_POS_XRUN; 1235 1236 len = had_process_ringbuf(substream, intelhaddata); 1237 if (len < 0) 1238 return SNDRV_PCM_POS_XRUN; 1239 len = bytes_to_frames(substream->runtime, len); 1240 /* wrapping may happen when periods=1 */ 1241 len %= substream->runtime->buffer_size; 1242 return len; 1243} 1244 1245/* 1246 * ALSA PCM ops 1247 */ 1248static const struct snd_pcm_ops had_pcm_ops = { 1249 .open = had_pcm_open, 1250 .close = had_pcm_close, 1251 .hw_params = had_pcm_hw_params, 1252 .prepare = had_pcm_prepare, 1253 .trigger = had_pcm_trigger, 1254 .sync_stop = had_pcm_sync_stop, 1255 .pointer = had_pcm_pointer, 1256}; 1257 1258/* process mode change of the running stream; called in mutex */ 1259static int had_process_mode_change(struct snd_intelhad *intelhaddata) 1260{ 1261 struct snd_pcm_substream *substream; 1262 int retval = 0; 1263 u32 disp_samp_freq, n_param; 1264 u32 link_rate = 0; 1265 1266 substream = had_substream_get(intelhaddata); 1267 if (!substream) 1268 return 0; 1269 1270 /* Disable Audio */ 1271 had_enable_audio(intelhaddata, false); 1272 1273 /* Update CTS value */ 1274 disp_samp_freq = intelhaddata->tmds_clock_speed; 1275 1276 retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata); 1277 if (retval) { 1278 dev_err(intelhaddata->dev, 1279 "programming N value failed %#x\n", retval); 1280 goto out; 1281 } 1282 1283 if (intelhaddata->dp_output) 1284 link_rate = intelhaddata->link_rate; 1285 1286 had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate, 1287 n_param, intelhaddata); 1288 1289 /* Enable Audio */ 1290 had_enable_audio(intelhaddata, true); 1291 1292out: 1293 had_substream_put(intelhaddata); 1294 return retval; 1295} 1296 1297/* process hot plug, called from wq with mutex locked */ 1298static void had_process_hot_plug(struct snd_intelhad *intelhaddata) 1299{ 1300 struct snd_pcm_substream *substream; 1301 1302 scoped_guard(spinlock_irq, &intelhaddata->had_spinlock) { 1303 if (intelhaddata->connected) { 1304 dev_dbg(intelhaddata->dev, "Device already connected\n"); 1305 return; 1306 } 1307 1308 /* Disable Audio */ 1309 had_enable_audio(intelhaddata, false); 1310 1311 intelhaddata->connected = true; 1312 dev_dbg(intelhaddata->dev, 1313 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n", 1314 __func__, __LINE__); 1315 } 1316 1317 had_build_channel_allocation_map(intelhaddata); 1318 1319 /* Report to above ALSA layer */ 1320 substream = had_substream_get(intelhaddata); 1321 if (substream) { 1322 snd_pcm_stop_xrun(substream); 1323 had_substream_put(intelhaddata); 1324 } 1325 1326 snd_jack_report(intelhaddata->jack, SND_JACK_AVOUT); 1327} 1328 1329/* process hot unplug, called from wq with mutex locked */ 1330static void had_process_hot_unplug(struct snd_intelhad *intelhaddata) 1331{ 1332 struct snd_pcm_substream *substream; 1333 1334 scoped_guard(spinlock_irq, &intelhaddata->had_spinlock) { 1335 if (!intelhaddata->connected) { 1336 dev_dbg(intelhaddata->dev, "Device already disconnected\n"); 1337 return; 1338 } 1339 1340 /* Disable Audio */ 1341 had_enable_audio(intelhaddata, false); 1342 1343 intelhaddata->connected = false; 1344 dev_dbg(intelhaddata->dev, 1345 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_DISCONNECTED\n", 1346 __func__, __LINE__); 1347 } 1348 1349 kfree(intelhaddata->chmap->chmap); 1350 intelhaddata->chmap->chmap = NULL; 1351 1352 /* Report to above ALSA layer */ 1353 substream = had_substream_get(intelhaddata); 1354 if (substream) { 1355 snd_pcm_stop_xrun(substream); 1356 had_substream_put(intelhaddata); 1357 } 1358 1359 snd_jack_report(intelhaddata->jack, 0); 1360} 1361 1362/* 1363 * ALSA iec958 and ELD controls 1364 */ 1365 1366static int had_iec958_info(struct snd_kcontrol *kcontrol, 1367 struct snd_ctl_elem_info *uinfo) 1368{ 1369 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1370 uinfo->count = 1; 1371 return 0; 1372} 1373 1374static int had_iec958_get(struct snd_kcontrol *kcontrol, 1375 struct snd_ctl_elem_value *ucontrol) 1376{ 1377 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol); 1378 1379 guard(mutex)(&intelhaddata->mutex); 1380 ucontrol->value.iec958.status[0] = (intelhaddata->aes_bits >> 0) & 0xff; 1381 ucontrol->value.iec958.status[1] = (intelhaddata->aes_bits >> 8) & 0xff; 1382 ucontrol->value.iec958.status[2] = 1383 (intelhaddata->aes_bits >> 16) & 0xff; 1384 ucontrol->value.iec958.status[3] = 1385 (intelhaddata->aes_bits >> 24) & 0xff; 1386 return 0; 1387} 1388 1389static int had_iec958_mask_get(struct snd_kcontrol *kcontrol, 1390 struct snd_ctl_elem_value *ucontrol) 1391{ 1392 ucontrol->value.iec958.status[0] = 0xff; 1393 ucontrol->value.iec958.status[1] = 0xff; 1394 ucontrol->value.iec958.status[2] = 0xff; 1395 ucontrol->value.iec958.status[3] = 0xff; 1396 return 0; 1397} 1398 1399static int had_iec958_put(struct snd_kcontrol *kcontrol, 1400 struct snd_ctl_elem_value *ucontrol) 1401{ 1402 unsigned int val; 1403 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol); 1404 int changed = 0; 1405 1406 val = (ucontrol->value.iec958.status[0] << 0) | 1407 (ucontrol->value.iec958.status[1] << 8) | 1408 (ucontrol->value.iec958.status[2] << 16) | 1409 (ucontrol->value.iec958.status[3] << 24); 1410 guard(mutex)(&intelhaddata->mutex); 1411 if (intelhaddata->aes_bits != val) { 1412 intelhaddata->aes_bits = val; 1413 changed = 1; 1414 } 1415 return changed; 1416} 1417 1418static int had_ctl_eld_info(struct snd_kcontrol *kcontrol, 1419 struct snd_ctl_elem_info *uinfo) 1420{ 1421 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 1422 uinfo->count = HDMI_MAX_ELD_BYTES; 1423 return 0; 1424} 1425 1426static int had_ctl_eld_get(struct snd_kcontrol *kcontrol, 1427 struct snd_ctl_elem_value *ucontrol) 1428{ 1429 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol); 1430 1431 guard(mutex)(&intelhaddata->mutex); 1432 memcpy(ucontrol->value.bytes.data, intelhaddata->eld, 1433 HDMI_MAX_ELD_BYTES); 1434 return 0; 1435} 1436 1437static const struct snd_kcontrol_new had_controls[] = { 1438 { 1439 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1440 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1441 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK), 1442 .info = had_iec958_info, /* shared */ 1443 .get = had_iec958_mask_get, 1444 }, 1445 { 1446 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1447 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 1448 .info = had_iec958_info, 1449 .get = had_iec958_get, 1450 .put = had_iec958_put, 1451 }, 1452 { 1453 .access = (SNDRV_CTL_ELEM_ACCESS_READ | 1454 SNDRV_CTL_ELEM_ACCESS_VOLATILE), 1455 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1456 .name = "ELD", 1457 .info = had_ctl_eld_info, 1458 .get = had_ctl_eld_get, 1459 }, 1460}; 1461 1462/* 1463 * audio interrupt handler 1464 */ 1465static irqreturn_t display_pipe_interrupt_handler(int irq, void *dev_id) 1466{ 1467 struct snd_intelhad_card *card_ctx = dev_id; 1468 u32 audio_stat[3] = {}; 1469 int pipe, port; 1470 1471 for_each_pipe(card_ctx, pipe) { 1472 /* use raw register access to ack IRQs even while disconnected */ 1473 audio_stat[pipe] = had_read_register_raw(card_ctx, pipe, 1474 AUD_HDMI_STATUS) & 1475 (HDMI_AUDIO_UNDERRUN | HDMI_AUDIO_BUFFER_DONE); 1476 1477 if (audio_stat[pipe]) 1478 had_write_register_raw(card_ctx, pipe, 1479 AUD_HDMI_STATUS, audio_stat[pipe]); 1480 } 1481 1482 for_each_port(card_ctx, port) { 1483 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port]; 1484 int pipe = ctx->pipe; 1485 1486 if (pipe < 0) 1487 continue; 1488 1489 if (audio_stat[pipe] & HDMI_AUDIO_BUFFER_DONE) 1490 had_process_buffer_done(ctx); 1491 if (audio_stat[pipe] & HDMI_AUDIO_UNDERRUN) 1492 had_process_buffer_underrun(ctx); 1493 } 1494 1495 return IRQ_HANDLED; 1496} 1497 1498/* 1499 * monitor plug/unplug notification from i915; just kick off the work 1500 */ 1501static void notify_audio_lpe(struct platform_device *pdev, int port) 1502{ 1503 struct snd_intelhad_card *card_ctx = platform_get_drvdata(pdev); 1504 struct snd_intelhad *ctx; 1505 1506 ctx = &card_ctx->pcm_ctx[single_port ? 0 : port]; 1507 if (single_port) 1508 ctx->port = port; 1509 1510 schedule_work(&ctx->hdmi_audio_wq); 1511} 1512 1513/* the work to handle monitor hot plug/unplug */ 1514static void had_audio_wq(struct work_struct *work) 1515{ 1516 struct snd_intelhad *ctx = 1517 container_of(work, struct snd_intelhad, hdmi_audio_wq); 1518 struct intel_hdmi_lpe_audio_pdata *pdata = ctx->dev->platform_data; 1519 struct intel_hdmi_lpe_audio_port_pdata *ppdata = &pdata->port[ctx->port]; 1520 int ret; 1521 1522 ret = pm_runtime_resume_and_get(ctx->dev); 1523 if (ret < 0) 1524 return; 1525 1526 mutex_lock(&ctx->mutex); 1527 if (ppdata->pipe < 0) { 1528 dev_dbg(ctx->dev, "%s: Event: HAD_NOTIFY_HOT_UNPLUG : port = %d\n", 1529 __func__, ctx->port); 1530 1531 memset(ctx->eld, 0, sizeof(ctx->eld)); /* clear the old ELD */ 1532 1533 ctx->dp_output = false; 1534 ctx->tmds_clock_speed = 0; 1535 ctx->link_rate = 0; 1536 1537 /* Shut down the stream */ 1538 had_process_hot_unplug(ctx); 1539 1540 ctx->pipe = -1; 1541 } else { 1542 dev_dbg(ctx->dev, "%s: HAD_NOTIFY_ELD : port = %d, tmds = %d\n", 1543 __func__, ctx->port, ppdata->ls_clock); 1544 1545 memcpy(ctx->eld, ppdata->eld, sizeof(ctx->eld)); 1546 1547 ctx->dp_output = ppdata->dp_output; 1548 if (ctx->dp_output) { 1549 ctx->tmds_clock_speed = 0; 1550 ctx->link_rate = ppdata->ls_clock; 1551 } else { 1552 ctx->tmds_clock_speed = ppdata->ls_clock; 1553 ctx->link_rate = 0; 1554 } 1555 1556 /* 1557 * Shut down the stream before we change 1558 * the pipe assignment for this pcm device 1559 */ 1560 had_process_hot_plug(ctx); 1561 1562 ctx->pipe = ppdata->pipe; 1563 1564 /* Restart the stream if necessary */ 1565 had_process_mode_change(ctx); 1566 } 1567 1568 mutex_unlock(&ctx->mutex); 1569 pm_runtime_put_autosuspend(ctx->dev); 1570} 1571 1572/* 1573 * Jack interface 1574 */ 1575static int had_create_jack(struct snd_intelhad *ctx, 1576 struct snd_pcm *pcm) 1577{ 1578 char hdmi_str[32]; 1579 int err; 1580 1581 snprintf(hdmi_str, sizeof(hdmi_str), 1582 "HDMI/DP,pcm=%d", pcm->device); 1583 1584 err = snd_jack_new(ctx->card_ctx->card, hdmi_str, 1585 SND_JACK_AVOUT, &ctx->jack, 1586 true, false); 1587 if (err < 0) 1588 return err; 1589 ctx->jack->private_data = ctx; 1590 return 0; 1591} 1592 1593/* 1594 * PM callbacks 1595 */ 1596 1597static int hdmi_lpe_audio_suspend(struct device *dev) 1598{ 1599 struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev); 1600 1601 snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D3hot); 1602 1603 return 0; 1604} 1605 1606static int hdmi_lpe_audio_resume(struct device *dev) 1607{ 1608 struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev); 1609 1610 pm_runtime_mark_last_busy(dev); 1611 1612 snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D0); 1613 1614 return 0; 1615} 1616 1617/* release resources */ 1618static void hdmi_lpe_audio_free(struct snd_card *card) 1619{ 1620 struct snd_intelhad_card *card_ctx = card->private_data; 1621 struct intel_hdmi_lpe_audio_pdata *pdata = card_ctx->dev->platform_data; 1622 int port; 1623 1624 scoped_guard(spinlock_irq, &pdata->lpe_audio_slock) { 1625 pdata->notify_audio_lpe = NULL; 1626 } 1627 1628 for_each_port(card_ctx, port) { 1629 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port]; 1630 1631 cancel_work_sync(&ctx->hdmi_audio_wq); 1632 } 1633} 1634 1635/* 1636 * hdmi_lpe_audio_probe - start bridge with i915 1637 * 1638 * This function is called when the i915 driver creates the 1639 * hdmi-lpe-audio platform device. 1640 */ 1641static int __hdmi_lpe_audio_probe(struct platform_device *pdev) 1642{ 1643 struct snd_card *card; 1644 struct snd_intelhad_card *card_ctx; 1645 struct snd_intelhad *ctx; 1646 struct snd_pcm *pcm; 1647 struct intel_hdmi_lpe_audio_pdata *pdata; 1648 int irq; 1649 struct resource *res_mmio; 1650 int port, ret; 1651 1652 pdata = pdev->dev.platform_data; 1653 if (!pdata) { 1654 dev_err(&pdev->dev, "%s: quit: pdata not allocated by i915!!\n", __func__); 1655 return -EINVAL; 1656 } 1657 1658 /* get resources */ 1659 irq = platform_get_irq(pdev, 0); 1660 if (irq < 0) 1661 return irq; 1662 1663 res_mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1664 if (!res_mmio) { 1665 dev_err(&pdev->dev, "Could not get IO_MEM resources\n"); 1666 return -ENXIO; 1667 } 1668 1669 /* create a card instance with ALSA framework */ 1670 ret = snd_devm_card_new(&pdev->dev, hdmi_card_index, hdmi_card_id, 1671 THIS_MODULE, sizeof(*card_ctx), &card); 1672 if (ret) 1673 return ret; 1674 1675 card_ctx = card->private_data; 1676 card_ctx->dev = &pdev->dev; 1677 card_ctx->card = card; 1678 strscpy(card->driver, INTEL_HAD); 1679 strscpy(card->shortname, "Intel HDMI/DP LPE Audio"); 1680 strscpy(card->longname, "Intel HDMI/DP LPE Audio"); 1681 1682 card_ctx->irq = -1; 1683 1684 card->private_free = hdmi_lpe_audio_free; 1685 1686 platform_set_drvdata(pdev, card_ctx); 1687 1688 card_ctx->num_pipes = pdata->num_pipes; 1689 card_ctx->num_ports = single_port ? 1 : pdata->num_ports; 1690 1691 for_each_port(card_ctx, port) { 1692 ctx = &card_ctx->pcm_ctx[port]; 1693 ctx->card_ctx = card_ctx; 1694 ctx->dev = card_ctx->dev; 1695 ctx->port = single_port ? -1 : port; 1696 ctx->pipe = -1; 1697 1698 spin_lock_init(&ctx->had_spinlock); 1699 mutex_init(&ctx->mutex); 1700 INIT_WORK(&ctx->hdmi_audio_wq, had_audio_wq); 1701 } 1702 1703 dev_dbg(&pdev->dev, "%s: mmio_start = 0x%x, mmio_end = 0x%x\n", 1704 __func__, (unsigned int)res_mmio->start, 1705 (unsigned int)res_mmio->end); 1706 1707 card_ctx->mmio_start = 1708 devm_ioremap(&pdev->dev, res_mmio->start, 1709 (size_t)(resource_size(res_mmio))); 1710 if (!card_ctx->mmio_start) { 1711 dev_err(&pdev->dev, "Could not get ioremap\n"); 1712 return -EACCES; 1713 } 1714 1715 /* setup interrupt handler */ 1716 ret = devm_request_irq(&pdev->dev, irq, display_pipe_interrupt_handler, 1717 0, pdev->name, card_ctx); 1718 if (ret < 0) { 1719 dev_err(&pdev->dev, "request_irq failed\n"); 1720 return ret; 1721 } 1722 1723 card_ctx->irq = irq; 1724 1725 /* only 32bit addressable */ 1726 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 1727 if (ret) 1728 return ret; 1729 1730 init_channel_allocations(); 1731 1732 card_ctx->num_pipes = pdata->num_pipes; 1733 card_ctx->num_ports = single_port ? 1 : pdata->num_ports; 1734 1735 for_each_port(card_ctx, port) { 1736 int i; 1737 1738 ctx = &card_ctx->pcm_ctx[port]; 1739 ret = snd_pcm_new(card, INTEL_HAD, port, MAX_PB_STREAMS, 1740 MAX_CAP_STREAMS, &pcm); 1741 if (ret) 1742 return ret; 1743 1744 /* setup private data which can be retrieved when required */ 1745 pcm->private_data = ctx; 1746 pcm->info_flags = 0; 1747 strscpy(pcm->name, card->shortname, sizeof(pcm->name)); 1748 /* setup the ops for playback */ 1749 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &had_pcm_ops); 1750 1751 /* allocate dma pages; 1752 * try to allocate 600k buffer as default which is large enough 1753 */ 1754 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_WC, 1755 card->dev, HAD_DEFAULT_BUFFER, 1756 HAD_MAX_BUFFER); 1757 1758 /* create controls */ 1759 for (i = 0; i < ARRAY_SIZE(had_controls); i++) { 1760 struct snd_kcontrol *kctl; 1761 1762 kctl = snd_ctl_new1(&had_controls[i], ctx); 1763 if (!kctl) 1764 return -ENOMEM; 1765 1766 kctl->id.device = pcm->device; 1767 1768 ret = snd_ctl_add(card, kctl); 1769 if (ret < 0) 1770 return ret; 1771 } 1772 1773 /* Register channel map controls */ 1774 ret = had_register_chmap_ctls(ctx, pcm); 1775 if (ret < 0) 1776 return ret; 1777 1778 ret = had_create_jack(ctx, pcm); 1779 if (ret < 0) 1780 return ret; 1781 } 1782 1783 ret = snd_card_register(card); 1784 if (ret) 1785 return ret; 1786 1787 scoped_guard(spinlock_irq, &pdata->lpe_audio_slock) { 1788 pdata->notify_audio_lpe = notify_audio_lpe; 1789 } 1790 1791 pm_runtime_set_autosuspend_delay(&pdev->dev, INTEL_HDMI_AUDIO_SUSPEND_DELAY_MS); 1792 pm_runtime_use_autosuspend(&pdev->dev); 1793 pm_runtime_enable(&pdev->dev); 1794 pm_runtime_mark_last_busy(&pdev->dev); 1795 pm_runtime_idle(&pdev->dev); 1796 1797 dev_dbg(&pdev->dev, "%s: handle pending notification\n", __func__); 1798 for_each_port(card_ctx, port) { 1799 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port]; 1800 1801 schedule_work(&ctx->hdmi_audio_wq); 1802 } 1803 1804 return 0; 1805} 1806 1807static int hdmi_lpe_audio_probe(struct platform_device *pdev) 1808{ 1809 return snd_card_free_on_error(&pdev->dev, __hdmi_lpe_audio_probe(pdev)); 1810} 1811 1812static const struct dev_pm_ops hdmi_lpe_audio_pm = { 1813 SYSTEM_SLEEP_PM_OPS(hdmi_lpe_audio_suspend, hdmi_lpe_audio_resume) 1814}; 1815 1816static struct platform_driver hdmi_lpe_audio_driver = { 1817 .driver = { 1818 .name = "hdmi-lpe-audio", 1819 .pm = pm_ptr(&hdmi_lpe_audio_pm), 1820 }, 1821 .probe = hdmi_lpe_audio_probe, 1822}; 1823 1824module_platform_driver(hdmi_lpe_audio_driver); 1825MODULE_ALIAS("platform:hdmi_lpe_audio"); 1826 1827MODULE_AUTHOR("Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>"); 1828MODULE_AUTHOR("Ramesh Babu K V <ramesh.babu@intel.com>"); 1829MODULE_AUTHOR("Vaibhav Agarwal <vaibhav.agarwal@intel.com>"); 1830MODULE_AUTHOR("Jerome Anand <jerome.anand@intel.com>"); 1831MODULE_DESCRIPTION("Intel HDMI Audio driver"); 1832MODULE_LICENSE("GPL v2");
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