tegra210_ahub.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * tegra210_ahub.h - TEGRA210 AHUB
  4 *
  5 * Copyright (c) 2020-2025, NVIDIA CORPORATION.  All rights reserved.
  6 *
  7 */
  8
  9#ifndef __TEGRA210_AHUB__H__
 10#define __TEGRA210_AHUB__H__
 11
 12/* Tegra210 specific */
 13#define TEGRA210_XBAR_PART1_RX				0x200
 14#define TEGRA210_XBAR_PART2_RX				0x400
 15#define TEGRA210_XBAR_RX_STRIDE				0x4
 16#define TEGRA210_XBAR_AUDIO_RX_COUNT			90
 17#define TEGRA210_XBAR_REG_MASK_0			0xf1f03ff
 18#define TEGRA210_XBAR_REG_MASK_1			0x3f30031f
 19#define TEGRA210_XBAR_REG_MASK_2			0xff1cf313
 20#define TEGRA210_XBAR_REG_MASK_3			0x0
 21#define TEGRA210_XBAR_UPDATE_MAX_REG			3
 22/* Tegra186 specific */
 23#define TEGRA186_XBAR_PART3_RX				0x600
 24#define TEGRA186_XBAR_AUDIO_RX_COUNT			115
 25#define TEGRA186_XBAR_REG_MASK_0			0xf3fffff
 26#define TEGRA186_XBAR_REG_MASK_1			0x3f310f1f
 27#define TEGRA186_XBAR_REG_MASK_2			0xff3cf311
 28#define TEGRA186_XBAR_REG_MASK_3			0x3f0f00ff
 29#define TEGRA186_XBAR_UPDATE_MAX_REG			4
 30
 31/* Tegra264 specific */
 32#define TEGRA264_XBAR_PART1_RX				0x1000
 33#define TEGRA264_XBAR_PART2_RX				0x2000
 34#define TEGRA264_XBAR_PART3_RX				0x3000
 35#define TEGRA264_XBAR_PART4_RX				0x4000
 36#define TEGRA264_XBAR_PART0_ADX6_RX1			0x224
 37#define TEGRA264_XBAR_AUDIO_RX_COUNT			((TEGRA264_XBAR_PART0_ADX6_RX1 / 4) + 1)
 38#define TEGRA264_XBAR_REG_MASK_0			0xfffffff
 39#define TEGRA264_XBAR_REG_MASK_1			0x3f013f1f
 40#define TEGRA264_XBAR_REG_MASK_2			0xff3c0301
 41#define TEGRA264_XBAR_REG_MASK_3			0x3f00ffff
 42#define TEGRA264_XBAR_REG_MASK_4			0x7fff9f
 43#define TEGRA264_XBAR_UPDATE_MAX_REG			5
 44
 45#define TEGRA264_AXBAR_ADMAIF_RX1			0x0
 46#define TEGRA264_AXBAR_SFC4_RX1				0x6c
 47#define TEGRA264_AXBAR_MIXER1_RX1			0x80
 48#define TEGRA264_AXBAR_MIXER1_RX10			0xa4
 49#define TEGRA264_AXBAR_DSPK1_RX1			0xc0
 50#define TEGRA264_AXBAR_OPE1_RX1				0x100
 51#define TEGRA264_AXBAR_MVC1_RX1				0x110
 52#define TEGRA264_AXBAR_MVC2_RX1				0x114
 53#define TEGRA264_AXBAR_AMX1_RX1				0x120
 54#define TEGRA264_AXBAR_AMX3_RX4				0x14c
 55#define TEGRA264_AXBAR_ADX1_RX1				0x160
 56#define TEGRA264_AXBAR_ASRC1_RX7			0x1a8
 57#define TEGRA264_AXBAR_ADMAIF_RX21			0x1d0
 58#define TEGRA264_AXBAR_ADX6_RX1				0x224
 59
 60#define TEGRA_XBAR_UPDATE_MAX_REG (TEGRA264_XBAR_UPDATE_MAX_REG)
 61
 62#define TEGRA264_MAX_REGISTER_ADDR (TEGRA264_XBAR_PART4_RX +		\
 63	(TEGRA210_XBAR_RX_STRIDE * (TEGRA264_XBAR_AUDIO_RX_COUNT - 1)))
 64
 65#define TEGRA186_MAX_REGISTER_ADDR (TEGRA186_XBAR_PART3_RX +		\
 66	(TEGRA210_XBAR_RX_STRIDE * (TEGRA186_XBAR_AUDIO_RX_COUNT - 1)))
 67
 68#define TEGRA210_MAX_REGISTER_ADDR (TEGRA210_XBAR_PART2_RX +		\
 69	(TEGRA210_XBAR_RX_STRIDE * (TEGRA210_XBAR_AUDIO_RX_COUNT - 1)))
 70
 71/* AXBAR register offsets */
 72#define TEGRA186_AXBAR_PART_0_AMX1_RX1_0	0x120
 73#define TEGRA186_AXBAR_PART_0_AMX3_RX4_0	0x14c
 74#define TEGRA186_AXBAR_PART_0_ASRC1_RX7_0	0x1a8
 75#define TEGRA186_AXBAR_PART_0_DSPK1_RX1_0	0xc0
 76#define TEGRA186_AXBAR_PART_0_DSPK2_RX1_0	0xc4
 77#define TEGRA186_AXBAR_PART_0_I2S6_RX1_0	0x54
 78#define TEGRA186_AXBAR_PART_0_MVC1_RX1_0	0x110
 79#define TEGRA186_AXBAR_PART_0_MVC2_RX1_0	0x114
 80#define TEGRA210_AXBAR_PART_0_ADMAIF_RX10_0	0x24
 81#define TEGRA210_AXBAR_PART_0_ADMAIF_RX1_0	0x0
 82#define TEGRA210_AXBAR_PART_0_ADX1_RX1_0	0x160
 83#define TEGRA210_AXBAR_PART_0_ADX2_RX1_0	0x164
 84#define TEGRA210_AXBAR_PART_0_AFC1_RX1_0	0xd0
 85#define TEGRA210_AXBAR_PART_0_AFC6_RX1_0	0xe4
 86#define TEGRA210_AXBAR_PART_0_AMX1_RX1_0	0x140
 87#define TEGRA210_AXBAR_PART_0_I2S1_RX1_0	0x40
 88#define TEGRA210_AXBAR_PART_0_I2S5_RX1_0	0x50
 89#define TEGRA210_AXBAR_PART_0_MIXER1_RX10_0	0xa4
 90#define TEGRA210_AXBAR_PART_0_MIXER1_RX1_0	0x80
 91#define TEGRA210_AXBAR_PART_0_MVC1_RX1_0	0x120
 92#define TEGRA210_AXBAR_PART_0_MVC2_RX1_0	0x124
 93#define TEGRA210_AXBAR_PART_0_OPE1_RX1_0	0x100
 94#define TEGRA210_AXBAR_PART_0_OPE2_RX1_0	0x104
 95#define TEGRA210_AXBAR_PART_0_SFC1_RX1_0	0x60
 96#define TEGRA210_AXBAR_PART_0_SFC4_RX1_0	0x6c
 97#define TEGRA210_AXBAR_PART_0_SPDIF1_RX1_0	0xc0
 98#define TEGRA210_AXBAR_PART_0_SPDIF1_RX2_0	0xc4
 99#define TEGRA210_AXBAR_PART_0_SPKPROT1_RX1_0	0x110
100
101#define MUX_REG(id) (TEGRA210_XBAR_RX_STRIDE * (id))
102
103#define MUX_VALUE(npart, nbit) (1 + (nbit) + (npart) * 32)
104
105#define SOC_VALUE_ENUM_WIDE(xreg, shift, xmax, xtexts, xvalues)		\
106	{								\
107		.reg = xreg,						\
108		.shift_l = shift,					\
109		.shift_r = shift,					\
110		.items = xmax,						\
111		.texts = xtexts,					\
112		.values = xvalues,					\
113		.mask = xmax ? roundup_pow_of_two(xmax) - 1 : 0		\
114	}
115
116#define SOC_VALUE_ENUM_WIDE_DECL(name, xreg, shift, xtexts, xvalues)	\
117	static struct soc_enum name =					\
118		SOC_VALUE_ENUM_WIDE(xreg, shift, ARRAY_SIZE(xtexts),	\
119				    xtexts, xvalues)
120
121#define MUX_ENUM_CTRL_DECL(ename, id)					\
122	SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, MUX_REG(id), 0,		\
123				 tegra210_ahub_mux_texts,		\
124				 tegra210_ahub_mux_values);		\
125	static const struct snd_kcontrol_new ename##_control =		\
126		SOC_DAPM_ENUM_EXT("Route", ename##_enum,		\
127				  tegra_ahub_get_value_enum,		\
128				  tegra_ahub_put_value_enum)
129
130#define MUX_ENUM_CTRL_DECL_186(ename, id)				\
131	SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, MUX_REG(id), 0,		\
132				 tegra186_ahub_mux_texts,		\
133				 tegra186_ahub_mux_values);		\
134	static const struct snd_kcontrol_new ename##_control =		\
135		SOC_DAPM_ENUM_EXT("Route", ename##_enum,		\
136				  tegra_ahub_get_value_enum,		\
137				  tegra_ahub_put_value_enum)
138
139#define MUX_ENUM_CTRL_DECL_234(ename, id) MUX_ENUM_CTRL_DECL_186(ename, id)
140
141#define MUX_ENUM_CTRL_DECL_264(ename, id)				\
142	SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, MUX_REG(id), 0,		\
143				 tegra264_ahub_mux_texts,		\
144				 tegra264_ahub_mux_values);		\
145	static const struct snd_kcontrol_new ename##_control =		\
146		SOC_DAPM_ENUM_EXT("Route", ename##_enum,		\
147				  tegra_ahub_get_value_enum,		\
148				  tegra_ahub_put_value_enum)
149
150#define WIDGETS(sname, ename)						     \
151	SND_SOC_DAPM_AIF_IN(sname " XBAR-RX", NULL, 0, SND_SOC_NOPM, 0, 0),  \
152	SND_SOC_DAPM_AIF_OUT(sname " XBAR-TX", NULL, 0, SND_SOC_NOPM, 0, 0), \
153	SND_SOC_DAPM_MUX(sname " Mux", SND_SOC_NOPM, 0, 0,		     \
154			 &ename##_control)
155
156#define TX_WIDGETS(sname)						    \
157	SND_SOC_DAPM_AIF_IN(sname " XBAR-RX", NULL, 0, SND_SOC_NOPM, 0, 0), \
158	SND_SOC_DAPM_AIF_OUT(sname " XBAR-TX", NULL, 0, SND_SOC_NOPM, 0, 0)
159
160#define DAI(sname)							\
161	{								\
162		.name = "XBAR-" #sname,					\
163		.playback = {						\
164			.stream_name = #sname " XBAR-Playback",		\
165			.channels_min = 1,				\
166			.channels_max = 32,				\
167			.rates = SNDRV_PCM_RATE_8000_192000,		\
168			.formats = SNDRV_PCM_FMTBIT_S8 |		\
169				SNDRV_PCM_FMTBIT_S16_LE |		\
170				SNDRV_PCM_FMTBIT_S24_LE |		\
171				SNDRV_PCM_FMTBIT_S32_LE,		\
172		},							\
173		.capture = {						\
174			.stream_name = #sname " XBAR-Capture",		\
175			.channels_min = 1,				\
176			.channels_max = 32,				\
177			.rates = SNDRV_PCM_RATE_8000_192000,		\
178			.formats = SNDRV_PCM_FMTBIT_S8 |		\
179				SNDRV_PCM_FMTBIT_S16_LE |		\
180				SNDRV_PCM_FMTBIT_S24_LE |		\
181				SNDRV_PCM_FMTBIT_S32_LE,		\
182		},							\
183	}
184
185struct tegra_ahub_soc_data {
186	const struct regmap_config *regmap_config;
187	const struct snd_soc_component_driver *cmpnt_drv;
188	struct snd_soc_dai_driver *dai_drv;
189	unsigned int mask[TEGRA_XBAR_UPDATE_MAX_REG];
190	unsigned int reg_count;
191	unsigned int num_dais;
192	unsigned int xbar_part_size;
193};
194
195struct tegra_ahub {
196	const struct tegra_ahub_soc_data *soc_data;
197	struct regmap *regmap;
198	struct clk *clk;
199};
200
201#endif