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tegra210_ahub.c
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linux-6.19.14/sound/soc/tegra/tegra210_ahub.c
1// SPDX-License-Identifier: GPL-2.0-only 2// 3// tegra210_ahub.c - Tegra210 AHUB driver 4// 5// Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved. 6 7#include <linux/clk.h> 8#include <linux/device.h> 9#include <linux/module.h> 10#include <linux/of_platform.h> 11#include <linux/platform_device.h> 12#include <linux/pm_runtime.h> 13#include <linux/regmap.h> 14#include <sound/soc.h> 15#include "tegra210_ahub.h" 16 17static int tegra_ahub_get_value_enum(struct snd_kcontrol *kctl, 18 struct snd_ctl_elem_value *uctl) 19{ 20 struct snd_soc_component *cmpnt = snd_soc_dapm_kcontrol_to_component(kctl); 21 struct tegra_ahub *ahub = snd_soc_component_get_drvdata(cmpnt); 22 struct soc_enum *e = (struct soc_enum *)kctl->private_value; 23 unsigned int reg, i, bit_pos = 0; 24 25 /* 26 * Find the bit position of current MUX input. 27 * If nothing is set, position would be 0 and it corresponds to 'None'. 28 */ 29 for (i = 0; i < ahub->soc_data->reg_count; i++) { 30 unsigned int reg_val; 31 32 reg = e->reg + (ahub->soc_data->xbar_part_size * i); 33 reg_val = snd_soc_component_read(cmpnt, reg); 34 reg_val &= ahub->soc_data->mask[i]; 35 36 if (reg_val) { 37 bit_pos = ffs(reg_val) + 38 (8 * cmpnt->val_bytes * i); 39 break; 40 } 41 } 42 43 /* Find index related to the item in array *_ahub_mux_texts[] */ 44 for (i = 0; i < e->items; i++) { 45 if (bit_pos == e->values[i]) { 46 uctl->value.enumerated.item[0] = i; 47 break; 48 } 49 } 50 51 return 0; 52} 53 54static int tegra_ahub_put_value_enum(struct snd_kcontrol *kctl, 55 struct snd_ctl_elem_value *uctl) 56{ 57 struct snd_soc_component *cmpnt = snd_soc_dapm_kcontrol_to_component(kctl); 58 struct tegra_ahub *ahub = snd_soc_component_get_drvdata(cmpnt); 59 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kctl); 60 struct soc_enum *e = (struct soc_enum *)kctl->private_value; 61 struct snd_soc_dapm_update update[TEGRA_XBAR_UPDATE_MAX_REG] = { }; 62 unsigned int *item = uctl->value.enumerated.item; 63 unsigned int value = e->values[item[0]]; 64 unsigned int i, bit_pos, reg_idx = 0, reg_val = 0; 65 int change = 0; 66 67 if (item[0] >= e->items) 68 return -EINVAL; 69 70 if (value) { 71 /* Get the register index and value to set */ 72 reg_idx = (value - 1) / (8 * cmpnt->val_bytes); 73 bit_pos = (value - 1) % (8 * cmpnt->val_bytes); 74 reg_val = BIT(bit_pos); 75 } 76 77 /* 78 * Run through all parts of a MUX register to find the state changes. 79 * There will be an additional update if new MUX input value is from 80 * different part of the MUX register. 81 */ 82 for (i = 0; i < ahub->soc_data->reg_count; i++) { 83 update[i].reg = e->reg + (ahub->soc_data->xbar_part_size * i); 84 update[i].val = (i == reg_idx) ? reg_val : 0; 85 update[i].mask = ahub->soc_data->mask[i]; 86 update[i].kcontrol = kctl; 87 88 /* Update widget power if state has changed */ 89 if (snd_soc_component_test_bits(cmpnt, update[i].reg, 90 update[i].mask, 91 update[i].val)) 92 change |= snd_soc_dapm_mux_update_power(dapm, kctl, 93 item[0], e, 94 &update[i]); 95 } 96 97 return change; 98} 99 100static struct snd_soc_dai_driver tegra210_ahub_dais[] = { 101 DAI(ADMAIF1), 102 DAI(ADMAIF2), 103 DAI(ADMAIF3), 104 DAI(ADMAIF4), 105 DAI(ADMAIF5), 106 DAI(ADMAIF6), 107 DAI(ADMAIF7), 108 DAI(ADMAIF8), 109 DAI(ADMAIF9), 110 DAI(ADMAIF10), 111 /* XBAR <-> I2S <-> Codec */ 112 DAI(I2S1), 113 DAI(I2S2), 114 DAI(I2S3), 115 DAI(I2S4), 116 DAI(I2S5), 117 /* XBAR <- DMIC <- Codec */ 118 DAI(DMIC1), 119 DAI(DMIC2), 120 DAI(DMIC3), 121 /* XBAR -> SFC -> XBAR */ 122 DAI(SFC1 RX), 123 DAI(SFC1 TX), 124 DAI(SFC2 RX), 125 DAI(SFC2 TX), 126 DAI(SFC3 RX), 127 DAI(SFC3 TX), 128 DAI(SFC4 RX), 129 DAI(SFC4 TX), 130 /* XBAR -> MVC -> XBAR */ 131 DAI(MVC1 RX), 132 DAI(MVC1 TX), 133 DAI(MVC2 RX), 134 DAI(MVC2 TX), 135 /* XBAR -> AMX(4:1) -> XBAR */ 136 DAI(AMX1 RX1), 137 DAI(AMX1 RX2), 138 DAI(AMX1 RX3), 139 DAI(AMX1 RX4), 140 DAI(AMX1), 141 DAI(AMX2 RX1), 142 DAI(AMX2 RX2), 143 DAI(AMX2 RX3), 144 DAI(AMX2 RX4), 145 DAI(AMX2), 146 /* XBAR -> ADX(1:4) -> XBAR */ 147 DAI(ADX1), 148 DAI(ADX1 TX1), 149 DAI(ADX1 TX2), 150 DAI(ADX1 TX3), 151 DAI(ADX1 TX4), 152 DAI(ADX2), 153 DAI(ADX2 TX1), 154 DAI(ADX2 TX2), 155 DAI(ADX2 TX3), 156 DAI(ADX2 TX4), 157 /* XBAR -> MIXER(10:5) -> XBAR */ 158 DAI(MIXER1 RX1), 159 DAI(MIXER1 RX2), 160 DAI(MIXER1 RX3), 161 DAI(MIXER1 RX4), 162 DAI(MIXER1 RX5), 163 DAI(MIXER1 RX6), 164 DAI(MIXER1 RX7), 165 DAI(MIXER1 RX8), 166 DAI(MIXER1 RX9), 167 DAI(MIXER1 RX10), 168 DAI(MIXER1 TX1), 169 DAI(MIXER1 TX2), 170 DAI(MIXER1 TX3), 171 DAI(MIXER1 TX4), 172 DAI(MIXER1 TX5), 173 /* XBAR -> OPE -> XBAR */ 174 DAI(OPE1 RX), 175 DAI(OPE1 TX), 176 DAI(OPE2 RX), 177 DAI(OPE2 TX), 178}; 179 180static struct snd_soc_dai_driver tegra186_ahub_dais[] = { 181 DAI(ADMAIF1), 182 DAI(ADMAIF2), 183 DAI(ADMAIF3), 184 DAI(ADMAIF4), 185 DAI(ADMAIF5), 186 DAI(ADMAIF6), 187 DAI(ADMAIF7), 188 DAI(ADMAIF8), 189 DAI(ADMAIF9), 190 DAI(ADMAIF10), 191 DAI(ADMAIF11), 192 DAI(ADMAIF12), 193 DAI(ADMAIF13), 194 DAI(ADMAIF14), 195 DAI(ADMAIF15), 196 DAI(ADMAIF16), 197 DAI(ADMAIF17), 198 DAI(ADMAIF18), 199 DAI(ADMAIF19), 200 DAI(ADMAIF20), 201 /* XBAR <-> I2S <-> Codec */ 202 DAI(I2S1), 203 DAI(I2S2), 204 DAI(I2S3), 205 DAI(I2S4), 206 DAI(I2S5), 207 DAI(I2S6), 208 /* XBAR <- DMIC <- Codec */ 209 DAI(DMIC1), 210 DAI(DMIC2), 211 DAI(DMIC3), 212 DAI(DMIC4), 213 /* XBAR -> DSPK -> Codec */ 214 DAI(DSPK1), 215 DAI(DSPK2), 216 /* XBAR -> SFC -> XBAR */ 217 DAI(SFC1 RX), 218 DAI(SFC1 TX), 219 DAI(SFC2 RX), 220 DAI(SFC2 TX), 221 DAI(SFC3 RX), 222 DAI(SFC3 TX), 223 DAI(SFC4 RX), 224 DAI(SFC4 TX), 225 /* XBAR -> MVC -> XBAR */ 226 DAI(MVC1 RX), 227 DAI(MVC1 TX), 228 DAI(MVC2 RX), 229 DAI(MVC2 TX), 230 /* XBAR -> AMX(4:1) -> XBAR */ 231 DAI(AMX1 RX1), 232 DAI(AMX1 RX2), 233 DAI(AMX1 RX3), 234 DAI(AMX1 RX4), 235 DAI(AMX1), 236 DAI(AMX2 RX1), 237 DAI(AMX2 RX2), 238 DAI(AMX2 RX3), 239 DAI(AMX2 RX4), 240 DAI(AMX2), 241 DAI(AMX3 RX1), 242 DAI(AMX3 RX2), 243 DAI(AMX3 RX3), 244 DAI(AMX3 RX4), 245 DAI(AMX3), 246 DAI(AMX4 RX1), 247 DAI(AMX4 RX2), 248 DAI(AMX4 RX3), 249 DAI(AMX4 RX4), 250 DAI(AMX4), 251 /* XBAR -> ADX(1:4) -> XBAR */ 252 DAI(ADX1), 253 DAI(ADX1 TX1), 254 DAI(ADX1 TX2), 255 DAI(ADX1 TX3), 256 DAI(ADX1 TX4), 257 DAI(ADX2), 258 DAI(ADX2 TX1), 259 DAI(ADX2 TX2), 260 DAI(ADX2 TX3), 261 DAI(ADX2 TX4), 262 DAI(ADX3), 263 DAI(ADX3 TX1), 264 DAI(ADX3 TX2), 265 DAI(ADX3 TX3), 266 DAI(ADX3 TX4), 267 DAI(ADX4), 268 DAI(ADX4 TX1), 269 DAI(ADX4 TX2), 270 DAI(ADX4 TX3), 271 DAI(ADX4 TX4), 272 /* XBAR -> MIXER1(10:5) -> XBAR */ 273 DAI(MIXER1 RX1), 274 DAI(MIXER1 RX2), 275 DAI(MIXER1 RX3), 276 DAI(MIXER1 RX4), 277 DAI(MIXER1 RX5), 278 DAI(MIXER1 RX6), 279 DAI(MIXER1 RX7), 280 DAI(MIXER1 RX8), 281 DAI(MIXER1 RX9), 282 DAI(MIXER1 RX10), 283 DAI(MIXER1 TX1), 284 DAI(MIXER1 TX2), 285 DAI(MIXER1 TX3), 286 DAI(MIXER1 TX4), 287 DAI(MIXER1 TX5), 288 /* XBAR -> ASRC -> XBAR */ 289 DAI(ASRC1 RX1), 290 DAI(ASRC1 TX1), 291 DAI(ASRC1 RX2), 292 DAI(ASRC1 TX2), 293 DAI(ASRC1 RX3), 294 DAI(ASRC1 TX3), 295 DAI(ASRC1 RX4), 296 DAI(ASRC1 TX4), 297 DAI(ASRC1 RX5), 298 DAI(ASRC1 TX5), 299 DAI(ASRC1 RX6), 300 DAI(ASRC1 TX6), 301 DAI(ASRC1 RX7), 302 /* XBAR -> OPE -> XBAR */ 303 DAI(OPE1 RX), 304 DAI(OPE1 TX), 305}; 306 307static struct snd_soc_dai_driver tegra264_ahub_dais[] = { 308 DAI(ADMAIF1), 309 DAI(ADMAIF2), 310 DAI(ADMAIF3), 311 DAI(ADMAIF4), 312 DAI(ADMAIF5), 313 DAI(ADMAIF6), 314 DAI(ADMAIF7), 315 DAI(ADMAIF8), 316 DAI(ADMAIF9), 317 DAI(ADMAIF10), 318 DAI(ADMAIF11), 319 DAI(ADMAIF12), 320 DAI(ADMAIF13), 321 DAI(ADMAIF14), 322 DAI(ADMAIF15), 323 DAI(ADMAIF16), 324 DAI(ADMAIF17), 325 DAI(ADMAIF18), 326 DAI(ADMAIF19), 327 DAI(ADMAIF20), 328 DAI(ADMAIF21), 329 DAI(ADMAIF22), 330 DAI(ADMAIF23), 331 DAI(ADMAIF24), 332 DAI(ADMAIF25), 333 DAI(ADMAIF26), 334 DAI(ADMAIF27), 335 DAI(ADMAIF28), 336 DAI(ADMAIF29), 337 DAI(ADMAIF30), 338 DAI(ADMAIF31), 339 DAI(ADMAIF32), 340 /* XBAR <-> I2S <-> Codec */ 341 DAI(I2S1), 342 DAI(I2S2), 343 DAI(I2S3), 344 DAI(I2S4), 345 DAI(I2S5), 346 DAI(I2S6), 347 DAI(I2S7), 348 DAI(I2S8), 349 /* XBAR <-> DMIC <-> Codec */ 350 DAI(DMIC1), 351 DAI(DMIC2), 352 /* XBAR <-> DSPK <-> Codec */ 353 DAI(DSPK1), 354 /* XBAR -> SFC -> XBAR */ 355 DAI(SFC1 RX), 356 DAI(SFC1 TX), 357 DAI(SFC2 RX), 358 DAI(SFC2 TX), 359 DAI(SFC3 RX), 360 DAI(SFC3 TX), 361 DAI(SFC4 RX), 362 DAI(SFC4 TX), 363 /* XBAR -> MVC -> XBAR */ 364 DAI(MVC1 RX), 365 DAI(MVC1 TX), 366 DAI(MVC2 RX), 367 DAI(MVC2 TX), 368 /* XBAR -> AMX(4:1) -> XBAR */ 369 DAI(AMX1 RX1), 370 DAI(AMX1 RX2), 371 DAI(AMX1 RX3), 372 DAI(AMX1 RX4), 373 DAI(AMX1), 374 DAI(AMX2 RX1), 375 DAI(AMX2 RX2), 376 DAI(AMX2 RX3), 377 DAI(AMX2 RX4), 378 DAI(AMX2), 379 DAI(AMX3 RX1), 380 DAI(AMX3 RX2), 381 DAI(AMX3 RX3), 382 DAI(AMX3 RX4), 383 DAI(AMX3), 384 DAI(AMX4 RX1), 385 DAI(AMX4 RX2), 386 DAI(AMX4 RX3), 387 DAI(AMX4 RX4), 388 DAI(AMX4), 389 DAI(AMX5 RX1), 390 DAI(AMX5 RX2), 391 DAI(AMX5 RX3), 392 DAI(AMX5 RX4), 393 DAI(AMX5), 394 DAI(AMX6 RX1), 395 DAI(AMX6 RX2), 396 DAI(AMX6 RX3), 397 DAI(AMX6 RX4), 398 DAI(AMX6), 399 /* XBAR -> ADX(1:4) -> XBAR */ 400 DAI(ADX1), 401 DAI(ADX1 TX1), 402 DAI(ADX1 TX2), 403 DAI(ADX1 TX3), 404 DAI(ADX1 TX4), 405 DAI(ADX2), 406 DAI(ADX2 TX1), 407 DAI(ADX2 TX2), 408 DAI(ADX2 TX3), 409 DAI(ADX2 TX4), 410 DAI(ADX3), 411 DAI(ADX3 TX1), 412 DAI(ADX3 TX2), 413 DAI(ADX3 TX3), 414 DAI(ADX3 TX4), 415 DAI(ADX4), 416 DAI(ADX4 TX1), 417 DAI(ADX4 TX2), 418 DAI(ADX4 TX3), 419 DAI(ADX4 TX4), 420 DAI(ADX5), 421 DAI(ADX5 TX1), 422 DAI(ADX5 TX2), 423 DAI(ADX5 TX3), 424 DAI(ADX5 TX4), 425 DAI(ADX6), 426 DAI(ADX6 TX1), 427 DAI(ADX6 TX2), 428 DAI(ADX6 TX3), 429 DAI(ADX6 TX4), 430 /* XBAR -> MIXER1(10:5) -> XBAR */ 431 DAI(MIXER1 RX1), 432 DAI(MIXER1 RX2), 433 DAI(MIXER1 RX3), 434 DAI(MIXER1 RX4), 435 DAI(MIXER1 RX5), 436 DAI(MIXER1 RX6), 437 DAI(MIXER1 RX7), 438 DAI(MIXER1 RX8), 439 DAI(MIXER1 RX9), 440 DAI(MIXER1 RX10), 441 DAI(MIXER1 TX1), 442 DAI(MIXER1 TX2), 443 DAI(MIXER1 TX3), 444 DAI(MIXER1 TX4), 445 DAI(MIXER1 TX5), 446 /* XBAR -> ASRC -> XBAR */ 447 DAI(ASRC1 RX1), 448 DAI(ASRC1 TX1), 449 DAI(ASRC1 RX2), 450 DAI(ASRC1 TX2), 451 DAI(ASRC1 RX3), 452 DAI(ASRC1 TX3), 453 DAI(ASRC1 RX4), 454 DAI(ASRC1 TX4), 455 DAI(ASRC1 RX5), 456 DAI(ASRC1 TX5), 457 DAI(ASRC1 RX6), 458 DAI(ASRC1 TX6), 459 DAI(ASRC1 RX7), 460 /* XBAR -> OPE -> XBAR */ 461 DAI(OPE1 RX), 462 DAI(OPE1 TX), 463}; 464 465static const char * const tegra210_ahub_mux_texts[] = { 466 "None", 467 "ADMAIF1", 468 "ADMAIF2", 469 "ADMAIF3", 470 "ADMAIF4", 471 "ADMAIF5", 472 "ADMAIF6", 473 "ADMAIF7", 474 "ADMAIF8", 475 "ADMAIF9", 476 "ADMAIF10", 477 "I2S1", 478 "I2S2", 479 "I2S3", 480 "I2S4", 481 "I2S5", 482 "DMIC1", 483 "DMIC2", 484 "DMIC3", 485 "SFC1", 486 "SFC2", 487 "SFC3", 488 "SFC4", 489 "MVC1", 490 "MVC2", 491 "AMX1", 492 "AMX2", 493 "ADX1 TX1", 494 "ADX1 TX2", 495 "ADX1 TX3", 496 "ADX1 TX4", 497 "ADX2 TX1", 498 "ADX2 TX2", 499 "ADX2 TX3", 500 "ADX2 TX4", 501 "MIXER1 TX1", 502 "MIXER1 TX2", 503 "MIXER1 TX3", 504 "MIXER1 TX4", 505 "MIXER1 TX5", 506 "OPE1", 507 "OPE2", 508}; 509 510static const char * const tegra186_ahub_mux_texts[] = { 511 "None", 512 "ADMAIF1", 513 "ADMAIF2", 514 "ADMAIF3", 515 "ADMAIF4", 516 "ADMAIF5", 517 "ADMAIF6", 518 "ADMAIF7", 519 "ADMAIF8", 520 "ADMAIF9", 521 "ADMAIF10", 522 "ADMAIF11", 523 "ADMAIF12", 524 "ADMAIF13", 525 "ADMAIF14", 526 "ADMAIF15", 527 "ADMAIF16", 528 "I2S1", 529 "I2S2", 530 "I2S3", 531 "I2S4", 532 "I2S5", 533 "I2S6", 534 "ADMAIF17", 535 "ADMAIF18", 536 "ADMAIF19", 537 "ADMAIF20", 538 "DMIC1", 539 "DMIC2", 540 "DMIC3", 541 "DMIC4", 542 "SFC1", 543 "SFC2", 544 "SFC3", 545 "SFC4", 546 "MVC1", 547 "MVC2", 548 "AMX1", 549 "AMX2", 550 "AMX3", 551 "AMX4", 552 "ADX1 TX1", 553 "ADX1 TX2", 554 "ADX1 TX3", 555 "ADX1 TX4", 556 "ADX2 TX1", 557 "ADX2 TX2", 558 "ADX2 TX3", 559 "ADX2 TX4", 560 "ADX3 TX1", 561 "ADX3 TX2", 562 "ADX3 TX3", 563 "ADX3 TX4", 564 "ADX4 TX1", 565 "ADX4 TX2", 566 "ADX4 TX3", 567 "ADX4 TX4", 568 "MIXER1 TX1", 569 "MIXER1 TX2", 570 "MIXER1 TX3", 571 "MIXER1 TX4", 572 "MIXER1 TX5", 573 "ASRC1 TX1", 574 "ASRC1 TX2", 575 "ASRC1 TX3", 576 "ASRC1 TX4", 577 "ASRC1 TX5", 578 "ASRC1 TX6", 579 "OPE1", 580}; 581 582static const char * const tegra264_ahub_mux_texts[] = { 583 "None", 584 "ADMAIF1", 585 "ADMAIF2", 586 "ADMAIF3", 587 "ADMAIF4", 588 "ADMAIF5", 589 "ADMAIF6", 590 "ADMAIF7", 591 "ADMAIF8", 592 "ADMAIF9", 593 "ADMAIF10", 594 "ADMAIF11", 595 "ADMAIF12", 596 "ADMAIF13", 597 "ADMAIF14", 598 "ADMAIF15", 599 "ADMAIF16", 600 "I2S1", 601 "I2S2", 602 "I2S3", 603 "I2S4", 604 "I2S5", 605 "I2S6", 606 "I2S7", 607 "I2S8", 608 "SFC1", 609 "SFC2", 610 "SFC3", 611 "SFC4", 612 "MIXER1 TX1", 613 "MIXER1 TX2", 614 "MIXER1 TX3", 615 "MIXER1 TX4", 616 "MIXER1 TX5", 617 "AMX1", 618 "AMX2", 619 "AMX3", 620 "AMX4", 621 "AMX5", 622 "AMX6", 623 "OPE1", 624 "MVC1", 625 "MVC2", 626 "DMIC1", 627 "DMIC2", 628 "ADX1 TX1", 629 "ADX1 TX2", 630 "ADX1 TX3", 631 "ADX1 TX4", 632 "ADX2 TX1", 633 "ADX2 TX2", 634 "ADX2 TX3", 635 "ADX2 TX4", 636 "ADX3 TX1", 637 "ADX3 TX2", 638 "ADX3 TX3", 639 "ADX3 TX4", 640 "ADX4 TX1", 641 "ADX4 TX2", 642 "ADX4 TX3", 643 "ADX4 TX4", 644 "ADX5 TX1", 645 "ADX5 TX2", 646 "ADX5 TX3", 647 "ADX5 TX4", 648 "ADX6 TX1", 649 "ADX6 TX2", 650 "ADX6 TX3", 651 "ADX6 TX4", 652 "ASRC1 TX1", 653 "ASRC1 TX2", 654 "ASRC1 TX3", 655 "ASRC1 TX4", 656 "ASRC1 TX5", 657 "ASRC1 TX6", 658 "ADMAIF17", 659 "ADMAIF18", 660 "ADMAIF19", 661 "ADMAIF20", 662 "ADMAIF21", 663 "ADMAIF22", 664 "ADMAIF23", 665 "ADMAIF24", 666 "ADMAIF25", 667 "ADMAIF26", 668 "ADMAIF27", 669 "ADMAIF28", 670 "ADMAIF29", 671 "ADMAIF30", 672 "ADMAIF31", 673 "ADMAIF32", 674}; 675 676static const unsigned int tegra210_ahub_mux_values[] = { 677 0, 678 /* ADMAIF */ 679 MUX_VALUE(0, 0), 680 MUX_VALUE(0, 1), 681 MUX_VALUE(0, 2), 682 MUX_VALUE(0, 3), 683 MUX_VALUE(0, 4), 684 MUX_VALUE(0, 5), 685 MUX_VALUE(0, 6), 686 MUX_VALUE(0, 7), 687 MUX_VALUE(0, 8), 688 MUX_VALUE(0, 9), 689 /* I2S */ 690 MUX_VALUE(0, 16), 691 MUX_VALUE(0, 17), 692 MUX_VALUE(0, 18), 693 MUX_VALUE(0, 19), 694 MUX_VALUE(0, 20), 695 /* DMIC */ 696 MUX_VALUE(2, 18), 697 MUX_VALUE(2, 19), 698 MUX_VALUE(2, 20), 699 /* SFC */ 700 MUX_VALUE(0, 24), 701 MUX_VALUE(0, 25), 702 MUX_VALUE(0, 26), 703 MUX_VALUE(0, 27), 704 /* MVC */ 705 MUX_VALUE(2, 8), 706 MUX_VALUE(2, 9), 707 /* AMX */ 708 MUX_VALUE(1, 8), 709 MUX_VALUE(1, 9), 710 /* ADX */ 711 MUX_VALUE(2, 24), 712 MUX_VALUE(2, 25), 713 MUX_VALUE(2, 26), 714 MUX_VALUE(2, 27), 715 MUX_VALUE(2, 28), 716 MUX_VALUE(2, 29), 717 MUX_VALUE(2, 30), 718 MUX_VALUE(2, 31), 719 /* MIXER */ 720 MUX_VALUE(1, 0), 721 MUX_VALUE(1, 1), 722 MUX_VALUE(1, 2), 723 MUX_VALUE(1, 3), 724 MUX_VALUE(1, 4), 725 /* OPE */ 726 MUX_VALUE(2, 0), 727 MUX_VALUE(2, 1), 728}; 729 730static const unsigned int tegra186_ahub_mux_values[] = { 731 0, 732 /* ADMAIF */ 733 MUX_VALUE(0, 0), 734 MUX_VALUE(0, 1), 735 MUX_VALUE(0, 2), 736 MUX_VALUE(0, 3), 737 MUX_VALUE(0, 4), 738 MUX_VALUE(0, 5), 739 MUX_VALUE(0, 6), 740 MUX_VALUE(0, 7), 741 MUX_VALUE(0, 8), 742 MUX_VALUE(0, 9), 743 MUX_VALUE(0, 10), 744 MUX_VALUE(0, 11), 745 MUX_VALUE(0, 12), 746 MUX_VALUE(0, 13), 747 MUX_VALUE(0, 14), 748 MUX_VALUE(0, 15), 749 /* I2S */ 750 MUX_VALUE(0, 16), 751 MUX_VALUE(0, 17), 752 MUX_VALUE(0, 18), 753 MUX_VALUE(0, 19), 754 MUX_VALUE(0, 20), 755 MUX_VALUE(0, 21), 756 /* ADMAIF */ 757 MUX_VALUE(3, 16), 758 MUX_VALUE(3, 17), 759 MUX_VALUE(3, 18), 760 MUX_VALUE(3, 19), 761 /* DMIC */ 762 MUX_VALUE(2, 18), 763 MUX_VALUE(2, 19), 764 MUX_VALUE(2, 20), 765 MUX_VALUE(2, 21), 766 /* SFC */ 767 MUX_VALUE(0, 24), 768 MUX_VALUE(0, 25), 769 MUX_VALUE(0, 26), 770 MUX_VALUE(0, 27), 771 /* MVC */ 772 MUX_VALUE(2, 8), 773 MUX_VALUE(2, 9), 774 /* AMX */ 775 MUX_VALUE(1, 8), 776 MUX_VALUE(1, 9), 777 MUX_VALUE(1, 10), 778 MUX_VALUE(1, 11), 779 /* ADX */ 780 MUX_VALUE(2, 24), 781 MUX_VALUE(2, 25), 782 MUX_VALUE(2, 26), 783 MUX_VALUE(2, 27), 784 MUX_VALUE(2, 28), 785 MUX_VALUE(2, 29), 786 MUX_VALUE(2, 30), 787 MUX_VALUE(2, 31), 788 MUX_VALUE(3, 0), 789 MUX_VALUE(3, 1), 790 MUX_VALUE(3, 2), 791 MUX_VALUE(3, 3), 792 MUX_VALUE(3, 4), 793 MUX_VALUE(3, 5), 794 MUX_VALUE(3, 6), 795 MUX_VALUE(3, 7), 796 /* MIXER */ 797 MUX_VALUE(1, 0), 798 MUX_VALUE(1, 1), 799 MUX_VALUE(1, 2), 800 MUX_VALUE(1, 3), 801 MUX_VALUE(1, 4), 802 /* ASRC */ 803 MUX_VALUE(3, 24), 804 MUX_VALUE(3, 25), 805 MUX_VALUE(3, 26), 806 MUX_VALUE(3, 27), 807 MUX_VALUE(3, 28), 808 MUX_VALUE(3, 29), 809 /* OPE */ 810 MUX_VALUE(2, 0), 811}; 812 813static const unsigned int tegra264_ahub_mux_values[] = { 814 0, 815 /* ADMAIF */ 816 MUX_VALUE(0, 0), 817 MUX_VALUE(0, 1), 818 MUX_VALUE(0, 2), 819 MUX_VALUE(0, 3), 820 MUX_VALUE(0, 4), 821 MUX_VALUE(0, 5), 822 MUX_VALUE(0, 6), 823 MUX_VALUE(0, 7), 824 MUX_VALUE(0, 8), 825 MUX_VALUE(0, 9), 826 MUX_VALUE(0, 10), 827 MUX_VALUE(0, 11), 828 MUX_VALUE(0, 12), 829 MUX_VALUE(0, 13), 830 MUX_VALUE(0, 14), 831 MUX_VALUE(0, 15), 832 /* I2S */ 833 MUX_VALUE(0, 16), 834 MUX_VALUE(0, 17), 835 MUX_VALUE(0, 18), 836 MUX_VALUE(0, 19), 837 MUX_VALUE(0, 20), 838 MUX_VALUE(0, 21), 839 MUX_VALUE(0, 22), 840 MUX_VALUE(0, 23), 841 /* SFC */ 842 MUX_VALUE(0, 24), 843 MUX_VALUE(0, 25), 844 MUX_VALUE(0, 26), 845 MUX_VALUE(0, 27), 846 /* MIXER */ 847 MUX_VALUE(1, 0), 848 MUX_VALUE(1, 1), 849 MUX_VALUE(1, 2), 850 MUX_VALUE(1, 3), 851 MUX_VALUE(1, 4), 852 /* AMX */ 853 MUX_VALUE(1, 8), 854 MUX_VALUE(1, 9), 855 MUX_VALUE(1, 10), 856 MUX_VALUE(1, 11), 857 MUX_VALUE(1, 12), 858 MUX_VALUE(1, 13), 859 /* OPE */ 860 MUX_VALUE(2, 0), 861 /* MVC */ 862 MUX_VALUE(2, 8), 863 MUX_VALUE(2, 9), 864 /* DMIC */ 865 MUX_VALUE(2, 18), 866 MUX_VALUE(2, 19), 867 /* ADX */ 868 MUX_VALUE(2, 24), 869 MUX_VALUE(2, 25), 870 MUX_VALUE(2, 26), 871 MUX_VALUE(2, 27), 872 MUX_VALUE(2, 28), 873 MUX_VALUE(2, 29), 874 MUX_VALUE(2, 30), 875 MUX_VALUE(2, 31), 876 MUX_VALUE(3, 0), 877 MUX_VALUE(3, 1), 878 MUX_VALUE(3, 2), 879 MUX_VALUE(3, 3), 880 MUX_VALUE(3, 4), 881 MUX_VALUE(3, 5), 882 MUX_VALUE(3, 6), 883 MUX_VALUE(3, 7), 884 MUX_VALUE(3, 8), 885 MUX_VALUE(3, 9), 886 MUX_VALUE(3, 10), 887 MUX_VALUE(3, 11), 888 MUX_VALUE(3, 12), 889 MUX_VALUE(3, 13), 890 MUX_VALUE(3, 14), 891 MUX_VALUE(3, 15), 892 /* ASRC */ 893 MUX_VALUE(3, 24), 894 MUX_VALUE(3, 25), 895 MUX_VALUE(3, 26), 896 MUX_VALUE(3, 27), 897 MUX_VALUE(3, 28), 898 MUX_VALUE(3, 29), 899 /* ADMAIF */ 900 MUX_VALUE(4, 7), 901 MUX_VALUE(4, 8), 902 MUX_VALUE(4, 9), 903 MUX_VALUE(4, 10), 904 MUX_VALUE(4, 11), 905 MUX_VALUE(4, 12), 906 MUX_VALUE(4, 13), 907 MUX_VALUE(4, 14), 908 MUX_VALUE(4, 15), 909 MUX_VALUE(4, 16), 910 MUX_VALUE(4, 17), 911 MUX_VALUE(4, 18), 912 MUX_VALUE(4, 19), 913 MUX_VALUE(4, 20), 914 MUX_VALUE(4, 21), 915 MUX_VALUE(4, 22), 916}; 917 918/* Controls for t210 */ 919MUX_ENUM_CTRL_DECL(t210_admaif1_tx, 0x00); 920MUX_ENUM_CTRL_DECL(t210_admaif2_tx, 0x01); 921MUX_ENUM_CTRL_DECL(t210_admaif3_tx, 0x02); 922MUX_ENUM_CTRL_DECL(t210_admaif4_tx, 0x03); 923MUX_ENUM_CTRL_DECL(t210_admaif5_tx, 0x04); 924MUX_ENUM_CTRL_DECL(t210_admaif6_tx, 0x05); 925MUX_ENUM_CTRL_DECL(t210_admaif7_tx, 0x06); 926MUX_ENUM_CTRL_DECL(t210_admaif8_tx, 0x07); 927MUX_ENUM_CTRL_DECL(t210_admaif9_tx, 0x08); 928MUX_ENUM_CTRL_DECL(t210_admaif10_tx, 0x09); 929MUX_ENUM_CTRL_DECL(t210_i2s1_tx, 0x10); 930MUX_ENUM_CTRL_DECL(t210_i2s2_tx, 0x11); 931MUX_ENUM_CTRL_DECL(t210_i2s3_tx, 0x12); 932MUX_ENUM_CTRL_DECL(t210_i2s4_tx, 0x13); 933MUX_ENUM_CTRL_DECL(t210_i2s5_tx, 0x14); 934MUX_ENUM_CTRL_DECL(t210_sfc1_tx, 0x18); 935MUX_ENUM_CTRL_DECL(t210_sfc2_tx, 0x19); 936MUX_ENUM_CTRL_DECL(t210_sfc3_tx, 0x1a); 937MUX_ENUM_CTRL_DECL(t210_sfc4_tx, 0x1b); 938MUX_ENUM_CTRL_DECL(t210_mvc1_tx, 0x48); 939MUX_ENUM_CTRL_DECL(t210_mvc2_tx, 0x49); 940MUX_ENUM_CTRL_DECL(t210_amx11_tx, 0x50); 941MUX_ENUM_CTRL_DECL(t210_amx12_tx, 0x51); 942MUX_ENUM_CTRL_DECL(t210_amx13_tx, 0x52); 943MUX_ENUM_CTRL_DECL(t210_amx14_tx, 0x53); 944MUX_ENUM_CTRL_DECL(t210_amx21_tx, 0x54); 945MUX_ENUM_CTRL_DECL(t210_amx22_tx, 0x55); 946MUX_ENUM_CTRL_DECL(t210_amx23_tx, 0x56); 947MUX_ENUM_CTRL_DECL(t210_amx24_tx, 0x57); 948MUX_ENUM_CTRL_DECL(t210_adx1_tx, 0x58); 949MUX_ENUM_CTRL_DECL(t210_adx2_tx, 0x59); 950MUX_ENUM_CTRL_DECL(t210_mixer11_tx, 0x20); 951MUX_ENUM_CTRL_DECL(t210_mixer12_tx, 0x21); 952MUX_ENUM_CTRL_DECL(t210_mixer13_tx, 0x22); 953MUX_ENUM_CTRL_DECL(t210_mixer14_tx, 0x23); 954MUX_ENUM_CTRL_DECL(t210_mixer15_tx, 0x24); 955MUX_ENUM_CTRL_DECL(t210_mixer16_tx, 0x25); 956MUX_ENUM_CTRL_DECL(t210_mixer17_tx, 0x26); 957MUX_ENUM_CTRL_DECL(t210_mixer18_tx, 0x27); 958MUX_ENUM_CTRL_DECL(t210_mixer19_tx, 0x28); 959MUX_ENUM_CTRL_DECL(t210_mixer110_tx, 0x29); 960MUX_ENUM_CTRL_DECL(t210_ope1_tx, 0x40); 961MUX_ENUM_CTRL_DECL(t210_ope2_tx, 0x41); 962 963/* Controls for t186 */ 964MUX_ENUM_CTRL_DECL_186(t186_admaif1_tx, 0x00); 965MUX_ENUM_CTRL_DECL_186(t186_admaif2_tx, 0x01); 966MUX_ENUM_CTRL_DECL_186(t186_admaif3_tx, 0x02); 967MUX_ENUM_CTRL_DECL_186(t186_admaif4_tx, 0x03); 968MUX_ENUM_CTRL_DECL_186(t186_admaif5_tx, 0x04); 969MUX_ENUM_CTRL_DECL_186(t186_admaif6_tx, 0x05); 970MUX_ENUM_CTRL_DECL_186(t186_admaif7_tx, 0x06); 971MUX_ENUM_CTRL_DECL_186(t186_admaif8_tx, 0x07); 972MUX_ENUM_CTRL_DECL_186(t186_admaif9_tx, 0x08); 973MUX_ENUM_CTRL_DECL_186(t186_admaif10_tx, 0x09); 974MUX_ENUM_CTRL_DECL_186(t186_i2s1_tx, 0x10); 975MUX_ENUM_CTRL_DECL_186(t186_i2s2_tx, 0x11); 976MUX_ENUM_CTRL_DECL_186(t186_i2s3_tx, 0x12); 977MUX_ENUM_CTRL_DECL_186(t186_i2s4_tx, 0x13); 978MUX_ENUM_CTRL_DECL_186(t186_i2s5_tx, 0x14); 979MUX_ENUM_CTRL_DECL_186(t186_admaif11_tx, 0x0a); 980MUX_ENUM_CTRL_DECL_186(t186_admaif12_tx, 0x0b); 981MUX_ENUM_CTRL_DECL_186(t186_admaif13_tx, 0x0c); 982MUX_ENUM_CTRL_DECL_186(t186_admaif14_tx, 0x0d); 983MUX_ENUM_CTRL_DECL_186(t186_admaif15_tx, 0x0e); 984MUX_ENUM_CTRL_DECL_186(t186_admaif16_tx, 0x0f); 985MUX_ENUM_CTRL_DECL_186(t186_i2s6_tx, 0x15); 986MUX_ENUM_CTRL_DECL_186(t186_dspk1_tx, 0x30); 987MUX_ENUM_CTRL_DECL_186(t186_dspk2_tx, 0x31); 988MUX_ENUM_CTRL_DECL_186(t186_admaif17_tx, 0x68); 989MUX_ENUM_CTRL_DECL_186(t186_admaif18_tx, 0x69); 990MUX_ENUM_CTRL_DECL_186(t186_admaif19_tx, 0x6a); 991MUX_ENUM_CTRL_DECL_186(t186_admaif20_tx, 0x6b); 992MUX_ENUM_CTRL_DECL_186(t186_sfc1_tx, 0x18); 993MUX_ENUM_CTRL_DECL_186(t186_sfc2_tx, 0x19); 994MUX_ENUM_CTRL_DECL_186(t186_sfc3_tx, 0x1a); 995MUX_ENUM_CTRL_DECL_186(t186_sfc4_tx, 0x1b); 996MUX_ENUM_CTRL_DECL_186(t186_mvc1_tx, 0x48); 997MUX_ENUM_CTRL_DECL_186(t186_mvc2_tx, 0x49); 998MUX_ENUM_CTRL_DECL_186(t186_amx11_tx, 0x50); 999MUX_ENUM_CTRL_DECL_186(t186_amx12_tx, 0x51); 1000MUX_ENUM_CTRL_DECL_186(t186_amx13_tx, 0x52); 1001MUX_ENUM_CTRL_DECL_186(t186_amx14_tx, 0x53); 1002MUX_ENUM_CTRL_DECL_186(t186_amx21_tx, 0x54); 1003MUX_ENUM_CTRL_DECL_186(t186_amx22_tx, 0x55); 1004MUX_ENUM_CTRL_DECL_186(t186_amx23_tx, 0x56); 1005MUX_ENUM_CTRL_DECL_186(t186_amx24_tx, 0x57); 1006MUX_ENUM_CTRL_DECL_186(t186_amx31_tx, 0x58); 1007MUX_ENUM_CTRL_DECL_186(t186_amx32_tx, 0x59); 1008MUX_ENUM_CTRL_DECL_186(t186_amx33_tx, 0x5a); 1009MUX_ENUM_CTRL_DECL_186(t186_amx34_tx, 0x5b); 1010MUX_ENUM_CTRL_DECL_186(t186_amx41_tx, 0x64); 1011MUX_ENUM_CTRL_DECL_186(t186_amx42_tx, 0x65); 1012MUX_ENUM_CTRL_DECL_186(t186_amx43_tx, 0x66); 1013MUX_ENUM_CTRL_DECL_186(t186_amx44_tx, 0x67); 1014MUX_ENUM_CTRL_DECL_186(t186_adx1_tx, 0x60); 1015MUX_ENUM_CTRL_DECL_186(t186_adx2_tx, 0x61); 1016MUX_ENUM_CTRL_DECL_186(t186_adx3_tx, 0x62); 1017MUX_ENUM_CTRL_DECL_186(t186_adx4_tx, 0x63); 1018MUX_ENUM_CTRL_DECL_186(t186_mixer11_tx, 0x20); 1019MUX_ENUM_CTRL_DECL_186(t186_mixer12_tx, 0x21); 1020MUX_ENUM_CTRL_DECL_186(t186_mixer13_tx, 0x22); 1021MUX_ENUM_CTRL_DECL_186(t186_mixer14_tx, 0x23); 1022MUX_ENUM_CTRL_DECL_186(t186_mixer15_tx, 0x24); 1023MUX_ENUM_CTRL_DECL_186(t186_mixer16_tx, 0x25); 1024MUX_ENUM_CTRL_DECL_186(t186_mixer17_tx, 0x26); 1025MUX_ENUM_CTRL_DECL_186(t186_mixer18_tx, 0x27); 1026MUX_ENUM_CTRL_DECL_186(t186_mixer19_tx, 0x28); 1027MUX_ENUM_CTRL_DECL_186(t186_mixer110_tx, 0x29); 1028MUX_ENUM_CTRL_DECL_186(t186_asrc11_tx, 0x6c); 1029MUX_ENUM_CTRL_DECL_186(t186_asrc12_tx, 0x6d); 1030MUX_ENUM_CTRL_DECL_186(t186_asrc13_tx, 0x6e); 1031MUX_ENUM_CTRL_DECL_186(t186_asrc14_tx, 0x6f); 1032MUX_ENUM_CTRL_DECL_186(t186_asrc15_tx, 0x70); 1033MUX_ENUM_CTRL_DECL_186(t186_asrc16_tx, 0x71); 1034MUX_ENUM_CTRL_DECL_186(t186_asrc17_tx, 0x72); 1035MUX_ENUM_CTRL_DECL_186(t186_ope1_tx, 0x40); 1036 1037/* Controls for t234 */ 1038MUX_ENUM_CTRL_DECL_234(t234_mvc1_tx, 0x44); 1039MUX_ENUM_CTRL_DECL_234(t234_mvc2_tx, 0x45); 1040MUX_ENUM_CTRL_DECL_234(t234_amx11_tx, 0x48); 1041MUX_ENUM_CTRL_DECL_234(t234_amx12_tx, 0x49); 1042MUX_ENUM_CTRL_DECL_234(t234_amx13_tx, 0x4a); 1043MUX_ENUM_CTRL_DECL_234(t234_amx14_tx, 0x4b); 1044MUX_ENUM_CTRL_DECL_234(t234_amx21_tx, 0x4c); 1045MUX_ENUM_CTRL_DECL_234(t234_amx22_tx, 0x4d); 1046MUX_ENUM_CTRL_DECL_234(t234_amx23_tx, 0x4e); 1047MUX_ENUM_CTRL_DECL_234(t234_amx24_tx, 0x4f); 1048MUX_ENUM_CTRL_DECL_234(t234_amx31_tx, 0x50); 1049MUX_ENUM_CTRL_DECL_234(t234_amx32_tx, 0x51); 1050MUX_ENUM_CTRL_DECL_234(t234_amx33_tx, 0x52); 1051MUX_ENUM_CTRL_DECL_234(t234_amx34_tx, 0x53); 1052MUX_ENUM_CTRL_DECL_234(t234_adx1_tx, 0x58); 1053MUX_ENUM_CTRL_DECL_234(t234_adx2_tx, 0x59); 1054MUX_ENUM_CTRL_DECL_234(t234_adx3_tx, 0x5a); 1055MUX_ENUM_CTRL_DECL_234(t234_adx4_tx, 0x5b); 1056MUX_ENUM_CTRL_DECL_234(t234_amx41_tx, 0x5c); 1057MUX_ENUM_CTRL_DECL_234(t234_amx42_tx, 0x5d); 1058MUX_ENUM_CTRL_DECL_234(t234_amx43_tx, 0x5e); 1059MUX_ENUM_CTRL_DECL_234(t234_amx44_tx, 0x5f); 1060MUX_ENUM_CTRL_DECL_234(t234_admaif17_tx, 0x60); 1061MUX_ENUM_CTRL_DECL_234(t234_admaif18_tx, 0x61); 1062MUX_ENUM_CTRL_DECL_234(t234_admaif19_tx, 0x62); 1063MUX_ENUM_CTRL_DECL_234(t234_admaif20_tx, 0x63); 1064MUX_ENUM_CTRL_DECL_234(t234_asrc11_tx, 0x64); 1065MUX_ENUM_CTRL_DECL_234(t234_asrc12_tx, 0x65); 1066MUX_ENUM_CTRL_DECL_234(t234_asrc13_tx, 0x66); 1067MUX_ENUM_CTRL_DECL_234(t234_asrc14_tx, 0x67); 1068MUX_ENUM_CTRL_DECL_234(t234_asrc15_tx, 0x68); 1069MUX_ENUM_CTRL_DECL_234(t234_asrc16_tx, 0x69); 1070MUX_ENUM_CTRL_DECL_234(t234_asrc17_tx, 0x6a); 1071 1072/* Controls for t264 */ 1073MUX_ENUM_CTRL_DECL_264(t264_admaif1_tx, 0x00); 1074MUX_ENUM_CTRL_DECL_264(t264_admaif2_tx, 0x01); 1075MUX_ENUM_CTRL_DECL_264(t264_admaif3_tx, 0x02); 1076MUX_ENUM_CTRL_DECL_264(t264_admaif4_tx, 0x03); 1077MUX_ENUM_CTRL_DECL_264(t264_admaif5_tx, 0x04); 1078MUX_ENUM_CTRL_DECL_264(t264_admaif6_tx, 0x05); 1079MUX_ENUM_CTRL_DECL_264(t264_admaif7_tx, 0x06); 1080MUX_ENUM_CTRL_DECL_264(t264_admaif8_tx, 0x07); 1081MUX_ENUM_CTRL_DECL_264(t264_admaif9_tx, 0x08); 1082MUX_ENUM_CTRL_DECL_264(t264_admaif10_tx, 0x09); 1083MUX_ENUM_CTRL_DECL_264(t264_admaif11_tx, 0x0a); 1084MUX_ENUM_CTRL_DECL_264(t264_admaif12_tx, 0x0b); 1085MUX_ENUM_CTRL_DECL_264(t264_admaif13_tx, 0x0c); 1086MUX_ENUM_CTRL_DECL_264(t264_admaif14_tx, 0x0d); 1087MUX_ENUM_CTRL_DECL_264(t264_admaif15_tx, 0x0e); 1088MUX_ENUM_CTRL_DECL_264(t264_admaif16_tx, 0x0f); 1089MUX_ENUM_CTRL_DECL_264(t264_i2s1_tx, 0x10); 1090MUX_ENUM_CTRL_DECL_264(t264_i2s2_tx, 0x11); 1091MUX_ENUM_CTRL_DECL_264(t264_i2s3_tx, 0x12); 1092MUX_ENUM_CTRL_DECL_264(t264_i2s4_tx, 0x13); 1093MUX_ENUM_CTRL_DECL_264(t264_i2s5_tx, 0x14); 1094MUX_ENUM_CTRL_DECL_264(t264_i2s6_tx, 0x15); 1095MUX_ENUM_CTRL_DECL_264(t264_i2s7_tx, 0x16); 1096MUX_ENUM_CTRL_DECL_264(t264_i2s8_tx, 0x17); 1097MUX_ENUM_CTRL_DECL_264(t264_sfc1_tx, 0x18); 1098MUX_ENUM_CTRL_DECL_264(t264_sfc2_tx, 0x19); 1099MUX_ENUM_CTRL_DECL_264(t264_sfc3_tx, 0x1a); 1100MUX_ENUM_CTRL_DECL_264(t264_sfc4_tx, 0x1b); 1101MUX_ENUM_CTRL_DECL_264(t264_mixer11_tx, 0x20); 1102MUX_ENUM_CTRL_DECL_264(t264_mixer12_tx, 0x21); 1103MUX_ENUM_CTRL_DECL_264(t264_mixer13_tx, 0x22); 1104MUX_ENUM_CTRL_DECL_264(t264_mixer14_tx, 0x23); 1105MUX_ENUM_CTRL_DECL_264(t264_mixer15_tx, 0x24); 1106MUX_ENUM_CTRL_DECL_264(t264_mixer16_tx, 0x25); 1107MUX_ENUM_CTRL_DECL_264(t264_mixer17_tx, 0x26); 1108MUX_ENUM_CTRL_DECL_264(t264_mixer18_tx, 0x27); 1109MUX_ENUM_CTRL_DECL_264(t264_mixer19_tx, 0x28); 1110MUX_ENUM_CTRL_DECL_264(t264_mixer110_tx, 0x29); 1111MUX_ENUM_CTRL_DECL_264(t264_dspk1_tx, 0x30); 1112MUX_ENUM_CTRL_DECL_264(t264_ope1_tx, 0x40); 1113MUX_ENUM_CTRL_DECL_264(t264_mvc1_tx, 0x44); 1114MUX_ENUM_CTRL_DECL_264(t264_mvc2_tx, 0x45); 1115MUX_ENUM_CTRL_DECL_264(t264_amx11_tx, 0x48); 1116MUX_ENUM_CTRL_DECL_264(t264_amx12_tx, 0x49); 1117MUX_ENUM_CTRL_DECL_264(t264_amx13_tx, 0x4a); 1118MUX_ENUM_CTRL_DECL_264(t264_amx14_tx, 0x4b); 1119MUX_ENUM_CTRL_DECL_264(t264_amx21_tx, 0x4c); 1120MUX_ENUM_CTRL_DECL_264(t264_amx22_tx, 0x4d); 1121MUX_ENUM_CTRL_DECL_264(t264_amx23_tx, 0x4e); 1122MUX_ENUM_CTRL_DECL_264(t264_amx24_tx, 0x4f); 1123MUX_ENUM_CTRL_DECL_264(t264_amx31_tx, 0x50); 1124MUX_ENUM_CTRL_DECL_264(t264_amx32_tx, 0x51); 1125MUX_ENUM_CTRL_DECL_264(t264_amx33_tx, 0x52); 1126MUX_ENUM_CTRL_DECL_264(t264_amx34_tx, 0x53); 1127MUX_ENUM_CTRL_DECL_264(t264_adx1_tx, 0x58); 1128MUX_ENUM_CTRL_DECL_264(t264_adx2_tx, 0x59); 1129MUX_ENUM_CTRL_DECL_264(t264_adx3_tx, 0x5a); 1130MUX_ENUM_CTRL_DECL_264(t264_adx4_tx, 0x5b); 1131MUX_ENUM_CTRL_DECL_264(t264_amx41_tx, 0x5c); 1132MUX_ENUM_CTRL_DECL_264(t264_amx42_tx, 0x5d); 1133MUX_ENUM_CTRL_DECL_264(t264_amx43_tx, 0x5e); 1134MUX_ENUM_CTRL_DECL_264(t264_amx44_tx, 0x5f); 1135MUX_ENUM_CTRL_DECL_264(t264_admaif17_tx, 0x60); 1136MUX_ENUM_CTRL_DECL_264(t264_admaif18_tx, 0x61); 1137MUX_ENUM_CTRL_DECL_264(t264_admaif19_tx, 0x62); 1138MUX_ENUM_CTRL_DECL_264(t264_admaif20_tx, 0x63); 1139MUX_ENUM_CTRL_DECL_264(t264_asrc11_tx, 0x64); 1140MUX_ENUM_CTRL_DECL_264(t264_asrc12_tx, 0x65); 1141MUX_ENUM_CTRL_DECL_264(t264_asrc13_tx, 0x66); 1142MUX_ENUM_CTRL_DECL_264(t264_asrc14_tx, 0x67); 1143MUX_ENUM_CTRL_DECL_264(t264_asrc15_tx, 0x68); 1144MUX_ENUM_CTRL_DECL_264(t264_asrc16_tx, 0x69); 1145MUX_ENUM_CTRL_DECL_264(t264_asrc17_tx, 0x6a); 1146MUX_ENUM_CTRL_DECL_264(t264_admaif21_tx, 0x74); 1147MUX_ENUM_CTRL_DECL_264(t264_admaif22_tx, 0x75); 1148MUX_ENUM_CTRL_DECL_264(t264_admaif23_tx, 0x76); 1149MUX_ENUM_CTRL_DECL_264(t264_admaif24_tx, 0x77); 1150MUX_ENUM_CTRL_DECL_264(t264_admaif25_tx, 0x78); 1151MUX_ENUM_CTRL_DECL_264(t264_admaif26_tx, 0x79); 1152MUX_ENUM_CTRL_DECL_264(t264_admaif27_tx, 0x7a); 1153MUX_ENUM_CTRL_DECL_264(t264_admaif28_tx, 0x7b); 1154MUX_ENUM_CTRL_DECL_264(t264_admaif29_tx, 0x7c); 1155MUX_ENUM_CTRL_DECL_264(t264_admaif30_tx, 0x7d); 1156MUX_ENUM_CTRL_DECL_264(t264_admaif31_tx, 0x7e); 1157MUX_ENUM_CTRL_DECL_264(t264_admaif32_tx, 0x7f); 1158MUX_ENUM_CTRL_DECL_264(t264_amx51_tx, 0x80); 1159MUX_ENUM_CTRL_DECL_264(t264_amx52_tx, 0x81); 1160MUX_ENUM_CTRL_DECL_264(t264_amx53_tx, 0x82); 1161MUX_ENUM_CTRL_DECL_264(t264_amx54_tx, 0x83); 1162MUX_ENUM_CTRL_DECL_264(t264_amx61_tx, 0x84); 1163MUX_ENUM_CTRL_DECL_264(t264_amx62_tx, 0x85); 1164MUX_ENUM_CTRL_DECL_264(t264_amx63_tx, 0x86); 1165MUX_ENUM_CTRL_DECL_264(t264_amx64_tx, 0x87); 1166MUX_ENUM_CTRL_DECL_264(t264_adx5_tx, 0x88); 1167MUX_ENUM_CTRL_DECL_264(t264_adx6_tx, 0x89); 1168 1169static const struct snd_soc_dapm_widget tegra210_ahub_widgets[] = { 1170 WIDGETS("ADMAIF1", t210_admaif1_tx), 1171 WIDGETS("ADMAIF2", t210_admaif2_tx), 1172 WIDGETS("ADMAIF3", t210_admaif3_tx), 1173 WIDGETS("ADMAIF4", t210_admaif4_tx), 1174 WIDGETS("ADMAIF5", t210_admaif5_tx), 1175 WIDGETS("ADMAIF6", t210_admaif6_tx), 1176 WIDGETS("ADMAIF7", t210_admaif7_tx), 1177 WIDGETS("ADMAIF8", t210_admaif8_tx), 1178 WIDGETS("ADMAIF9", t210_admaif9_tx), 1179 WIDGETS("ADMAIF10", t210_admaif10_tx), 1180 WIDGETS("I2S1", t210_i2s1_tx), 1181 WIDGETS("I2S2", t210_i2s2_tx), 1182 WIDGETS("I2S3", t210_i2s3_tx), 1183 WIDGETS("I2S4", t210_i2s4_tx), 1184 WIDGETS("I2S5", t210_i2s5_tx), 1185 TX_WIDGETS("DMIC1"), 1186 TX_WIDGETS("DMIC2"), 1187 TX_WIDGETS("DMIC3"), 1188 WIDGETS("SFC1", t210_sfc1_tx), 1189 WIDGETS("SFC2", t210_sfc2_tx), 1190 WIDGETS("SFC3", t210_sfc3_tx), 1191 WIDGETS("SFC4", t210_sfc4_tx), 1192 WIDGETS("MVC1", t210_mvc1_tx), 1193 WIDGETS("MVC2", t210_mvc2_tx), 1194 WIDGETS("AMX1 RX1", t210_amx11_tx), 1195 WIDGETS("AMX1 RX2", t210_amx12_tx), 1196 WIDGETS("AMX1 RX3", t210_amx13_tx), 1197 WIDGETS("AMX1 RX4", t210_amx14_tx), 1198 WIDGETS("AMX2 RX1", t210_amx21_tx), 1199 WIDGETS("AMX2 RX2", t210_amx22_tx), 1200 WIDGETS("AMX2 RX3", t210_amx23_tx), 1201 WIDGETS("AMX2 RX4", t210_amx24_tx), 1202 TX_WIDGETS("AMX1"), 1203 TX_WIDGETS("AMX2"), 1204 WIDGETS("ADX1", t210_adx1_tx), 1205 WIDGETS("ADX2", t210_adx2_tx), 1206 TX_WIDGETS("ADX1 TX1"), 1207 TX_WIDGETS("ADX1 TX2"), 1208 TX_WIDGETS("ADX1 TX3"), 1209 TX_WIDGETS("ADX1 TX4"), 1210 TX_WIDGETS("ADX2 TX1"), 1211 TX_WIDGETS("ADX2 TX2"), 1212 TX_WIDGETS("ADX2 TX3"), 1213 TX_WIDGETS("ADX2 TX4"), 1214 WIDGETS("MIXER1 RX1", t210_mixer11_tx), 1215 WIDGETS("MIXER1 RX2", t210_mixer12_tx), 1216 WIDGETS("MIXER1 RX3", t210_mixer13_tx), 1217 WIDGETS("MIXER1 RX4", t210_mixer14_tx), 1218 WIDGETS("MIXER1 RX5", t210_mixer15_tx), 1219 WIDGETS("MIXER1 RX6", t210_mixer16_tx), 1220 WIDGETS("MIXER1 RX7", t210_mixer17_tx), 1221 WIDGETS("MIXER1 RX8", t210_mixer18_tx), 1222 WIDGETS("MIXER1 RX9", t210_mixer19_tx), 1223 WIDGETS("MIXER1 RX10", t210_mixer110_tx), 1224 TX_WIDGETS("MIXER1 TX1"), 1225 TX_WIDGETS("MIXER1 TX2"), 1226 TX_WIDGETS("MIXER1 TX3"), 1227 TX_WIDGETS("MIXER1 TX4"), 1228 TX_WIDGETS("MIXER1 TX5"), 1229 WIDGETS("OPE1", t210_ope1_tx), 1230 WIDGETS("OPE2", t210_ope2_tx), 1231}; 1232 1233static const struct snd_soc_dapm_widget tegra186_ahub_widgets[] = { 1234 WIDGETS("ADMAIF1", t186_admaif1_tx), 1235 WIDGETS("ADMAIF2", t186_admaif2_tx), 1236 WIDGETS("ADMAIF3", t186_admaif3_tx), 1237 WIDGETS("ADMAIF4", t186_admaif4_tx), 1238 WIDGETS("ADMAIF5", t186_admaif5_tx), 1239 WIDGETS("ADMAIF6", t186_admaif6_tx), 1240 WIDGETS("ADMAIF7", t186_admaif7_tx), 1241 WIDGETS("ADMAIF8", t186_admaif8_tx), 1242 WIDGETS("ADMAIF9", t186_admaif9_tx), 1243 WIDGETS("ADMAIF10", t186_admaif10_tx), 1244 WIDGETS("ADMAIF11", t186_admaif11_tx), 1245 WIDGETS("ADMAIF12", t186_admaif12_tx), 1246 WIDGETS("ADMAIF13", t186_admaif13_tx), 1247 WIDGETS("ADMAIF14", t186_admaif14_tx), 1248 WIDGETS("ADMAIF15", t186_admaif15_tx), 1249 WIDGETS("ADMAIF16", t186_admaif16_tx), 1250 WIDGETS("ADMAIF17", t186_admaif17_tx), 1251 WIDGETS("ADMAIF18", t186_admaif18_tx), 1252 WIDGETS("ADMAIF19", t186_admaif19_tx), 1253 WIDGETS("ADMAIF20", t186_admaif20_tx), 1254 WIDGETS("I2S1", t186_i2s1_tx), 1255 WIDGETS("I2S2", t186_i2s2_tx), 1256 WIDGETS("I2S3", t186_i2s3_tx), 1257 WIDGETS("I2S4", t186_i2s4_tx), 1258 WIDGETS("I2S5", t186_i2s5_tx), 1259 WIDGETS("I2S6", t186_i2s6_tx), 1260 TX_WIDGETS("DMIC1"), 1261 TX_WIDGETS("DMIC2"), 1262 TX_WIDGETS("DMIC3"), 1263 TX_WIDGETS("DMIC4"), 1264 WIDGETS("DSPK1", t186_dspk1_tx), 1265 WIDGETS("DSPK2", t186_dspk2_tx), 1266 WIDGETS("SFC1", t186_sfc1_tx), 1267 WIDGETS("SFC2", t186_sfc2_tx), 1268 WIDGETS("SFC3", t186_sfc3_tx), 1269 WIDGETS("SFC4", t186_sfc4_tx), 1270 WIDGETS("MVC1", t186_mvc1_tx), 1271 WIDGETS("MVC2", t186_mvc2_tx), 1272 WIDGETS("AMX1 RX1", t186_amx11_tx), 1273 WIDGETS("AMX1 RX2", t186_amx12_tx), 1274 WIDGETS("AMX1 RX3", t186_amx13_tx), 1275 WIDGETS("AMX1 RX4", t186_amx14_tx), 1276 WIDGETS("AMX2 RX1", t186_amx21_tx), 1277 WIDGETS("AMX2 RX2", t186_amx22_tx), 1278 WIDGETS("AMX2 RX3", t186_amx23_tx), 1279 WIDGETS("AMX2 RX4", t186_amx24_tx), 1280 WIDGETS("AMX3 RX1", t186_amx31_tx), 1281 WIDGETS("AMX3 RX2", t186_amx32_tx), 1282 WIDGETS("AMX3 RX3", t186_amx33_tx), 1283 WIDGETS("AMX3 RX4", t186_amx34_tx), 1284 WIDGETS("AMX4 RX1", t186_amx41_tx), 1285 WIDGETS("AMX4 RX2", t186_amx42_tx), 1286 WIDGETS("AMX4 RX3", t186_amx43_tx), 1287 WIDGETS("AMX4 RX4", t186_amx44_tx), 1288 TX_WIDGETS("AMX1"), 1289 TX_WIDGETS("AMX2"), 1290 TX_WIDGETS("AMX3"), 1291 TX_WIDGETS("AMX4"), 1292 WIDGETS("ADX1", t186_adx1_tx), 1293 WIDGETS("ADX2", t186_adx2_tx), 1294 WIDGETS("ADX3", t186_adx3_tx), 1295 WIDGETS("ADX4", t186_adx4_tx), 1296 TX_WIDGETS("ADX1 TX1"), 1297 TX_WIDGETS("ADX1 TX2"), 1298 TX_WIDGETS("ADX1 TX3"), 1299 TX_WIDGETS("ADX1 TX4"), 1300 TX_WIDGETS("ADX2 TX1"), 1301 TX_WIDGETS("ADX2 TX2"), 1302 TX_WIDGETS("ADX2 TX3"), 1303 TX_WIDGETS("ADX2 TX4"), 1304 TX_WIDGETS("ADX3 TX1"), 1305 TX_WIDGETS("ADX3 TX2"), 1306 TX_WIDGETS("ADX3 TX3"), 1307 TX_WIDGETS("ADX3 TX4"), 1308 TX_WIDGETS("ADX4 TX1"), 1309 TX_WIDGETS("ADX4 TX2"), 1310 TX_WIDGETS("ADX4 TX3"), 1311 TX_WIDGETS("ADX4 TX4"), 1312 WIDGETS("MIXER1 RX1", t186_mixer11_tx), 1313 WIDGETS("MIXER1 RX2", t186_mixer12_tx), 1314 WIDGETS("MIXER1 RX3", t186_mixer13_tx), 1315 WIDGETS("MIXER1 RX4", t186_mixer14_tx), 1316 WIDGETS("MIXER1 RX5", t186_mixer15_tx), 1317 WIDGETS("MIXER1 RX6", t186_mixer16_tx), 1318 WIDGETS("MIXER1 RX7", t186_mixer17_tx), 1319 WIDGETS("MIXER1 RX8", t186_mixer18_tx), 1320 WIDGETS("MIXER1 RX9", t186_mixer19_tx), 1321 WIDGETS("MIXER1 RX10", t186_mixer110_tx), 1322 TX_WIDGETS("MIXER1 TX1"), 1323 TX_WIDGETS("MIXER1 TX2"), 1324 TX_WIDGETS("MIXER1 TX3"), 1325 TX_WIDGETS("MIXER1 TX4"), 1326 TX_WIDGETS("MIXER1 TX5"), 1327 WIDGETS("ASRC1 RX1", t186_asrc11_tx), 1328 WIDGETS("ASRC1 RX2", t186_asrc12_tx), 1329 WIDGETS("ASRC1 RX3", t186_asrc13_tx), 1330 WIDGETS("ASRC1 RX4", t186_asrc14_tx), 1331 WIDGETS("ASRC1 RX5", t186_asrc15_tx), 1332 WIDGETS("ASRC1 RX6", t186_asrc16_tx), 1333 WIDGETS("ASRC1 RX7", t186_asrc17_tx), 1334 TX_WIDGETS("ASRC1 TX1"), 1335 TX_WIDGETS("ASRC1 TX2"), 1336 TX_WIDGETS("ASRC1 TX3"), 1337 TX_WIDGETS("ASRC1 TX4"), 1338 TX_WIDGETS("ASRC1 TX5"), 1339 TX_WIDGETS("ASRC1 TX6"), 1340 WIDGETS("OPE1", t186_ope1_tx), 1341}; 1342 1343static const struct snd_soc_dapm_widget tegra234_ahub_widgets[] = { 1344 WIDGETS("ADMAIF1", t186_admaif1_tx), 1345 WIDGETS("ADMAIF2", t186_admaif2_tx), 1346 WIDGETS("ADMAIF3", t186_admaif3_tx), 1347 WIDGETS("ADMAIF4", t186_admaif4_tx), 1348 WIDGETS("ADMAIF5", t186_admaif5_tx), 1349 WIDGETS("ADMAIF6", t186_admaif6_tx), 1350 WIDGETS("ADMAIF7", t186_admaif7_tx), 1351 WIDGETS("ADMAIF8", t186_admaif8_tx), 1352 WIDGETS("ADMAIF9", t186_admaif9_tx), 1353 WIDGETS("ADMAIF10", t186_admaif10_tx), 1354 WIDGETS("ADMAIF11", t186_admaif11_tx), 1355 WIDGETS("ADMAIF12", t186_admaif12_tx), 1356 WIDGETS("ADMAIF13", t186_admaif13_tx), 1357 WIDGETS("ADMAIF14", t186_admaif14_tx), 1358 WIDGETS("ADMAIF15", t186_admaif15_tx), 1359 WIDGETS("ADMAIF16", t186_admaif16_tx), 1360 WIDGETS("ADMAIF17", t234_admaif17_tx), 1361 WIDGETS("ADMAIF18", t234_admaif18_tx), 1362 WIDGETS("ADMAIF19", t234_admaif19_tx), 1363 WIDGETS("ADMAIF20", t234_admaif20_tx), 1364 WIDGETS("I2S1", t186_i2s1_tx), 1365 WIDGETS("I2S2", t186_i2s2_tx), 1366 WIDGETS("I2S3", t186_i2s3_tx), 1367 WIDGETS("I2S4", t186_i2s4_tx), 1368 WIDGETS("I2S5", t186_i2s5_tx), 1369 WIDGETS("I2S6", t186_i2s6_tx), 1370 TX_WIDGETS("DMIC1"), 1371 TX_WIDGETS("DMIC2"), 1372 TX_WIDGETS("DMIC3"), 1373 TX_WIDGETS("DMIC4"), 1374 WIDGETS("DSPK1", t186_dspk1_tx), 1375 WIDGETS("DSPK2", t186_dspk2_tx), 1376 WIDGETS("SFC1", t186_sfc1_tx), 1377 WIDGETS("SFC2", t186_sfc2_tx), 1378 WIDGETS("SFC3", t186_sfc3_tx), 1379 WIDGETS("SFC4", t186_sfc4_tx), 1380 WIDGETS("MVC1", t234_mvc1_tx), 1381 WIDGETS("MVC2", t234_mvc2_tx), 1382 WIDGETS("AMX1 RX1", t234_amx11_tx), 1383 WIDGETS("AMX1 RX2", t234_amx12_tx), 1384 WIDGETS("AMX1 RX3", t234_amx13_tx), 1385 WIDGETS("AMX1 RX4", t234_amx14_tx), 1386 WIDGETS("AMX2 RX1", t234_amx21_tx), 1387 WIDGETS("AMX2 RX2", t234_amx22_tx), 1388 WIDGETS("AMX2 RX3", t234_amx23_tx), 1389 WIDGETS("AMX2 RX4", t234_amx24_tx), 1390 WIDGETS("AMX3 RX1", t234_amx31_tx), 1391 WIDGETS("AMX3 RX2", t234_amx32_tx), 1392 WIDGETS("AMX3 RX3", t234_amx33_tx), 1393 WIDGETS("AMX3 RX4", t234_amx34_tx), 1394 WIDGETS("AMX4 RX1", t234_amx41_tx), 1395 WIDGETS("AMX4 RX2", t234_amx42_tx), 1396 WIDGETS("AMX4 RX3", t234_amx43_tx), 1397 WIDGETS("AMX4 RX4", t234_amx44_tx), 1398 TX_WIDGETS("AMX1"), 1399 TX_WIDGETS("AMX2"), 1400 TX_WIDGETS("AMX3"), 1401 TX_WIDGETS("AMX4"), 1402 WIDGETS("ADX1", t234_adx1_tx), 1403 WIDGETS("ADX2", t234_adx2_tx), 1404 WIDGETS("ADX3", t234_adx3_tx), 1405 WIDGETS("ADX4", t234_adx4_tx), 1406 TX_WIDGETS("ADX1 TX1"), 1407 TX_WIDGETS("ADX1 TX2"), 1408 TX_WIDGETS("ADX1 TX3"), 1409 TX_WIDGETS("ADX1 TX4"), 1410 TX_WIDGETS("ADX2 TX1"), 1411 TX_WIDGETS("ADX2 TX2"), 1412 TX_WIDGETS("ADX2 TX3"), 1413 TX_WIDGETS("ADX2 TX4"), 1414 TX_WIDGETS("ADX3 TX1"), 1415 TX_WIDGETS("ADX3 TX2"), 1416 TX_WIDGETS("ADX3 TX3"), 1417 TX_WIDGETS("ADX3 TX4"), 1418 TX_WIDGETS("ADX4 TX1"), 1419 TX_WIDGETS("ADX4 TX2"), 1420 TX_WIDGETS("ADX4 TX3"), 1421 TX_WIDGETS("ADX4 TX4"), 1422 WIDGETS("MIXER1 RX1", t186_mixer11_tx), 1423 WIDGETS("MIXER1 RX2", t186_mixer12_tx), 1424 WIDGETS("MIXER1 RX3", t186_mixer13_tx), 1425 WIDGETS("MIXER1 RX4", t186_mixer14_tx), 1426 WIDGETS("MIXER1 RX5", t186_mixer15_tx), 1427 WIDGETS("MIXER1 RX6", t186_mixer16_tx), 1428 WIDGETS("MIXER1 RX7", t186_mixer17_tx), 1429 WIDGETS("MIXER1 RX8", t186_mixer18_tx), 1430 WIDGETS("MIXER1 RX9", t186_mixer19_tx), 1431 WIDGETS("MIXER1 RX10", t186_mixer110_tx), 1432 TX_WIDGETS("MIXER1 TX1"), 1433 TX_WIDGETS("MIXER1 TX2"), 1434 TX_WIDGETS("MIXER1 TX3"), 1435 TX_WIDGETS("MIXER1 TX4"), 1436 TX_WIDGETS("MIXER1 TX5"), 1437 WIDGETS("ASRC1 RX1", t234_asrc11_tx), 1438 WIDGETS("ASRC1 RX2", t234_asrc12_tx), 1439 WIDGETS("ASRC1 RX3", t234_asrc13_tx), 1440 WIDGETS("ASRC1 RX4", t234_asrc14_tx), 1441 WIDGETS("ASRC1 RX5", t234_asrc15_tx), 1442 WIDGETS("ASRC1 RX6", t234_asrc16_tx), 1443 WIDGETS("ASRC1 RX7", t234_asrc17_tx), 1444 TX_WIDGETS("ASRC1 TX1"), 1445 TX_WIDGETS("ASRC1 TX2"), 1446 TX_WIDGETS("ASRC1 TX3"), 1447 TX_WIDGETS("ASRC1 TX4"), 1448 TX_WIDGETS("ASRC1 TX5"), 1449 TX_WIDGETS("ASRC1 TX6"), 1450 WIDGETS("OPE1", t186_ope1_tx), 1451}; 1452 1453static const struct snd_soc_dapm_widget tegra264_ahub_widgets[] = { 1454 WIDGETS("ADMAIF1", t264_admaif1_tx), 1455 WIDGETS("ADMAIF2", t264_admaif2_tx), 1456 WIDGETS("ADMAIF3", t264_admaif3_tx), 1457 WIDGETS("ADMAIF4", t264_admaif4_tx), 1458 WIDGETS("ADMAIF5", t264_admaif5_tx), 1459 WIDGETS("ADMAIF6", t264_admaif6_tx), 1460 WIDGETS("ADMAIF7", t264_admaif7_tx), 1461 WIDGETS("ADMAIF8", t264_admaif8_tx), 1462 WIDGETS("ADMAIF9", t264_admaif9_tx), 1463 WIDGETS("ADMAIF10", t264_admaif10_tx), 1464 WIDGETS("ADMAIF11", t264_admaif11_tx), 1465 WIDGETS("ADMAIF12", t264_admaif12_tx), 1466 WIDGETS("ADMAIF13", t264_admaif13_tx), 1467 WIDGETS("ADMAIF14", t264_admaif14_tx), 1468 WIDGETS("ADMAIF15", t264_admaif15_tx), 1469 WIDGETS("ADMAIF16", t264_admaif16_tx), 1470 WIDGETS("ADMAIF17", t264_admaif17_tx), 1471 WIDGETS("ADMAIF18", t264_admaif18_tx), 1472 WIDGETS("ADMAIF19", t264_admaif19_tx), 1473 WIDGETS("ADMAIF20", t264_admaif20_tx), 1474 WIDGETS("ADMAIF21", t264_admaif21_tx), 1475 WIDGETS("ADMAIF22", t264_admaif22_tx), 1476 WIDGETS("ADMAIF23", t264_admaif23_tx), 1477 WIDGETS("ADMAIF24", t264_admaif24_tx), 1478 WIDGETS("ADMAIF25", t264_admaif25_tx), 1479 WIDGETS("ADMAIF26", t264_admaif26_tx), 1480 WIDGETS("ADMAIF27", t264_admaif27_tx), 1481 WIDGETS("ADMAIF28", t264_admaif28_tx), 1482 WIDGETS("ADMAIF29", t264_admaif29_tx), 1483 WIDGETS("ADMAIF30", t264_admaif30_tx), 1484 WIDGETS("ADMAIF31", t264_admaif31_tx), 1485 WIDGETS("ADMAIF32", t264_admaif32_tx), 1486 WIDGETS("I2S1", t264_i2s1_tx), 1487 WIDGETS("I2S2", t264_i2s2_tx), 1488 WIDGETS("I2S3", t264_i2s3_tx), 1489 WIDGETS("I2S4", t264_i2s4_tx), 1490 WIDGETS("I2S5", t264_i2s5_tx), 1491 WIDGETS("I2S6", t264_i2s6_tx), 1492 WIDGETS("I2S7", t264_i2s7_tx), 1493 WIDGETS("I2S8", t264_i2s8_tx), 1494 TX_WIDGETS("DMIC1"), 1495 TX_WIDGETS("DMIC2"), 1496 WIDGETS("DSPK1", t264_dspk1_tx), 1497 WIDGETS("SFC1", t264_sfc1_tx), 1498 WIDGETS("SFC2", t264_sfc2_tx), 1499 WIDGETS("SFC3", t264_sfc3_tx), 1500 WIDGETS("SFC4", t264_sfc4_tx), 1501 WIDGETS("MVC1", t264_mvc1_tx), 1502 WIDGETS("MVC2", t264_mvc2_tx), 1503 WIDGETS("AMX1 RX1", t264_amx11_tx), 1504 WIDGETS("AMX1 RX2", t264_amx12_tx), 1505 WIDGETS("AMX1 RX3", t264_amx13_tx), 1506 WIDGETS("AMX1 RX4", t264_amx14_tx), 1507 WIDGETS("AMX2 RX1", t264_amx21_tx), 1508 WIDGETS("AMX2 RX2", t264_amx22_tx), 1509 WIDGETS("AMX2 RX3", t264_amx23_tx), 1510 WIDGETS("AMX2 RX4", t264_amx24_tx), 1511 WIDGETS("AMX3 RX1", t264_amx31_tx), 1512 WIDGETS("AMX3 RX2", t264_amx32_tx), 1513 WIDGETS("AMX3 RX3", t264_amx33_tx), 1514 WIDGETS("AMX3 RX4", t264_amx34_tx), 1515 WIDGETS("AMX4 RX1", t264_amx41_tx), 1516 WIDGETS("AMX4 RX2", t264_amx42_tx), 1517 WIDGETS("AMX4 RX3", t264_amx43_tx), 1518 WIDGETS("AMX4 RX4", t264_amx44_tx), 1519 WIDGETS("AMX5 RX1", t264_amx51_tx), 1520 WIDGETS("AMX5 RX2", t264_amx52_tx), 1521 WIDGETS("AMX5 RX3", t264_amx53_tx), 1522 WIDGETS("AMX5 RX4", t264_amx54_tx), 1523 WIDGETS("AMX6 RX1", t264_amx61_tx), 1524 WIDGETS("AMX6 RX2", t264_amx62_tx), 1525 WIDGETS("AMX6 RX3", t264_amx63_tx), 1526 WIDGETS("AMX6 RX4", t264_amx64_tx), 1527 TX_WIDGETS("AMX1"), 1528 TX_WIDGETS("AMX2"), 1529 TX_WIDGETS("AMX3"), 1530 TX_WIDGETS("AMX4"), 1531 TX_WIDGETS("AMX5"), 1532 TX_WIDGETS("AMX6"), 1533 WIDGETS("ADX1", t264_adx1_tx), 1534 WIDGETS("ADX2", t264_adx2_tx), 1535 WIDGETS("ADX3", t264_adx3_tx), 1536 WIDGETS("ADX4", t264_adx4_tx), 1537 WIDGETS("ADX5", t264_adx5_tx), 1538 WIDGETS("ADX6", t264_adx6_tx), 1539 TX_WIDGETS("ADX1 TX1"), 1540 TX_WIDGETS("ADX1 TX2"), 1541 TX_WIDGETS("ADX1 TX3"), 1542 TX_WIDGETS("ADX1 TX4"), 1543 TX_WIDGETS("ADX2 TX1"), 1544 TX_WIDGETS("ADX2 TX2"), 1545 TX_WIDGETS("ADX2 TX3"), 1546 TX_WIDGETS("ADX2 TX4"), 1547 TX_WIDGETS("ADX3 TX1"), 1548 TX_WIDGETS("ADX3 TX2"), 1549 TX_WIDGETS("ADX3 TX3"), 1550 TX_WIDGETS("ADX3 TX4"), 1551 TX_WIDGETS("ADX4 TX1"), 1552 TX_WIDGETS("ADX4 TX2"), 1553 TX_WIDGETS("ADX4 TX3"), 1554 TX_WIDGETS("ADX4 TX4"), 1555 TX_WIDGETS("ADX5 TX1"), 1556 TX_WIDGETS("ADX5 TX2"), 1557 TX_WIDGETS("ADX5 TX3"), 1558 TX_WIDGETS("ADX5 TX4"), 1559 TX_WIDGETS("ADX6 TX1"), 1560 TX_WIDGETS("ADX6 TX2"), 1561 TX_WIDGETS("ADX6 TX3"), 1562 TX_WIDGETS("ADX6 TX4"), 1563 WIDGETS("MIXER1 RX1", t264_mixer11_tx), 1564 WIDGETS("MIXER1 RX2", t264_mixer12_tx), 1565 WIDGETS("MIXER1 RX3", t264_mixer13_tx), 1566 WIDGETS("MIXER1 RX4", t264_mixer14_tx), 1567 WIDGETS("MIXER1 RX5", t264_mixer15_tx), 1568 WIDGETS("MIXER1 RX6", t264_mixer16_tx), 1569 WIDGETS("MIXER1 RX7", t264_mixer17_tx), 1570 WIDGETS("MIXER1 RX8", t264_mixer18_tx), 1571 WIDGETS("MIXER1 RX9", t264_mixer19_tx), 1572 WIDGETS("MIXER1 RX10", t264_mixer110_tx), 1573 TX_WIDGETS("MIXER1 TX1"), 1574 TX_WIDGETS("MIXER1 TX2"), 1575 TX_WIDGETS("MIXER1 TX3"), 1576 TX_WIDGETS("MIXER1 TX4"), 1577 TX_WIDGETS("MIXER1 TX5"), 1578 WIDGETS("ASRC1 RX1", t264_asrc11_tx), 1579 WIDGETS("ASRC1 RX2", t264_asrc12_tx), 1580 WIDGETS("ASRC1 RX3", t264_asrc13_tx), 1581 WIDGETS("ASRC1 RX4", t264_asrc14_tx), 1582 WIDGETS("ASRC1 RX5", t264_asrc15_tx), 1583 WIDGETS("ASRC1 RX6", t264_asrc16_tx), 1584 WIDGETS("ASRC1 RX7", t264_asrc17_tx), 1585 TX_WIDGETS("ASRC1 TX1"), 1586 TX_WIDGETS("ASRC1 TX2"), 1587 TX_WIDGETS("ASRC1 TX3"), 1588 TX_WIDGETS("ASRC1 TX4"), 1589 TX_WIDGETS("ASRC1 TX5"), 1590 TX_WIDGETS("ASRC1 TX6"), 1591 WIDGETS("OPE1", t264_ope1_tx), 1592}; 1593 1594#define TEGRA_COMMON_MUX_ROUTES(name) \ 1595 { name " XBAR-TX", NULL, name " Mux" }, \ 1596 { name " Mux", "ADMAIF1", "ADMAIF1 XBAR-RX" }, \ 1597 { name " Mux", "ADMAIF2", "ADMAIF2 XBAR-RX" }, \ 1598 { name " Mux", "ADMAIF3", "ADMAIF3 XBAR-RX" }, \ 1599 { name " Mux", "ADMAIF4", "ADMAIF4 XBAR-RX" }, \ 1600 { name " Mux", "ADMAIF5", "ADMAIF5 XBAR-RX" }, \ 1601 { name " Mux", "ADMAIF6", "ADMAIF6 XBAR-RX" }, \ 1602 { name " Mux", "ADMAIF7", "ADMAIF7 XBAR-RX" }, \ 1603 { name " Mux", "ADMAIF8", "ADMAIF8 XBAR-RX" }, \ 1604 { name " Mux", "ADMAIF9", "ADMAIF9 XBAR-RX" }, \ 1605 { name " Mux", "ADMAIF10", "ADMAIF10 XBAR-RX" }, \ 1606 { name " Mux", "I2S1", "I2S1 XBAR-RX" }, \ 1607 { name " Mux", "I2S2", "I2S2 XBAR-RX" }, \ 1608 { name " Mux", "I2S3", "I2S3 XBAR-RX" }, \ 1609 { name " Mux", "I2S4", "I2S4 XBAR-RX" }, \ 1610 { name " Mux", "I2S5", "I2S5 XBAR-RX" }, \ 1611 { name " Mux", "DMIC1", "DMIC1 XBAR-RX" }, \ 1612 { name " Mux", "DMIC2", "DMIC2 XBAR-RX" }, \ 1613 { name " Mux", "SFC1", "SFC1 XBAR-RX" }, \ 1614 { name " Mux", "SFC2", "SFC2 XBAR-RX" }, \ 1615 { name " Mux", "SFC3", "SFC3 XBAR-RX" }, \ 1616 { name " Mux", "SFC4", "SFC4 XBAR-RX" }, \ 1617 { name " Mux", "MVC1", "MVC1 XBAR-RX" }, \ 1618 { name " Mux", "MVC2", "MVC2 XBAR-RX" }, \ 1619 { name " Mux", "AMX1", "AMX1 XBAR-RX" }, \ 1620 { name " Mux", "AMX2", "AMX2 XBAR-RX" }, \ 1621 { name " Mux", "ADX1 TX1", "ADX1 TX1 XBAR-RX" }, \ 1622 { name " Mux", "ADX1 TX2", "ADX1 TX2 XBAR-RX" }, \ 1623 { name " Mux", "ADX1 TX3", "ADX1 TX3 XBAR-RX" }, \ 1624 { name " Mux", "ADX1 TX4", "ADX1 TX4 XBAR-RX" }, \ 1625 { name " Mux", "ADX2 TX1", "ADX2 TX1 XBAR-RX" }, \ 1626 { name " Mux", "ADX2 TX2", "ADX2 TX2 XBAR-RX" }, \ 1627 { name " Mux", "ADX2 TX3", "ADX2 TX3 XBAR-RX" }, \ 1628 { name " Mux", "ADX2 TX4", "ADX2 TX4 XBAR-RX" }, \ 1629 { name " Mux", "MIXER1 TX1", "MIXER1 TX1 XBAR-RX" }, \ 1630 { name " Mux", "MIXER1 TX2", "MIXER1 TX2 XBAR-RX" }, \ 1631 { name " Mux", "MIXER1 TX3", "MIXER1 TX3 XBAR-RX" }, \ 1632 { name " Mux", "MIXER1 TX4", "MIXER1 TX4 XBAR-RX" }, \ 1633 { name " Mux", "MIXER1 TX5", "MIXER1 TX5 XBAR-RX" }, \ 1634 { name " Mux", "OPE1", "OPE1 XBAR-RX" }, 1635 1636#define TEGRA210_ONLY_MUX_ROUTES(name) \ 1637 { name " Mux", "DMIC3", "DMIC3 XBAR-RX" }, \ 1638 { name " Mux", "OPE2", "OPE2 XBAR-RX" }, 1639 1640#define TEGRA186_ONLY_MUX_ROUTES(name) \ 1641 { name " Mux", "ADMAIF11", "ADMAIF11 XBAR-RX" }, \ 1642 { name " Mux", "ADMAIF12", "ADMAIF12 XBAR-RX" }, \ 1643 { name " Mux", "ADMAIF13", "ADMAIF13 XBAR-RX" }, \ 1644 { name " Mux", "ADMAIF14", "ADMAIF14 XBAR-RX" }, \ 1645 { name " Mux", "ADMAIF15", "ADMAIF15 XBAR-RX" }, \ 1646 { name " Mux", "ADMAIF16", "ADMAIF16 XBAR-RX" }, \ 1647 { name " Mux", "ADMAIF17", "ADMAIF17 XBAR-RX" }, \ 1648 { name " Mux", "ADMAIF18", "ADMAIF18 XBAR-RX" }, \ 1649 { name " Mux", "ADMAIF19", "ADMAIF19 XBAR-RX" }, \ 1650 { name " Mux", "ADMAIF20", "ADMAIF20 XBAR-RX" }, \ 1651 { name " Mux", "I2S6", "I2S6 XBAR-RX" }, \ 1652 { name " Mux", "DMIC3", "DMIC3 XBAR-RX" }, \ 1653 { name " Mux", "DMIC4", "DMIC4 XBAR-RX" }, \ 1654 { name " Mux", "AMX3", "AMX3 XBAR-RX" }, \ 1655 { name " Mux", "AMX4", "AMX4 XBAR-RX" }, \ 1656 { name " Mux", "ADX3 TX1", "ADX3 TX1 XBAR-RX" }, \ 1657 { name " Mux", "ADX3 TX2", "ADX3 TX2 XBAR-RX" }, \ 1658 { name " Mux", "ADX3 TX3", "ADX3 TX3 XBAR-RX" }, \ 1659 { name " Mux", "ADX3 TX4", "ADX3 TX4 XBAR-RX" }, \ 1660 { name " Mux", "ADX4 TX1", "ADX4 TX1 XBAR-RX" }, \ 1661 { name " Mux", "ADX4 TX2", "ADX4 TX2 XBAR-RX" }, \ 1662 { name " Mux", "ADX4 TX3", "ADX4 TX3 XBAR-RX" }, \ 1663 { name " Mux", "ADX4 TX4", "ADX4 TX4 XBAR-RX" }, \ 1664 { name " Mux", "ASRC1 TX1", "ASRC1 TX1 XBAR-RX" }, \ 1665 { name " Mux", "ASRC1 TX2", "ASRC1 TX2 XBAR-RX" }, \ 1666 { name " Mux", "ASRC1 TX3", "ASRC1 TX3 XBAR-RX" }, \ 1667 { name " Mux", "ASRC1 TX4", "ASRC1 TX4 XBAR-RX" }, \ 1668 { name " Mux", "ASRC1 TX5", "ASRC1 TX5 XBAR-RX" }, \ 1669 { name " Mux", "ASRC1 TX6", "ASRC1 TX6 XBAR-RX" }, 1670 1671#define TEGRA264_ONLY_MUX_ROUTES(name) \ 1672 { name " Mux", "ADMAIF11", "ADMAIF11 XBAR-RX" }, \ 1673 { name " Mux", "ADMAIF12", "ADMAIF12 XBAR-RX" }, \ 1674 { name " Mux", "ADMAIF13", "ADMAIF13 XBAR-RX" }, \ 1675 { name " Mux", "ADMAIF14", "ADMAIF14 XBAR-RX" }, \ 1676 { name " Mux", "ADMAIF15", "ADMAIF15 XBAR-RX" }, \ 1677 { name " Mux", "ADMAIF16", "ADMAIF16 XBAR-RX" }, \ 1678 { name " Mux", "ADMAIF17", "ADMAIF17 XBAR-RX" }, \ 1679 { name " Mux", "ADMAIF18", "ADMAIF18 XBAR-RX" }, \ 1680 { name " Mux", "ADMAIF19", "ADMAIF19 XBAR-RX" }, \ 1681 { name " Mux", "ADMAIF20", "ADMAIF20 XBAR-RX" }, \ 1682 { name " Mux", "ADMAIF21", "ADMAIF21 XBAR-RX" }, \ 1683 { name " Mux", "ADMAIF22", "ADMAIF22 XBAR-RX" }, \ 1684 { name " Mux", "ADMAIF23", "ADMAIF23 XBAR-RX" }, \ 1685 { name " Mux", "ADMAIF24", "ADMAIF24 XBAR-RX" }, \ 1686 { name " Mux", "ADMAIF25", "ADMAIF25 XBAR-RX" }, \ 1687 { name " Mux", "ADMAIF26", "ADMAIF26 XBAR-RX" }, \ 1688 { name " Mux", "ADMAIF27", "ADMAIF27 XBAR-RX" }, \ 1689 { name " Mux", "ADMAIF28", "ADMAIF28 XBAR-RX" }, \ 1690 { name " Mux", "ADMAIF29", "ADMAIF29 XBAR-RX" }, \ 1691 { name " Mux", "ADMAIF30", "ADMAIF30 XBAR-RX" }, \ 1692 { name " Mux", "ADMAIF31", "ADMAIF31 XBAR-RX" }, \ 1693 { name " Mux", "ADMAIF32", "ADMAIF32 XBAR-RX" }, \ 1694 { name " Mux", "I2S6", "I2S6 XBAR-RX" }, \ 1695 { name " Mux", "I2S7", "I2S7 XBAR-RX" }, \ 1696 { name " Mux", "I2S8", "I2S8 XBAR-RX" }, \ 1697 { name " Mux", "AMX3", "AMX3 XBAR-RX" }, \ 1698 { name " Mux", "AMX4", "AMX4 XBAR-RX" }, \ 1699 { name " Mux", "AMX5", "AMX5 XBAR-RX" }, \ 1700 { name " Mux", "AMX6", "AMX6 XBAR-RX" }, \ 1701 { name " Mux", "ADX3 TX1", "ADX3 TX1 XBAR-RX" }, \ 1702 { name " Mux", "ADX3 TX2", "ADX3 TX2 XBAR-RX" }, \ 1703 { name " Mux", "ADX3 TX3", "ADX3 TX3 XBAR-RX" }, \ 1704 { name " Mux", "ADX3 TX4", "ADX3 TX4 XBAR-RX" }, \ 1705 { name " Mux", "ADX4 TX1", "ADX4 TX1 XBAR-RX" }, \ 1706 { name " Mux", "ADX4 TX2", "ADX4 TX2 XBAR-RX" }, \ 1707 { name " Mux", "ADX4 TX3", "ADX4 TX3 XBAR-RX" }, \ 1708 { name " Mux", "ADX4 TX4", "ADX4 TX4 XBAR-RX" }, \ 1709 { name " Mux", "ADX5 TX1", "ADX5 TX1 XBAR-RX" }, \ 1710 { name " Mux", "ADX5 TX2", "ADX5 TX2 XBAR-RX" }, \ 1711 { name " Mux", "ADX5 TX3", "ADX5 TX3 XBAR-RX" }, \ 1712 { name " Mux", "ADX5 TX4", "ADX5 TX4 XBAR-RX" }, \ 1713 { name " Mux", "ADX6 TX1", "ADX6 TX1 XBAR-RX" }, \ 1714 { name " Mux", "ADX6 TX2", "ADX6 TX2 XBAR-RX" }, \ 1715 { name " Mux", "ADX6 TX3", "ADX6 TX3 XBAR-RX" }, \ 1716 { name " Mux", "ADX6 TX4", "ADX6 TX4 XBAR-RX" }, \ 1717 { name " Mux", "ASRC1 TX1", "ASRC1 TX1 XBAR-RX" }, \ 1718 { name " Mux", "ASRC1 TX2", "ASRC1 TX2 XBAR-RX" }, \ 1719 { name " Mux", "ASRC1 TX3", "ASRC1 TX3 XBAR-RX" }, \ 1720 { name " Mux", "ASRC1 TX4", "ASRC1 TX4 XBAR-RX" }, \ 1721 { name " Mux", "ASRC1 TX5", "ASRC1 TX5 XBAR-RX" }, \ 1722 { name " Mux", "ASRC1 TX6", "ASRC1 TX6 XBAR-RX" }, 1723 1724#define TEGRA210_MUX_ROUTES(name) \ 1725 TEGRA_COMMON_MUX_ROUTES(name) \ 1726 TEGRA210_ONLY_MUX_ROUTES(name) 1727 1728#define TEGRA186_MUX_ROUTES(name) \ 1729 TEGRA_COMMON_MUX_ROUTES(name) \ 1730 TEGRA186_ONLY_MUX_ROUTES(name) 1731 1732#define TEGRA264_MUX_ROUTES(name) \ 1733 TEGRA_COMMON_MUX_ROUTES(name) \ 1734 TEGRA264_ONLY_MUX_ROUTES(name) 1735 1736/* Connect FEs with XBAR */ 1737#define TEGRA_FE_ROUTES(name) \ 1738 { name " XBAR-Playback", NULL, name " Playback" }, \ 1739 { name " XBAR-RX", NULL, name " XBAR-Playback"}, \ 1740 { name " XBAR-Capture", NULL, name " XBAR-TX" }, \ 1741 { name " Capture", NULL, name " XBAR-Capture" }, 1742 1743static const struct snd_soc_dapm_route tegra210_ahub_routes[] = { 1744 TEGRA_FE_ROUTES("ADMAIF1") 1745 TEGRA_FE_ROUTES("ADMAIF2") 1746 TEGRA_FE_ROUTES("ADMAIF3") 1747 TEGRA_FE_ROUTES("ADMAIF4") 1748 TEGRA_FE_ROUTES("ADMAIF5") 1749 TEGRA_FE_ROUTES("ADMAIF6") 1750 TEGRA_FE_ROUTES("ADMAIF7") 1751 TEGRA_FE_ROUTES("ADMAIF8") 1752 TEGRA_FE_ROUTES("ADMAIF9") 1753 TEGRA_FE_ROUTES("ADMAIF10") 1754 TEGRA210_MUX_ROUTES("ADMAIF1") 1755 TEGRA210_MUX_ROUTES("ADMAIF2") 1756 TEGRA210_MUX_ROUTES("ADMAIF3") 1757 TEGRA210_MUX_ROUTES("ADMAIF4") 1758 TEGRA210_MUX_ROUTES("ADMAIF5") 1759 TEGRA210_MUX_ROUTES("ADMAIF6") 1760 TEGRA210_MUX_ROUTES("ADMAIF7") 1761 TEGRA210_MUX_ROUTES("ADMAIF8") 1762 TEGRA210_MUX_ROUTES("ADMAIF9") 1763 TEGRA210_MUX_ROUTES("ADMAIF10") 1764 TEGRA210_MUX_ROUTES("I2S1") 1765 TEGRA210_MUX_ROUTES("I2S2") 1766 TEGRA210_MUX_ROUTES("I2S3") 1767 TEGRA210_MUX_ROUTES("I2S4") 1768 TEGRA210_MUX_ROUTES("I2S5") 1769 TEGRA210_MUX_ROUTES("SFC1") 1770 TEGRA210_MUX_ROUTES("SFC2") 1771 TEGRA210_MUX_ROUTES("SFC3") 1772 TEGRA210_MUX_ROUTES("SFC4") 1773 TEGRA210_MUX_ROUTES("MVC1") 1774 TEGRA210_MUX_ROUTES("MVC2") 1775 TEGRA210_MUX_ROUTES("AMX1 RX1") 1776 TEGRA210_MUX_ROUTES("AMX1 RX2") 1777 TEGRA210_MUX_ROUTES("AMX1 RX3") 1778 TEGRA210_MUX_ROUTES("AMX1 RX4") 1779 TEGRA210_MUX_ROUTES("AMX2 RX1") 1780 TEGRA210_MUX_ROUTES("AMX2 RX2") 1781 TEGRA210_MUX_ROUTES("AMX2 RX3") 1782 TEGRA210_MUX_ROUTES("AMX2 RX4") 1783 TEGRA210_MUX_ROUTES("ADX1") 1784 TEGRA210_MUX_ROUTES("ADX2") 1785 TEGRA210_MUX_ROUTES("MIXER1 RX1") 1786 TEGRA210_MUX_ROUTES("MIXER1 RX2") 1787 TEGRA210_MUX_ROUTES("MIXER1 RX3") 1788 TEGRA210_MUX_ROUTES("MIXER1 RX4") 1789 TEGRA210_MUX_ROUTES("MIXER1 RX5") 1790 TEGRA210_MUX_ROUTES("MIXER1 RX6") 1791 TEGRA210_MUX_ROUTES("MIXER1 RX7") 1792 TEGRA210_MUX_ROUTES("MIXER1 RX8") 1793 TEGRA210_MUX_ROUTES("MIXER1 RX9") 1794 TEGRA210_MUX_ROUTES("MIXER1 RX10") 1795 TEGRA210_MUX_ROUTES("OPE1") 1796 TEGRA210_MUX_ROUTES("OPE2") 1797}; 1798 1799static const struct snd_soc_dapm_route tegra186_ahub_routes[] = { 1800 TEGRA_FE_ROUTES("ADMAIF1") 1801 TEGRA_FE_ROUTES("ADMAIF2") 1802 TEGRA_FE_ROUTES("ADMAIF3") 1803 TEGRA_FE_ROUTES("ADMAIF4") 1804 TEGRA_FE_ROUTES("ADMAIF5") 1805 TEGRA_FE_ROUTES("ADMAIF6") 1806 TEGRA_FE_ROUTES("ADMAIF7") 1807 TEGRA_FE_ROUTES("ADMAIF8") 1808 TEGRA_FE_ROUTES("ADMAIF9") 1809 TEGRA_FE_ROUTES("ADMAIF10") 1810 TEGRA_FE_ROUTES("ADMAIF11") 1811 TEGRA_FE_ROUTES("ADMAIF12") 1812 TEGRA_FE_ROUTES("ADMAIF13") 1813 TEGRA_FE_ROUTES("ADMAIF14") 1814 TEGRA_FE_ROUTES("ADMAIF15") 1815 TEGRA_FE_ROUTES("ADMAIF16") 1816 TEGRA_FE_ROUTES("ADMAIF17") 1817 TEGRA_FE_ROUTES("ADMAIF18") 1818 TEGRA_FE_ROUTES("ADMAIF19") 1819 TEGRA_FE_ROUTES("ADMAIF20") 1820 TEGRA186_MUX_ROUTES("ADMAIF1") 1821 TEGRA186_MUX_ROUTES("ADMAIF2") 1822 TEGRA186_MUX_ROUTES("ADMAIF3") 1823 TEGRA186_MUX_ROUTES("ADMAIF4") 1824 TEGRA186_MUX_ROUTES("ADMAIF5") 1825 TEGRA186_MUX_ROUTES("ADMAIF6") 1826 TEGRA186_MUX_ROUTES("ADMAIF7") 1827 TEGRA186_MUX_ROUTES("ADMAIF8") 1828 TEGRA186_MUX_ROUTES("ADMAIF9") 1829 TEGRA186_MUX_ROUTES("ADMAIF10") 1830 TEGRA186_MUX_ROUTES("ADMAIF11") 1831 TEGRA186_MUX_ROUTES("ADMAIF12") 1832 TEGRA186_MUX_ROUTES("ADMAIF13") 1833 TEGRA186_MUX_ROUTES("ADMAIF14") 1834 TEGRA186_MUX_ROUTES("ADMAIF15") 1835 TEGRA186_MUX_ROUTES("ADMAIF16") 1836 TEGRA186_MUX_ROUTES("ADMAIF17") 1837 TEGRA186_MUX_ROUTES("ADMAIF18") 1838 TEGRA186_MUX_ROUTES("ADMAIF19") 1839 TEGRA186_MUX_ROUTES("ADMAIF20") 1840 TEGRA186_MUX_ROUTES("I2S1") 1841 TEGRA186_MUX_ROUTES("I2S2") 1842 TEGRA186_MUX_ROUTES("I2S3") 1843 TEGRA186_MUX_ROUTES("I2S4") 1844 TEGRA186_MUX_ROUTES("I2S5") 1845 TEGRA186_MUX_ROUTES("I2S6") 1846 TEGRA186_MUX_ROUTES("DSPK1") 1847 TEGRA186_MUX_ROUTES("DSPK2") 1848 TEGRA186_MUX_ROUTES("SFC1") 1849 TEGRA186_MUX_ROUTES("SFC2") 1850 TEGRA186_MUX_ROUTES("SFC3") 1851 TEGRA186_MUX_ROUTES("SFC4") 1852 TEGRA186_MUX_ROUTES("MVC1") 1853 TEGRA186_MUX_ROUTES("MVC2") 1854 TEGRA186_MUX_ROUTES("AMX1 RX1") 1855 TEGRA186_MUX_ROUTES("AMX1 RX2") 1856 TEGRA186_MUX_ROUTES("AMX1 RX3") 1857 TEGRA186_MUX_ROUTES("AMX1 RX4") 1858 TEGRA186_MUX_ROUTES("AMX2 RX1") 1859 TEGRA186_MUX_ROUTES("AMX2 RX2") 1860 TEGRA186_MUX_ROUTES("AMX2 RX3") 1861 TEGRA186_MUX_ROUTES("AMX2 RX4") 1862 TEGRA186_MUX_ROUTES("AMX3 RX1") 1863 TEGRA186_MUX_ROUTES("AMX3 RX2") 1864 TEGRA186_MUX_ROUTES("AMX3 RX3") 1865 TEGRA186_MUX_ROUTES("AMX3 RX4") 1866 TEGRA186_MUX_ROUTES("AMX4 RX1") 1867 TEGRA186_MUX_ROUTES("AMX4 RX2") 1868 TEGRA186_MUX_ROUTES("AMX4 RX3") 1869 TEGRA186_MUX_ROUTES("AMX4 RX4") 1870 TEGRA186_MUX_ROUTES("ADX1") 1871 TEGRA186_MUX_ROUTES("ADX2") 1872 TEGRA186_MUX_ROUTES("ADX3") 1873 TEGRA186_MUX_ROUTES("ADX4") 1874 TEGRA186_MUX_ROUTES("MIXER1 RX1") 1875 TEGRA186_MUX_ROUTES("MIXER1 RX2") 1876 TEGRA186_MUX_ROUTES("MIXER1 RX3") 1877 TEGRA186_MUX_ROUTES("MIXER1 RX4") 1878 TEGRA186_MUX_ROUTES("MIXER1 RX5") 1879 TEGRA186_MUX_ROUTES("MIXER1 RX6") 1880 TEGRA186_MUX_ROUTES("MIXER1 RX7") 1881 TEGRA186_MUX_ROUTES("MIXER1 RX8") 1882 TEGRA186_MUX_ROUTES("MIXER1 RX9") 1883 TEGRA186_MUX_ROUTES("MIXER1 RX10") 1884 TEGRA186_MUX_ROUTES("ASRC1 RX1") 1885 TEGRA186_MUX_ROUTES("ASRC1 RX2") 1886 TEGRA186_MUX_ROUTES("ASRC1 RX3") 1887 TEGRA186_MUX_ROUTES("ASRC1 RX4") 1888 TEGRA186_MUX_ROUTES("ASRC1 RX5") 1889 TEGRA186_MUX_ROUTES("ASRC1 RX6") 1890 TEGRA186_MUX_ROUTES("ASRC1 RX7") 1891 TEGRA186_MUX_ROUTES("OPE1") 1892}; 1893 1894static const struct snd_soc_dapm_route tegra264_ahub_routes[] = { 1895 TEGRA_FE_ROUTES("ADMAIF1") 1896 TEGRA_FE_ROUTES("ADMAIF2") 1897 TEGRA_FE_ROUTES("ADMAIF3") 1898 TEGRA_FE_ROUTES("ADMAIF4") 1899 TEGRA_FE_ROUTES("ADMAIF5") 1900 TEGRA_FE_ROUTES("ADMAIF6") 1901 TEGRA_FE_ROUTES("ADMAIF7") 1902 TEGRA_FE_ROUTES("ADMAIF8") 1903 TEGRA_FE_ROUTES("ADMAIF9") 1904 TEGRA_FE_ROUTES("ADMAIF10") 1905 TEGRA_FE_ROUTES("ADMAIF11") 1906 TEGRA_FE_ROUTES("ADMAIF12") 1907 TEGRA_FE_ROUTES("ADMAIF13") 1908 TEGRA_FE_ROUTES("ADMAIF14") 1909 TEGRA_FE_ROUTES("ADMAIF15") 1910 TEGRA_FE_ROUTES("ADMAIF16") 1911 TEGRA_FE_ROUTES("ADMAIF17") 1912 TEGRA_FE_ROUTES("ADMAIF18") 1913 TEGRA_FE_ROUTES("ADMAIF19") 1914 TEGRA_FE_ROUTES("ADMAIF20") 1915 TEGRA_FE_ROUTES("ADMAIF21") 1916 TEGRA_FE_ROUTES("ADMAIF22") 1917 TEGRA_FE_ROUTES("ADMAIF23") 1918 TEGRA_FE_ROUTES("ADMAIF24") 1919 TEGRA_FE_ROUTES("ADMAIF25") 1920 TEGRA_FE_ROUTES("ADMAIF26") 1921 TEGRA_FE_ROUTES("ADMAIF27") 1922 TEGRA_FE_ROUTES("ADMAIF28") 1923 TEGRA_FE_ROUTES("ADMAIF29") 1924 TEGRA_FE_ROUTES("ADMAIF30") 1925 TEGRA_FE_ROUTES("ADMAIF31") 1926 TEGRA_FE_ROUTES("ADMAIF32") 1927 TEGRA264_MUX_ROUTES("ADMAIF1") 1928 TEGRA264_MUX_ROUTES("ADMAIF2") 1929 TEGRA264_MUX_ROUTES("ADMAIF3") 1930 TEGRA264_MUX_ROUTES("ADMAIF4") 1931 TEGRA264_MUX_ROUTES("ADMAIF5") 1932 TEGRA264_MUX_ROUTES("ADMAIF6") 1933 TEGRA264_MUX_ROUTES("ADMAIF7") 1934 TEGRA264_MUX_ROUTES("ADMAIF8") 1935 TEGRA264_MUX_ROUTES("ADMAIF9") 1936 TEGRA264_MUX_ROUTES("ADMAIF10") 1937 TEGRA264_MUX_ROUTES("ADMAIF11") 1938 TEGRA264_MUX_ROUTES("ADMAIF12") 1939 TEGRA264_MUX_ROUTES("ADMAIF13") 1940 TEGRA264_MUX_ROUTES("ADMAIF14") 1941 TEGRA264_MUX_ROUTES("ADMAIF15") 1942 TEGRA264_MUX_ROUTES("ADMAIF16") 1943 TEGRA264_MUX_ROUTES("ADMAIF17") 1944 TEGRA264_MUX_ROUTES("ADMAIF18") 1945 TEGRA264_MUX_ROUTES("ADMAIF19") 1946 TEGRA264_MUX_ROUTES("ADMAIF20") 1947 TEGRA264_MUX_ROUTES("ADMAIF21") 1948 TEGRA264_MUX_ROUTES("ADMAIF22") 1949 TEGRA264_MUX_ROUTES("ADMAIF23") 1950 TEGRA264_MUX_ROUTES("ADMAIF24") 1951 TEGRA264_MUX_ROUTES("ADMAIF25") 1952 TEGRA264_MUX_ROUTES("ADMAIF26") 1953 TEGRA264_MUX_ROUTES("ADMAIF27") 1954 TEGRA264_MUX_ROUTES("ADMAIF28") 1955 TEGRA264_MUX_ROUTES("ADMAIF29") 1956 TEGRA264_MUX_ROUTES("ADMAIF30") 1957 TEGRA264_MUX_ROUTES("ADMAIF31") 1958 TEGRA264_MUX_ROUTES("ADMAIF32") 1959 TEGRA264_MUX_ROUTES("I2S1") 1960 TEGRA264_MUX_ROUTES("I2S2") 1961 TEGRA264_MUX_ROUTES("I2S3") 1962 TEGRA264_MUX_ROUTES("I2S4") 1963 TEGRA264_MUX_ROUTES("I2S5") 1964 TEGRA264_MUX_ROUTES("I2S6") 1965 TEGRA264_MUX_ROUTES("I2S7") 1966 TEGRA264_MUX_ROUTES("I2S8") 1967 TEGRA264_MUX_ROUTES("DSPK1") 1968 TEGRA264_MUX_ROUTES("SFC1") 1969 TEGRA264_MUX_ROUTES("SFC2") 1970 TEGRA264_MUX_ROUTES("SFC3") 1971 TEGRA264_MUX_ROUTES("SFC4") 1972 TEGRA264_MUX_ROUTES("MVC1") 1973 TEGRA264_MUX_ROUTES("MVC2") 1974 TEGRA264_MUX_ROUTES("AMX1 RX1") 1975 TEGRA264_MUX_ROUTES("AMX1 RX2") 1976 TEGRA264_MUX_ROUTES("AMX1 RX3") 1977 TEGRA264_MUX_ROUTES("AMX1 RX4") 1978 TEGRA264_MUX_ROUTES("AMX2 RX1") 1979 TEGRA264_MUX_ROUTES("AMX2 RX2") 1980 TEGRA264_MUX_ROUTES("AMX2 RX3") 1981 TEGRA264_MUX_ROUTES("AMX2 RX4") 1982 TEGRA264_MUX_ROUTES("AMX3 RX1") 1983 TEGRA264_MUX_ROUTES("AMX3 RX2") 1984 TEGRA264_MUX_ROUTES("AMX3 RX3") 1985 TEGRA264_MUX_ROUTES("AMX3 RX4") 1986 TEGRA264_MUX_ROUTES("AMX4 RX1") 1987 TEGRA264_MUX_ROUTES("AMX4 RX2") 1988 TEGRA264_MUX_ROUTES("AMX4 RX3") 1989 TEGRA264_MUX_ROUTES("AMX4 RX4") 1990 TEGRA264_MUX_ROUTES("AMX5 RX1") 1991 TEGRA264_MUX_ROUTES("AMX5 RX2") 1992 TEGRA264_MUX_ROUTES("AMX5 RX3") 1993 TEGRA264_MUX_ROUTES("AMX5 RX4") 1994 TEGRA264_MUX_ROUTES("AMX6 RX1") 1995 TEGRA264_MUX_ROUTES("AMX6 RX2") 1996 TEGRA264_MUX_ROUTES("AMX6 RX3") 1997 TEGRA264_MUX_ROUTES("AMX6 RX4") 1998 TEGRA264_MUX_ROUTES("ADX1") 1999 TEGRA264_MUX_ROUTES("ADX2") 2000 TEGRA264_MUX_ROUTES("ADX3") 2001 TEGRA264_MUX_ROUTES("ADX4") 2002 TEGRA264_MUX_ROUTES("ADX5") 2003 TEGRA264_MUX_ROUTES("ADX6") 2004 TEGRA264_MUX_ROUTES("MIXER1 RX1") 2005 TEGRA264_MUX_ROUTES("MIXER1 RX2") 2006 TEGRA264_MUX_ROUTES("MIXER1 RX3") 2007 TEGRA264_MUX_ROUTES("MIXER1 RX4") 2008 TEGRA264_MUX_ROUTES("MIXER1 RX5") 2009 TEGRA264_MUX_ROUTES("MIXER1 RX6") 2010 TEGRA264_MUX_ROUTES("MIXER1 RX7") 2011 TEGRA264_MUX_ROUTES("MIXER1 RX8") 2012 TEGRA264_MUX_ROUTES("MIXER1 RX9") 2013 TEGRA264_MUX_ROUTES("MIXER1 RX10") 2014 TEGRA264_MUX_ROUTES("ASRC1 RX1") 2015 TEGRA264_MUX_ROUTES("ASRC1 RX2") 2016 TEGRA264_MUX_ROUTES("ASRC1 RX3") 2017 TEGRA264_MUX_ROUTES("ASRC1 RX4") 2018 TEGRA264_MUX_ROUTES("ASRC1 RX5") 2019 TEGRA264_MUX_ROUTES("ASRC1 RX6") 2020 TEGRA264_MUX_ROUTES("ASRC1 RX7") 2021 TEGRA264_MUX_ROUTES("OPE1") 2022}; 2023 2024static const struct snd_soc_component_driver tegra210_ahub_component = { 2025 .dapm_widgets = tegra210_ahub_widgets, 2026 .num_dapm_widgets = ARRAY_SIZE(tegra210_ahub_widgets), 2027 .dapm_routes = tegra210_ahub_routes, 2028 .num_dapm_routes = ARRAY_SIZE(tegra210_ahub_routes), 2029}; 2030 2031static const struct snd_soc_component_driver tegra186_ahub_component = { 2032 .dapm_widgets = tegra186_ahub_widgets, 2033 .num_dapm_widgets = ARRAY_SIZE(tegra186_ahub_widgets), 2034 .dapm_routes = tegra186_ahub_routes, 2035 .num_dapm_routes = ARRAY_SIZE(tegra186_ahub_routes), 2036}; 2037 2038static const struct snd_soc_component_driver tegra234_ahub_component = { 2039 .dapm_widgets = tegra234_ahub_widgets, 2040 .num_dapm_widgets = ARRAY_SIZE(tegra234_ahub_widgets), 2041 .dapm_routes = tegra186_ahub_routes, 2042 .num_dapm_routes = ARRAY_SIZE(tegra186_ahub_routes), 2043}; 2044 2045static const struct snd_soc_component_driver tegra264_ahub_component = { 2046 .dapm_widgets = tegra264_ahub_widgets, 2047 .num_dapm_widgets = ARRAY_SIZE(tegra264_ahub_widgets), 2048 .dapm_routes = tegra264_ahub_routes, 2049 .num_dapm_routes = ARRAY_SIZE(tegra264_ahub_routes), 2050}; 2051 2052static bool tegra210_ahub_wr_reg(struct device *dev, unsigned int reg) 2053{ 2054 int part; 2055 2056 if (reg % TEGRA210_XBAR_RX_STRIDE) 2057 return false; 2058 2059 for (part = 0; part < TEGRA210_XBAR_UPDATE_MAX_REG; part++) { 2060 switch (reg & ~(part * TEGRA210_XBAR_PART1_RX)) { 2061 case TEGRA210_AXBAR_PART_0_ADMAIF_RX1_0 ... TEGRA210_AXBAR_PART_0_ADMAIF_RX10_0: 2062 case TEGRA210_AXBAR_PART_0_I2S1_RX1_0 ... TEGRA210_AXBAR_PART_0_I2S5_RX1_0: 2063 case TEGRA210_AXBAR_PART_0_SFC1_RX1_0 ... TEGRA210_AXBAR_PART_0_SFC4_RX1_0: 2064 case TEGRA210_AXBAR_PART_0_MIXER1_RX1_0 ... TEGRA210_AXBAR_PART_0_MIXER1_RX10_0: 2065 case TEGRA210_AXBAR_PART_0_SPDIF1_RX1_0 ... TEGRA210_AXBAR_PART_0_SPDIF1_RX2_0: 2066 case TEGRA210_AXBAR_PART_0_AFC1_RX1_0 ... TEGRA210_AXBAR_PART_0_AFC6_RX1_0: 2067 case TEGRA210_AXBAR_PART_0_OPE1_RX1_0 ... TEGRA210_AXBAR_PART_0_OPE2_RX1_0: 2068 case TEGRA210_AXBAR_PART_0_SPKPROT1_RX1_0: 2069 case TEGRA210_AXBAR_PART_0_MVC1_RX1_0 ... TEGRA210_AXBAR_PART_0_MVC2_RX1_0: 2070 case TEGRA210_AXBAR_PART_0_AMX1_RX1_0 ... TEGRA210_AXBAR_PART_0_ADX2_RX1_0: 2071 return true; 2072 default: 2073 break; 2074 } 2075 } 2076 2077 return false; 2078} 2079 2080static bool tegra186_ahub_wr_reg(struct device *dev, unsigned int reg) 2081{ 2082 int part; 2083 2084 if (reg % TEGRA210_XBAR_RX_STRIDE) 2085 return false; 2086 2087 for (part = 0; part < TEGRA186_XBAR_UPDATE_MAX_REG; part++) { 2088 switch (reg & ~(part * TEGRA210_XBAR_PART1_RX)) { 2089 case TEGRA210_AXBAR_PART_0_ADMAIF_RX1_0 ... TEGRA186_AXBAR_PART_0_I2S6_RX1_0: 2090 case TEGRA210_AXBAR_PART_0_SFC1_RX1_0 ... TEGRA210_AXBAR_PART_0_SFC4_RX1_0: 2091 case TEGRA210_AXBAR_PART_0_MIXER1_RX1_0 ... TEGRA210_AXBAR_PART_0_MIXER1_RX10_0: 2092 case TEGRA186_AXBAR_PART_0_DSPK1_RX1_0 ... TEGRA186_AXBAR_PART_0_DSPK2_RX1_0: 2093 case TEGRA210_AXBAR_PART_0_AFC1_RX1_0 ... TEGRA210_AXBAR_PART_0_AFC6_RX1_0: 2094 case TEGRA210_AXBAR_PART_0_OPE1_RX1_0: 2095 case TEGRA186_AXBAR_PART_0_MVC1_RX1_0 ... TEGRA186_AXBAR_PART_0_MVC2_RX1_0: 2096 case TEGRA186_AXBAR_PART_0_AMX1_RX1_0 ... TEGRA186_AXBAR_PART_0_AMX3_RX4_0: 2097 case TEGRA210_AXBAR_PART_0_ADX1_RX1_0 ... TEGRA186_AXBAR_PART_0_ASRC1_RX7_0: 2098 return true; 2099 default: 2100 break; 2101 } 2102 } 2103 2104 return false; 2105} 2106 2107static bool tegra264_ahub_wr_reg(struct device *dev, unsigned int reg) 2108{ 2109 int part; 2110 2111 for (part = 0; part < TEGRA264_XBAR_UPDATE_MAX_REG; part++) { 2112 switch (reg & ~(part << 12)) { 2113 case TEGRA264_AXBAR_ADMAIF_RX1 ... TEGRA264_AXBAR_SFC4_RX1: 2114 case TEGRA264_AXBAR_MIXER1_RX1 ... TEGRA264_AXBAR_MIXER1_RX10: 2115 case TEGRA264_AXBAR_DSPK1_RX1: 2116 case TEGRA264_AXBAR_OPE1_RX1: 2117 case TEGRA264_AXBAR_MVC1_RX1 ... TEGRA264_AXBAR_MVC2_RX1: 2118 case TEGRA264_AXBAR_AMX1_RX1 ... TEGRA264_AXBAR_AMX3_RX4: 2119 case TEGRA264_AXBAR_ADX1_RX1 ... TEGRA264_AXBAR_ASRC1_RX7: 2120 case TEGRA264_AXBAR_ADMAIF_RX21 ... TEGRA264_AXBAR_ADX6_RX1: 2121 return true; 2122 default: 2123 break; 2124 } 2125 } 2126 2127 return false; 2128} 2129 2130static const struct regmap_config tegra210_ahub_regmap_config = { 2131 .reg_bits = 32, 2132 .val_bits = 32, 2133 .reg_stride = 4, 2134 .writeable_reg = tegra210_ahub_wr_reg, 2135 .max_register = TEGRA210_MAX_REGISTER_ADDR, 2136 .cache_type = REGCACHE_FLAT, 2137}; 2138 2139static const struct regmap_config tegra186_ahub_regmap_config = { 2140 .reg_bits = 32, 2141 .val_bits = 32, 2142 .reg_stride = 4, 2143 .writeable_reg = tegra186_ahub_wr_reg, 2144 .max_register = TEGRA186_MAX_REGISTER_ADDR, 2145 .cache_type = REGCACHE_FLAT, 2146}; 2147 2148static const struct regmap_config tegra264_ahub_regmap_config = { 2149 .reg_bits = 32, 2150 .val_bits = 32, 2151 .reg_stride = 4, 2152 .writeable_reg = tegra264_ahub_wr_reg, 2153 .max_register = TEGRA264_MAX_REGISTER_ADDR, 2154 .cache_type = REGCACHE_FLAT, 2155}; 2156 2157static const struct tegra_ahub_soc_data soc_data_tegra210 = { 2158 .cmpnt_drv = &tegra210_ahub_component, 2159 .dai_drv = tegra210_ahub_dais, 2160 .num_dais = ARRAY_SIZE(tegra210_ahub_dais), 2161 .regmap_config = &tegra210_ahub_regmap_config, 2162 .mask[0] = TEGRA210_XBAR_REG_MASK_0, 2163 .mask[1] = TEGRA210_XBAR_REG_MASK_1, 2164 .mask[2] = TEGRA210_XBAR_REG_MASK_2, 2165 .mask[3] = TEGRA210_XBAR_REG_MASK_3, 2166 .reg_count = TEGRA210_XBAR_UPDATE_MAX_REG, 2167 .xbar_part_size = TEGRA210_XBAR_PART1_RX, 2168}; 2169 2170static const struct tegra_ahub_soc_data soc_data_tegra186 = { 2171 .cmpnt_drv = &tegra186_ahub_component, 2172 .dai_drv = tegra186_ahub_dais, 2173 .num_dais = ARRAY_SIZE(tegra186_ahub_dais), 2174 .regmap_config = &tegra186_ahub_regmap_config, 2175 .mask[0] = TEGRA186_XBAR_REG_MASK_0, 2176 .mask[1] = TEGRA186_XBAR_REG_MASK_1, 2177 .mask[2] = TEGRA186_XBAR_REG_MASK_2, 2178 .mask[3] = TEGRA186_XBAR_REG_MASK_3, 2179 .reg_count = TEGRA186_XBAR_UPDATE_MAX_REG, 2180 .xbar_part_size = TEGRA210_XBAR_PART1_RX, 2181}; 2182 2183static const struct tegra_ahub_soc_data soc_data_tegra234 = { 2184 .cmpnt_drv = &tegra234_ahub_component, 2185 .dai_drv = tegra186_ahub_dais, 2186 .num_dais = ARRAY_SIZE(tegra186_ahub_dais), 2187 .regmap_config = &tegra186_ahub_regmap_config, 2188 .mask[0] = TEGRA186_XBAR_REG_MASK_0, 2189 .mask[1] = TEGRA186_XBAR_REG_MASK_1, 2190 .mask[2] = TEGRA186_XBAR_REG_MASK_2, 2191 .mask[3] = TEGRA186_XBAR_REG_MASK_3, 2192 .reg_count = TEGRA186_XBAR_UPDATE_MAX_REG, 2193 .xbar_part_size = TEGRA210_XBAR_PART1_RX, 2194}; 2195 2196static const struct tegra_ahub_soc_data soc_data_tegra264 = { 2197 .cmpnt_drv = &tegra264_ahub_component, 2198 .dai_drv = tegra264_ahub_dais, 2199 .num_dais = ARRAY_SIZE(tegra264_ahub_dais), 2200 .regmap_config = &tegra264_ahub_regmap_config, 2201 .mask[0] = TEGRA264_XBAR_REG_MASK_0, 2202 .mask[1] = TEGRA264_XBAR_REG_MASK_1, 2203 .mask[2] = TEGRA264_XBAR_REG_MASK_2, 2204 .mask[3] = TEGRA264_XBAR_REG_MASK_3, 2205 .mask[4] = TEGRA264_XBAR_REG_MASK_4, 2206 .reg_count = TEGRA264_XBAR_UPDATE_MAX_REG, 2207 .xbar_part_size = TEGRA264_XBAR_PART1_RX, 2208}; 2209 2210static const struct of_device_id tegra_ahub_of_match[] = { 2211 { .compatible = "nvidia,tegra210-ahub", .data = &soc_data_tegra210 }, 2212 { .compatible = "nvidia,tegra186-ahub", .data = &soc_data_tegra186 }, 2213 { .compatible = "nvidia,tegra234-ahub", .data = &soc_data_tegra234 }, 2214 { .compatible = "nvidia,tegra264-ahub", .data = &soc_data_tegra264 }, 2215 {}, 2216}; 2217MODULE_DEVICE_TABLE(of, tegra_ahub_of_match); 2218 2219static int tegra_ahub_runtime_suspend(struct device *dev) 2220{ 2221 struct tegra_ahub *ahub = dev_get_drvdata(dev); 2222 2223 regcache_cache_only(ahub->regmap, true); 2224 regcache_mark_dirty(ahub->regmap); 2225 2226 clk_disable_unprepare(ahub->clk); 2227 2228 return 0; 2229} 2230 2231static int tegra_ahub_runtime_resume(struct device *dev) 2232{ 2233 struct tegra_ahub *ahub = dev_get_drvdata(dev); 2234 int err; 2235 2236 err = clk_prepare_enable(ahub->clk); 2237 if (err) { 2238 dev_err(dev, "failed to enable AHUB clock, err: %d\n", err); 2239 return err; 2240 } 2241 2242 regcache_cache_only(ahub->regmap, false); 2243 regcache_sync(ahub->regmap); 2244 2245 return 0; 2246} 2247 2248static int tegra_ahub_probe(struct platform_device *pdev) 2249{ 2250 struct tegra_ahub *ahub; 2251 void __iomem *regs; 2252 int err; 2253 2254 ahub = devm_kzalloc(&pdev->dev, sizeof(*ahub), GFP_KERNEL); 2255 if (!ahub) 2256 return -ENOMEM; 2257 2258 ahub->soc_data = of_device_get_match_data(&pdev->dev); 2259 if (!ahub->soc_data) 2260 return -ENODEV; 2261 2262 platform_set_drvdata(pdev, ahub); 2263 2264 ahub->clk = devm_clk_get(&pdev->dev, "ahub"); 2265 if (IS_ERR(ahub->clk)) { 2266 dev_err(&pdev->dev, "can't retrieve AHUB clock\n"); 2267 return PTR_ERR(ahub->clk); 2268 } 2269 2270 regs = devm_platform_ioremap_resource(pdev, 0); 2271 if (IS_ERR(regs)) 2272 return PTR_ERR(regs); 2273 2274 ahub->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 2275 ahub->soc_data->regmap_config); 2276 if (IS_ERR(ahub->regmap)) { 2277 dev_err(&pdev->dev, "regmap init failed\n"); 2278 return PTR_ERR(ahub->regmap); 2279 } 2280 2281 regcache_cache_only(ahub->regmap, true); 2282 2283 err = devm_snd_soc_register_component(&pdev->dev, 2284 ahub->soc_data->cmpnt_drv, 2285 ahub->soc_data->dai_drv, 2286 ahub->soc_data->num_dais); 2287 if (err) { 2288 dev_err(&pdev->dev, "can't register AHUB component, err: %d\n", 2289 err); 2290 return err; 2291 } 2292 2293 pm_runtime_enable(&pdev->dev); 2294 2295 err = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); 2296 if (err) { 2297 pm_runtime_disable(&pdev->dev); 2298 return err; 2299 } 2300 2301 return 0; 2302} 2303 2304static void tegra_ahub_remove(struct platform_device *pdev) 2305{ 2306 pm_runtime_disable(&pdev->dev); 2307} 2308 2309static const struct dev_pm_ops tegra_ahub_pm_ops = { 2310 RUNTIME_PM_OPS(tegra_ahub_runtime_suspend, 2311 tegra_ahub_runtime_resume, NULL) 2312 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 2313}; 2314 2315static struct platform_driver tegra_ahub_driver = { 2316 .probe = tegra_ahub_probe, 2317 .remove = tegra_ahub_remove, 2318 .driver = { 2319 .name = "tegra210-ahub", 2320 .of_match_table = tegra_ahub_of_match, 2321 .pm = pm_ptr(&tegra_ahub_pm_ops), 2322 }, 2323}; 2324module_platform_driver(tegra_ahub_driver); 2325 2326MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); 2327MODULE_AUTHOR("Mohan Kumar <mkumard@nvidia.com>"); 2328MODULE_DESCRIPTION("Tegra210 ASoC AHUB driver"); 2329MODULE_LICENSE("GPL v2");
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