tegra210_adx.h

 1/* SPDX-License-Identifier: GPL-2.0-only
 2 * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION. All rights reserved.
 3 *
 4 * tegra210_adx.h - Definitions for Tegra210 ADX driver
 5 *
 6 */
 7
 8#ifndef __TEGRA210_ADX_H__
 9#define __TEGRA210_ADX_H__
10
11/* Register offsets from TEGRA210_ADX*_BASE */
12#define TEGRA210_ADX_RX_STATUS		0x0c
13#define TEGRA210_ADX_RX_INT_STATUS	0x10
14#define TEGRA210_ADX_RX_INT_MASK	0x14
15#define TEGRA210_ADX_RX_INT_SET		0x18
16#define TEGRA210_ADX_RX_INT_CLEAR	0x1c
17#define TEGRA210_ADX_RX_CIF_CTRL	0x20
18#define TEGRA210_ADX_TX_STATUS		0x4c
19#define TEGRA210_ADX_TX_INT_STATUS	0x50
20#define TEGRA210_ADX_TX_INT_MASK	0x54
21#define TEGRA210_ADX_TX_INT_SET		0x58
22#define TEGRA210_ADX_TX_INT_CLEAR	0x5c
23#define TEGRA210_ADX_TX1_CIF_CTRL	0x60
24#define TEGRA210_ADX_TX2_CIF_CTRL	0x64
25#define TEGRA210_ADX_TX3_CIF_CTRL	0x68
26#define TEGRA210_ADX_TX4_CIF_CTRL	0x6c
27#define TEGRA210_ADX_ENABLE		0x80
28#define TEGRA210_ADX_SOFT_RESET		0x84
29#define TEGRA210_ADX_CG			0x88
30#define TEGRA210_ADX_STATUS		0x8c
31#define TEGRA210_ADX_INT_STATUS		0x90
32#define TEGRA210_ADX_CTRL		0xa4
33#define TEGRA210_ADX_IN_BYTE_EN0	0xa8
34#define TEGRA210_ADX_IN_BYTE_EN1	0xac
35#define TEGRA210_ADX_CFG_RAM_CTRL	0xb8
36#define TEGRA210_ADX_CFG_RAM_DATA	0xbc
37
38#define TEGRA264_ADX_CYA		0xb8
39#define TEGRA264_ADX_CFG_RAM_CTRL	0xc0
40#define TEGRA264_ADX_CFG_RAM_DATA	0xc4
41
42/* Fields in TEGRA210_ADX_ENABLE */
43#define TEGRA210_ADX_ENABLE_SHIFT			0
44
45/* Fields in TEGRA210_ADX_CFG_RAM_CTRL */
46#define TEGRA210_ADX_CFG_RAM_CTRL_RAM_ADDR_SHIFT	0
47
48#define TEGRA210_ADX_CFG_RAM_CTRL_RW_SHIFT		14
49#define TEGRA210_ADX_CFG_RAM_CTRL_RW_WRITE		(1 << TEGRA210_ADX_CFG_RAM_CTRL_RW_SHIFT)
50
51#define TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT	13
52#define TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN		(1 << TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT)
53
54#define TEGRA210_ADX_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT	12
55#define TEGRA210_ADX_CFG_RAM_CTRL_SEQ_ACCESS_EN		(1 << TEGRA210_ADX_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT)
56
57/* Fields in TEGRA210_ADX_SOFT_RESET */
58#define TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT	0
59#define TEGRA210_ADX_SOFT_RESET_SOFT_RESET_MASK		(1 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT)
60#define TEGRA210_ADX_SOFT_RESET_SOFT_EN			(1 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT)
61#define TEGRA210_ADX_SOFT_RESET_SOFT_DEFAULT		(0 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT)
62
63#define TEGRA210_ADX_AUDIOCIF_CH_STRIDE		4
64#define TEGRA210_ADX_RAM_DEPTH			16
65#define TEGRA210_ADX_MAP_STREAM_NUMBER_SHIFT	6
66#define TEGRA210_ADX_MAP_WORD_NUMBER_SHIFT	2
67#define TEGRA210_ADX_MAP_BYTE_NUMBER_SHIFT	0
68#define TEGRA210_ADX_BYTE_MASK_COUNT		2
69#define TEGRA210_ADX_MAX_CHANNEL		16
70#define TEGRA210_ADX_CYA_OFFSET			0
71
72#define TEGRA264_ADX_RAM_DEPTH			32
73#define TEGRA264_ADX_BYTE_MASK_COUNT		4
74#define TEGRA264_ADX_MAX_CHANNEL		32
75#define TEGRA264_ADX_CYA_OFFSET			8
76
77#define TEGRA_ADX_IN_DAI_ID			4
78
79struct tegra210_adx_soc_data {
80	const struct regmap_config *regmap_conf;
81	const struct snd_kcontrol_new *controls;
82	unsigned int num_controls;
83	unsigned int max_ch;
84	unsigned int ram_depth;
85	unsigned int byte_mask_size;
86	unsigned int cya_offset;
87};
88
89struct tegra210_adx {
90	struct regmap *regmap;
91	unsigned int *map;
92	unsigned int *byte_mask;
93	const struct tegra210_adx_soc_data *soc_data;
94};
95
96#endif