tegra186_asrc.h

  1/* SPDX-License-Identifier: GPL-2.0-only
  2 * SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION. All rights reserved.
  3 * tegra186_asrc.h - Definitions for Tegra186 ASRC driver
  4 *
  5 */
  6
  7#ifndef __TEGRA186_ASRC_H__
  8#define __TEGRA186_ASRC_H__
  9
 10/* ASRC stream related offset */
 11#define TEGRA186_ASRC_CFG				0x0
 12#define TEGRA186_ASRC_RATIO_INT_PART			0x4
 13#define TEGRA186_ASRC_RATIO_FRAC_PART			0x8
 14#define TEGRA186_ASRC_RATIO_LOCK_STATUS			0xc
 15#define TEGRA186_ASRC_MUTE_UNMUTE_DURATION		0x10
 16#define TEGRA186_ASRC_TX_THRESHOLD			0x14
 17#define TEGRA186_ASRC_RX_THRESHOLD			0x18
 18#define TEGRA186_ASRC_RATIO_COMP			0x1c
 19#define TEGRA186_ASRC_RX_STATUS				0x20
 20#define TEGRA186_ASRC_RX_CIF_CTRL			0x24
 21#define TEGRA186_ASRC_TX_STATUS				0x2c
 22#define TEGRA186_ASRC_TX_CIF_CTRL			0x30
 23#define TEGRA186_ASRC_ENABLE				0x38
 24#define TEGRA186_ASRC_SOFT_RESET			0x3c
 25#define TEGRA186_ASRC_STATUS				0x4c
 26#define TEGRA186_ASRC_STATEBUF_ADDR			0x5c
 27#define TEGRA186_ASRC_STATEBUF_CFG			0x60
 28#define TEGRA186_ASRC_INSAMPLEBUF_ADDR			0x64
 29#define TEGRA186_ASRC_INSAMPLEBUF_CFG			0x68
 30#define TEGRA186_ASRC_OUTSAMPLEBUF_ADDR			0x6c
 31#define TEGRA186_ASRC_OUTSAMPLEBUF_CFG			0x70
 32
 33/* ASRC Global registers offset */
 34#define TEGRA186_ASRC_GLOBAL_ENB			0x2f4
 35#define TEGRA186_ASRC_GLOBAL_SOFT_RESET			0x2f8
 36#define TEGRA186_ASRC_GLOBAL_CG				0x2fc
 37#define TEGRA186_ASRC_GLOBAL_CFG			0x300
 38#define TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR		0x304
 39#define TEGRA186_ASRC_GLOBAL_SCRATCH_CFG		0x308
 40#define TEGRA186_ASRC_RATIO_UPD_RX_CIF_CTRL		0x30c
 41#define TEGRA186_ASRC_RATIO_UPD_RX_STATUS		0x310
 42#define TEGRA186_ASRC_GLOBAL_STATUS			0x314
 43#define TEGRA186_ASRC_GLOBAL_STREAM_ENABLE_STATUS	0x318
 44#define TEGRA186_ASRC_GLOBAL_INT_STATUS			0x324
 45#define TEGRA186_ASRC_GLOBAL_INT_MASK			0x328
 46#define TEGRA186_ASRC_GLOBAL_INT_SET			0x32c
 47#define TEGRA186_ASRC_GLOBAL_INT_CLEAR			0x330
 48#define TEGRA186_ASRC_GLOBAL_TRANSFER_ERROR_LOG		0x334
 49#define TEGRA186_ASRC_GLOBAL_APR_CTRL			0x1000
 50#define TEGRA186_ASRC_GLOBAL_APR_CTRL_ACCESS_CTRL	0x1004
 51#define TEGRA186_ASRC_GLOBAL_DISARM_APR			0x1008
 52#define TEGRA186_ASRC_GLOBAL_DISARM_APR_ACCESS_CTRL	0x100c
 53#define TEGRA186_ASRC_GLOBAL_RATIO_WR_ACCESS		0x1010
 54#define TEGRA186_ASRC_GLOBAL_RATIO_WR_ACCESS_CTRL	0x1014
 55#define TEGRA186_ASRC_CYA				0x1018
 56
 57#define TEGRA186_ASRC_STREAM_DEFAULT_HW_COMP_BIAS_VALUE		0xaaaa
 58#define TEGRA186_ASRC_STREAM_DEFAULT_INPUT_HW_COMP_THRESH_CFG	0x00201002
 59#define TEGRA186_ASRC_STREAM_DEFAULT_OUTPUT_HW_COMP_THRESH_CFG	0x00201002
 60
 61#define TEGRA186_ASRC_GLOBAL_CFG_FRAC_28BIT_PRECISION		0
 62#define TEGRA186_ASRC_GLOBAL_CFG_FRAC_32BIT_PRECISION		1
 63
 64#define TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_SHIFT		31
 65#define TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_MASK		(1 << TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_SHIFT)
 66#define TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_ENABLE	(1 << TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_SHIFT)
 67#define TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_DISABLE	(0 << TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_SHIFT)
 68
 69#define TEGRA186_ASRC_STREAM_RATIO_TYPE_SHIFT			0
 70#define TEGRA186_ASRC_STREAM_RATIO_TYPE_MASK			(1 << TEGRA186_ASRC_STREAM_RATIO_TYPE_SHIFT)
 71
 72#define TEGRA186_ASRC_STREAM_EN_SHIFT				0
 73#define TEGRA186_ASRC_STREAM_EN					(1 << TEGRA186_ASRC_STREAM_EN_SHIFT)
 74#define TEGRA186_ASRC_GLOBAL_EN_SHIFT				0
 75#define TEGRA186_ASRC_GLOBAL_EN					(1 << TEGRA186_ASRC_GLOBAL_EN_SHIFT)
 76
 77#define TEGRA186_ASRC_STREAM_STATEBUF_CFG_SIZE_SHIFT		0
 78#define TEGRA186_ASRC_STREAM_STATEBUF_CFG_SIZE_MASK		(0xffff << TEGRA186_ASRC_STREAM_STATEBUF_CFG_SIZE_SHIFT)
 79#define TEGRA186_ASRC_STREAM_INSAMPLEBUF_CFG_SIZE_SHIFT		0
 80#define TEGRA186_ASRC_STREAM_INSAMPLEBUF_CFG_SIZE_MASK		(0xffff << TEGRA186_ASRC_STREAM_INSAMPLEBUF_CFG_SIZE_SHIFT)
 81#define TEGRA186_ASRC_STREAM_OUTSAMPLEBUF_CFG_SIZE_SHIFT	0
 82#define TEGRA186_ASRC_STREAM_OUTSAMPLEBUF_CFG_SIZE_MASK		(0xffff << TEGRA186_ASRC_STREAM_OUTSAMPLEBUF_CFG_SIZE_SHIFT)
 83
 84#define TEGRA186_ASRC_STREAM_RATIO_INT_PART_MASK		0x1f
 85#define TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK		0xffffffff
 86
 87#define TEGRA186_ASRC_STREAM_STRIDE				0x80
 88#define TEGRA186_ASRC_STREAM_MAX				0x6
 89#define TEGRA186_ASRC_STREAM_LIMIT				0x2f0
 90
 91#define TEGRA186_ASRC_RATIO_SOURCE_ARAD				0x0
 92#define TEGRA186_ASRC_RATIO_SOURCE_SW				0x1
 93
 94#define TEGRA186_ASRC_ARAM_START_ADDR				0x3f800000
 95#define TEGRA264_ASRC_ARAM_START_ADDR				0x8a080000
 96
 97struct tegra186_asrc_lane {
 98	unsigned int int_part;
 99	unsigned int frac_part;
100	unsigned int ratio_source;
101	unsigned int hwcomp_disable;
102	unsigned int input_thresh;
103	unsigned int output_thresh;
104};
105
106struct tegra_asrc_soc_data {
107	unsigned int aram_start_addr;
108};
109
110struct tegra186_asrc {
111	const struct tegra_asrc_soc_data *soc_data;
112	struct tegra186_asrc_lane lane[TEGRA186_ASRC_STREAM_MAX];
113	struct regmap *regmap;
114};
115
116#endif