sun4i-spdif.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * ALSA SoC SPDIF Audio Layer
  4 *
  5 * Copyright 2015 Andrea Venturi <be17068@iperbole.bo.it>
  6 * Copyright 2015 Marcus Cooper <codekipper@gmail.com>
  7 *
  8 * Based on the Allwinner SDK driver, released under the GPL.
  9 */
 10
 11#include <linux/clk.h>
 12#include <linux/delay.h>
 13#include <linux/device.h>
 14#include <linux/kernel.h>
 15#include <linux/init.h>
 16#include <linux/regmap.h>
 17#include <linux/of.h>
 18#include <linux/ioport.h>
 19#include <linux/module.h>
 20#include <linux/platform_device.h>
 21#include <linux/pm_runtime.h>
 22#include <linux/reset.h>
 23#include <linux/spinlock.h>
 24#include <sound/asoundef.h>
 25#include <sound/dmaengine_pcm.h>
 26#include <sound/pcm_params.h>
 27#include <sound/soc.h>
 28
 29#define	SUN4I_SPDIF_CTL		(0x00)
 30	#define SUN4I_SPDIF_CTL_MCLKDIV(v)		((v) << 4) /* v even */
 31	#define SUN4I_SPDIF_CTL_MCLKOUTEN		BIT(2)
 32	#define SUN4I_SPDIF_CTL_GEN			BIT(1)
 33	#define SUN4I_SPDIF_CTL_RESET			BIT(0)
 34
 35#define SUN4I_SPDIF_TXCFG	(0x04)
 36	#define SUN4I_SPDIF_TXCFG_SINGLEMOD		BIT(31)
 37	#define SUN4I_SPDIF_TXCFG_ASS			BIT(17)
 38	#define SUN4I_SPDIF_TXCFG_NONAUDIO		BIT(16)
 39	#define SUN4I_SPDIF_TXCFG_TXRATIO(v)		((v) << 4)
 40	#define SUN4I_SPDIF_TXCFG_TXRATIO_MASK		GENMASK(8, 4)
 41	#define SUN4I_SPDIF_TXCFG_FMTRVD		GENMASK(3, 2)
 42	#define SUN4I_SPDIF_TXCFG_FMT16BIT		(0 << 2)
 43	#define SUN4I_SPDIF_TXCFG_FMT20BIT		(1 << 2)
 44	#define SUN4I_SPDIF_TXCFG_FMT24BIT		(2 << 2)
 45	#define SUN4I_SPDIF_TXCFG_CHSTMODE		BIT(1)
 46	#define SUN4I_SPDIF_TXCFG_TXEN			BIT(0)
 47
 48#define SUN4I_SPDIF_RXCFG	(0x08)
 49	#define SUN4I_SPDIF_RXCFG_LOCKFLAG		BIT(4)
 50	#define SUN4I_SPDIF_RXCFG_CHSTSRC		BIT(3)
 51	#define SUN4I_SPDIF_RXCFG_CHSTCP		BIT(1)
 52	#define SUN4I_SPDIF_RXCFG_RXEN			BIT(0)
 53
 54#define SUN4I_SPDIF_TXFIFO	(0x0C)
 55
 56#define SUN4I_SPDIF_RXFIFO	(0x10)
 57
 58#define SUN4I_SPDIF_FCTL	(0x14)
 59	#define SUN4I_SPDIF_FCTL_FIFOSRC		BIT(31)
 60	#define SUN4I_SPDIF_FCTL_FTX			BIT(17)
 61	#define SUN4I_SPDIF_FCTL_FRX			BIT(16)
 62	#define SUN4I_SPDIF_FCTL_TXTL(v)		((v) << 8)
 63	#define SUN4I_SPDIF_FCTL_TXTL_MASK		GENMASK(12, 8)
 64	#define SUN4I_SPDIF_FCTL_RXTL(v)		((v) << 3)
 65	#define SUN4I_SPDIF_FCTL_RXTL_MASK		GENMASK(7, 3)
 66	#define SUN4I_SPDIF_FCTL_TXIM			BIT(2)
 67	#define SUN4I_SPDIF_FCTL_RXOM(v)		((v) << 0)
 68	#define SUN4I_SPDIF_FCTL_RXOM_MASK		GENMASK(1, 0)
 69
 70#define SUN50I_H6_SPDIF_FCTL (0x14)
 71	#define SUN50I_H6_SPDIF_FCTL_HUB_EN		BIT(31)
 72	#define SUN50I_H6_SPDIF_FCTL_FTX		BIT(30)
 73	#define SUN50I_H6_SPDIF_FCTL_FRX		BIT(29)
 74	#define SUN50I_H6_SPDIF_FCTL_TXTL(v)		((v) << 12)
 75	#define SUN50I_H6_SPDIF_FCTL_TXTL_MASK		GENMASK(19, 12)
 76	#define SUN50I_H6_SPDIF_FCTL_RXTL(v)		((v) << 4)
 77	#define SUN50I_H6_SPDIF_FCTL_RXTL_MASK		GENMASK(10, 4)
 78	#define SUN50I_H6_SPDIF_FCTL_TXIM		BIT(2)
 79	#define SUN50I_H6_SPDIF_FCTL_RXOM(v)		((v) << 0)
 80	#define SUN50I_H6_SPDIF_FCTL_RXOM_MASK		GENMASK(1, 0)
 81
 82#define SUN4I_SPDIF_FSTA	(0x18)
 83	#define SUN4I_SPDIF_FSTA_TXE			BIT(14)
 84	#define SUN4I_SPDIF_FSTA_TXECNTSHT		(8)
 85	#define SUN4I_SPDIF_FSTA_RXA			BIT(6)
 86	#define SUN4I_SPDIF_FSTA_RXACNTSHT		(0)
 87
 88#define SUN4I_SPDIF_INT		(0x1C)
 89	#define SUN4I_SPDIF_INT_RXLOCKEN		BIT(18)
 90	#define SUN4I_SPDIF_INT_RXUNLOCKEN		BIT(17)
 91	#define SUN4I_SPDIF_INT_RXPARERREN		BIT(16)
 92	#define SUN4I_SPDIF_INT_TXDRQEN			BIT(7)
 93	#define SUN4I_SPDIF_INT_TXUIEN			BIT(6)
 94	#define SUN4I_SPDIF_INT_TXOIEN			BIT(5)
 95	#define SUN4I_SPDIF_INT_TXEIEN			BIT(4)
 96	#define SUN4I_SPDIF_INT_RXDRQEN			BIT(2)
 97	#define SUN4I_SPDIF_INT_RXOIEN			BIT(1)
 98	#define SUN4I_SPDIF_INT_RXAIEN			BIT(0)
 99
100#define SUN4I_SPDIF_ISTA	(0x20)
101	#define SUN4I_SPDIF_ISTA_RXLOCKSTA		BIT(18)
102	#define SUN4I_SPDIF_ISTA_RXUNLOCKSTA		BIT(17)
103	#define SUN4I_SPDIF_ISTA_RXPARERRSTA		BIT(16)
104	#define SUN4I_SPDIF_ISTA_TXUSTA			BIT(6)
105	#define SUN4I_SPDIF_ISTA_TXOSTA			BIT(5)
106	#define SUN4I_SPDIF_ISTA_TXESTA			BIT(4)
107	#define SUN4I_SPDIF_ISTA_RXOSTA			BIT(1)
108	#define SUN4I_SPDIF_ISTA_RXASTA			BIT(0)
109
110#define SUN8I_SPDIF_TXFIFO	(0x20)
111
112#define SUN4I_SPDIF_TXCNT	(0x24)
113
114#define SUN4I_SPDIF_RXCNT	(0x28)
115
116#define SUN4I_SPDIF_TXCHSTA0	(0x2C)
117	#define SUN4I_SPDIF_TXCHSTA0_CLK(v)		((v) << 28)
118	#define SUN4I_SPDIF_TXCHSTA0_SAMFREQ(v)		((v) << 24)
119	#define SUN4I_SPDIF_TXCHSTA0_SAMFREQ_MASK	GENMASK(27, 24)
120	#define SUN4I_SPDIF_TXCHSTA0_CHNUM(v)		((v) << 20)
121	#define SUN4I_SPDIF_TXCHSTA0_CHNUM_MASK		GENMASK(23, 20)
122	#define SUN4I_SPDIF_TXCHSTA0_SRCNUM(v)		((v) << 16)
123	#define SUN4I_SPDIF_TXCHSTA0_CATACOD(v)		((v) << 8)
124	#define SUN4I_SPDIF_TXCHSTA0_MODE(v)		((v) << 6)
125	#define SUN4I_SPDIF_TXCHSTA0_EMPHASIS(v)	((v) << 3)
126	#define SUN4I_SPDIF_TXCHSTA0_CP			BIT(2)
127	#define SUN4I_SPDIF_TXCHSTA0_AUDIO		BIT(1)
128	#define SUN4I_SPDIF_TXCHSTA0_PRO		BIT(0)
129
130#define SUN4I_SPDIF_TXCHSTA1	(0x30)
131	#define SUN4I_SPDIF_TXCHSTA1_CGMSA(v)		((v) << 8)
132	#define SUN4I_SPDIF_TXCHSTA1_ORISAMFREQ(v)	((v) << 4)
133	#define SUN4I_SPDIF_TXCHSTA1_ORISAMFREQ_MASK	GENMASK(7, 4)
134	#define SUN4I_SPDIF_TXCHSTA1_SAMWORDLEN(v)	((v) << 1)
135	#define SUN4I_SPDIF_TXCHSTA1_MAXWORDLEN		BIT(0)
136
137#define SUN4I_SPDIF_RXCHSTA0	(0x34)
138	#define SUN4I_SPDIF_RXCHSTA0_CLK(v)		((v) << 28)
139	#define SUN4I_SPDIF_RXCHSTA0_SAMFREQ(v)		((v) << 24)
140	#define SUN4I_SPDIF_RXCHSTA0_CHNUM(v)		((v) << 20)
141	#define SUN4I_SPDIF_RXCHSTA0_SRCNUM(v)		((v) << 16)
142	#define SUN4I_SPDIF_RXCHSTA0_CATACOD(v)		((v) << 8)
143	#define SUN4I_SPDIF_RXCHSTA0_MODE(v)		((v) << 6)
144	#define SUN4I_SPDIF_RXCHSTA0_EMPHASIS(v)	((v) << 3)
145	#define SUN4I_SPDIF_RXCHSTA0_CP			BIT(2)
146	#define SUN4I_SPDIF_RXCHSTA0_AUDIO		BIT(1)
147	#define SUN4I_SPDIF_RXCHSTA0_PRO		BIT(0)
148
149#define SUN4I_SPDIF_RXCHSTA1	(0x38)
150	#define SUN4I_SPDIF_RXCHSTA1_CGMSA(v)		((v) << 8)
151	#define SUN4I_SPDIF_RXCHSTA1_ORISAMFREQ(v)	((v) << 4)
152	#define SUN4I_SPDIF_RXCHSTA1_SAMWORDLEN(v)	((v) << 1)
153	#define SUN4I_SPDIF_RXCHSTA1_MAXWORDLEN		BIT(0)
154
155/* Defines for Sampling Frequency */
156#define SUN4I_SPDIF_SAMFREQ_44_1KHZ		0x0
157#define SUN4I_SPDIF_SAMFREQ_NOT_INDICATED	0x1
158#define SUN4I_SPDIF_SAMFREQ_48KHZ		0x2
159#define SUN4I_SPDIF_SAMFREQ_32KHZ		0x3
160#define SUN4I_SPDIF_SAMFREQ_22_05KHZ		0x4
161#define SUN4I_SPDIF_SAMFREQ_24KHZ		0x6
162#define SUN4I_SPDIF_SAMFREQ_88_2KHZ		0x8
163#define SUN4I_SPDIF_SAMFREQ_76_8KHZ		0x9
164#define SUN4I_SPDIF_SAMFREQ_96KHZ		0xa
165#define SUN4I_SPDIF_SAMFREQ_176_4KHZ		0xc
166#define SUN4I_SPDIF_SAMFREQ_192KHZ		0xe
167
168/**
169 * struct sun4i_spdif_quirks - Differences between SoC variants.
170 *
171 * @reg_dac_txdata: TX FIFO offset for DMA config.
172 * @has_reset: SoC needs reset deasserted.
173 * @val_fctl_ftx: TX FIFO flush bitmask.
174 * @mclk_multiplier: ratio of internal MCLK divider
175 * @tx_clk_name: name of TX module clock if split clock design
176 */
177struct sun4i_spdif_quirks {
178	unsigned int reg_dac_txdata;
179	bool has_reset;
180	unsigned int val_fctl_ftx;
181	unsigned int mclk_multiplier;
182	const char *tx_clk_name;
183};
184
185struct sun4i_spdif_dev {
186	struct platform_device *pdev;
187	struct clk *spdif_clk;
188	struct clk *apb_clk;
189	struct reset_control *rst;
190	struct snd_soc_dai_driver cpu_dai_drv;
191	struct regmap *regmap;
192	struct snd_dmaengine_dai_dma_data dma_params_tx;
193	const struct sun4i_spdif_quirks *quirks;
194	spinlock_t lock;
195};
196
197static void sun4i_spdif_configure(struct sun4i_spdif_dev *host)
198{
199	const struct sun4i_spdif_quirks *quirks = host->quirks;
200
201	/* soft reset SPDIF */
202	regmap_write(host->regmap, SUN4I_SPDIF_CTL, SUN4I_SPDIF_CTL_RESET);
203
204	/* flush TX FIFO */
205	regmap_update_bits(host->regmap, SUN4I_SPDIF_FCTL,
206			   quirks->val_fctl_ftx, quirks->val_fctl_ftx);
207
208	/* Valid data at the MSB of TXFIFO Register */
209	regmap_update_bits(host->regmap, SUN4I_SPDIF_FCTL,
210			   SUN4I_SPDIF_FCTL_TXIM, 0);
211
212	/* clear TX counter */
213	regmap_write(host->regmap, SUN4I_SPDIF_TXCNT, 0);
214}
215
216static void sun4i_snd_txctrl_on(struct snd_pcm_substream *substream,
217				struct sun4i_spdif_dev *host)
218{
219	if (substream->runtime->channels == 1)
220		regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
221				   SUN4I_SPDIF_TXCFG_SINGLEMOD,
222				   SUN4I_SPDIF_TXCFG_SINGLEMOD);
223
224	/* SPDIF TX ENABLE */
225	regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
226			   SUN4I_SPDIF_TXCFG_TXEN, SUN4I_SPDIF_TXCFG_TXEN);
227
228	/* DRQ ENABLE */
229	regmap_update_bits(host->regmap, SUN4I_SPDIF_INT,
230			   SUN4I_SPDIF_INT_TXDRQEN, SUN4I_SPDIF_INT_TXDRQEN);
231
232	/* Global enable */
233	regmap_update_bits(host->regmap, SUN4I_SPDIF_CTL,
234			   SUN4I_SPDIF_CTL_GEN, SUN4I_SPDIF_CTL_GEN);
235}
236
237static void sun4i_snd_txctrl_off(struct snd_pcm_substream *substream,
238				 struct sun4i_spdif_dev *host)
239{
240	/* SPDIF TX DISABLE */
241	regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
242			   SUN4I_SPDIF_TXCFG_TXEN, 0);
243
244	/* DRQ DISABLE */
245	regmap_update_bits(host->regmap, SUN4I_SPDIF_INT,
246			   SUN4I_SPDIF_INT_TXDRQEN, 0);
247
248	/* Global disable */
249	regmap_update_bits(host->regmap, SUN4I_SPDIF_CTL,
250			   SUN4I_SPDIF_CTL_GEN, 0);
251}
252
253static int sun4i_spdif_startup(struct snd_pcm_substream *substream,
254			       struct snd_soc_dai *cpu_dai)
255{
256	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
257	struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(snd_soc_rtd_to_cpu(rtd, 0));
258
259	if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
260		return -EINVAL;
261
262	sun4i_spdif_configure(host);
263
264	return 0;
265}
266
267static int sun4i_spdif_hw_params(struct snd_pcm_substream *substream,
268				 struct snd_pcm_hw_params *params,
269				 struct snd_soc_dai *cpu_dai)
270{
271	int ret = 0;
272	int fmt;
273	unsigned long rate = params_rate(params);
274	u32 mclk_div = 0;
275	unsigned int mclk = 0;
276	u32 reg_val;
277	struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
278	struct platform_device *pdev = host->pdev;
279
280	/* Add the PCM and raw data select interface */
281	switch (params_channels(params)) {
282	case 1: /* PCM mode */
283	case 2:
284		fmt = 0;
285		break;
286	case 4: /* raw data mode */
287		fmt = SUN4I_SPDIF_TXCFG_NONAUDIO;
288		break;
289	default:
290		return -EINVAL;
291	}
292
293	host->dma_params_tx.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
294	switch (params_format(params)) {
295	case SNDRV_PCM_FORMAT_S16_LE:
296		fmt |= SUN4I_SPDIF_TXCFG_FMT16BIT;
297		host->dma_params_tx.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
298		break;
299	case SNDRV_PCM_FORMAT_S20_3LE:
300		fmt |= SUN4I_SPDIF_TXCFG_FMT20BIT;
301		break;
302	case SNDRV_PCM_FORMAT_S24_LE:
303	case SNDRV_PCM_FORMAT_S32_LE:
304		fmt |= SUN4I_SPDIF_TXCFG_FMT24BIT;
305		break;
306	default:
307		return -EINVAL;
308	}
309
310	switch (rate) {
311	case 22050:
312	case 44100:
313	case 88200:
314	case 176400:
315		mclk = 22579200;
316		break;
317	case 24000:
318	case 32000:
319	case 48000:
320	case 96000:
321	case 192000:
322		mclk = 24576000;
323		break;
324	default:
325		return -EINVAL;
326	}
327	mclk *= host->quirks->mclk_multiplier;
328
329	ret = clk_set_rate(host->spdif_clk, mclk);
330	if (ret < 0) {
331		dev_err(&pdev->dev,
332			"Setting SPDIF clock rate for %d Hz failed!\n", mclk);
333		return ret;
334	}
335
336	switch (rate) {
337	case 22050:
338	case 24000:
339		mclk_div = 8;
340		break;
341	case 32000:
342		mclk_div = 6;
343		break;
344	case 44100:
345	case 48000:
346		mclk_div = 4;
347		break;
348	case 88200:
349	case 96000:
350		mclk_div = 2;
351		break;
352	case 176400:
353	case 192000:
354		mclk_div = 1;
355		break;
356	default:
357		return -EINVAL;
358	}
359	mclk_div *= host->quirks->mclk_multiplier;
360
361	reg_val = 0;
362	reg_val |= SUN4I_SPDIF_TXCFG_ASS;
363	reg_val |= fmt; /* set non audio and bit depth */
364	reg_val |= SUN4I_SPDIF_TXCFG_CHSTMODE;
365	reg_val |= SUN4I_SPDIF_TXCFG_TXRATIO(mclk_div - 1);
366	regmap_write(host->regmap, SUN4I_SPDIF_TXCFG, reg_val);
367
368	return 0;
369}
370
371static int sun4i_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
372			       struct snd_soc_dai *dai)
373{
374	int ret = 0;
375	struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(dai);
376
377	if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
378		return -EINVAL;
379
380	switch (cmd) {
381	case SNDRV_PCM_TRIGGER_START:
382	case SNDRV_PCM_TRIGGER_RESUME:
383	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
384		sun4i_snd_txctrl_on(substream, host);
385		break;
386
387	case SNDRV_PCM_TRIGGER_STOP:
388	case SNDRV_PCM_TRIGGER_SUSPEND:
389	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
390		sun4i_snd_txctrl_off(substream, host);
391		break;
392
393	default:
394		ret = -EINVAL;
395		break;
396	}
397	return ret;
398}
399
400static int sun4i_spdif_info(struct snd_kcontrol *kcontrol,
401			    struct snd_ctl_elem_info *uinfo)
402{
403	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
404	uinfo->count = 1;
405
406	return 0;
407}
408
409static int sun4i_spdif_get_status_mask(struct snd_kcontrol *kcontrol,
410				       struct snd_ctl_elem_value *ucontrol)
411{
412	u8 *status = ucontrol->value.iec958.status;
413
414	status[0] = 0xff;
415	status[1] = 0xff;
416	status[2] = 0xff;
417	status[3] = 0xff;
418	status[4] = 0xff;
419	status[5] = 0x03;
420
421	return 0;
422}
423
424static int sun4i_spdif_get_status(struct snd_kcontrol *kcontrol,
425				  struct snd_ctl_elem_value *ucontrol)
426{
427	struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
428	struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
429	u8 *status = ucontrol->value.iec958.status;
430	unsigned long flags;
431	unsigned int reg;
432
433	spin_lock_irqsave(&host->lock, flags);
434
435	regmap_read(host->regmap, SUN4I_SPDIF_TXCHSTA0, &reg);
436
437	status[0] = reg & 0xff;
438	status[1] = (reg >> 8) & 0xff;
439	status[2] = (reg >> 16) & 0xff;
440	status[3] = (reg >> 24) & 0xff;
441
442	regmap_read(host->regmap, SUN4I_SPDIF_TXCHSTA1, &reg);
443
444	status[4] = reg & 0xff;
445	status[5] = (reg >> 8) & 0x3;
446
447	spin_unlock_irqrestore(&host->lock, flags);
448
449	return 0;
450}
451
452static int sun4i_spdif_set_status(struct snd_kcontrol *kcontrol,
453				  struct snd_ctl_elem_value *ucontrol)
454{
455	struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
456	struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
457	u8 *status = ucontrol->value.iec958.status;
458	unsigned long flags;
459	unsigned int reg;
460	bool chg0, chg1;
461
462	spin_lock_irqsave(&host->lock, flags);
463
464	reg = (u32)status[3] << 24;
465	reg |= (u32)status[2] << 16;
466	reg |= (u32)status[1] << 8;
467	reg |= (u32)status[0];
468
469	regmap_update_bits_check(host->regmap, SUN4I_SPDIF_TXCHSTA0,
470				 GENMASK(31,0), reg, &chg0);
471
472	reg = (u32)status[5] << 8;
473	reg |= (u32)status[4];
474
475	regmap_update_bits_check(host->regmap, SUN4I_SPDIF_TXCHSTA1,
476				 GENMASK(9,0), reg, &chg1);
477
478	reg = SUN4I_SPDIF_TXCFG_CHSTMODE;
479	if (status[0] & IEC958_AES0_NONAUDIO)
480		reg |= SUN4I_SPDIF_TXCFG_NONAUDIO;
481
482	regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
483			   SUN4I_SPDIF_TXCFG_CHSTMODE |
484			   SUN4I_SPDIF_TXCFG_NONAUDIO, reg);
485
486	spin_unlock_irqrestore(&host->lock, flags);
487
488	return chg0 || chg1;
489}
490
491static struct snd_kcontrol_new sun4i_spdif_controls[] = {
492	{
493		.access = SNDRV_CTL_ELEM_ACCESS_READ,
494		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
495		.name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
496		.info = sun4i_spdif_info,
497		.get = sun4i_spdif_get_status_mask
498	},
499	{
500		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
501		.name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
502		.info = sun4i_spdif_info,
503		.get = sun4i_spdif_get_status,
504		.put = sun4i_spdif_set_status
505	}
506};
507
508static int sun4i_spdif_soc_dai_probe(struct snd_soc_dai *dai)
509{
510	struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(dai);
511
512	snd_soc_dai_init_dma_data(dai, &host->dma_params_tx, NULL);
513	snd_soc_add_dai_controls(dai, sun4i_spdif_controls,
514				 ARRAY_SIZE(sun4i_spdif_controls));
515
516	return 0;
517}
518
519static const struct snd_soc_dai_ops sun4i_spdif_dai_ops = {
520	.probe		= sun4i_spdif_soc_dai_probe,
521	.startup	= sun4i_spdif_startup,
522	.trigger	= sun4i_spdif_trigger,
523	.hw_params	= sun4i_spdif_hw_params,
524};
525
526static const struct regmap_config sun4i_spdif_regmap_config = {
527	.reg_bits = 32,
528	.reg_stride = 4,
529	.val_bits = 32,
530	.max_register = SUN4I_SPDIF_RXCHSTA1,
531};
532
533#define SUN4I_RATES	SNDRV_PCM_RATE_8000_192000
534
535#define SUN4I_FORMATS	(SNDRV_PCM_FMTBIT_S16_LE | \
536				SNDRV_PCM_FMTBIT_S20_3LE | \
537				SNDRV_PCM_FMTBIT_S24_LE | \
538				SNDRV_PCM_FMTBIT_S32_LE)
539
540static struct snd_soc_dai_driver sun4i_spdif_dai = {
541	.playback = {
542		.channels_min = 1,
543		.channels_max = 2,
544		.rates = SUN4I_RATES,
545		.formats = SUN4I_FORMATS,
546	},
547	.ops = &sun4i_spdif_dai_ops,
548	.name = "spdif",
549};
550
551static const struct sun4i_spdif_quirks sun4i_a10_spdif_quirks = {
552	.reg_dac_txdata	= SUN4I_SPDIF_TXFIFO,
553	.val_fctl_ftx   = SUN4I_SPDIF_FCTL_FTX,
554	.mclk_multiplier = 1,
555};
556
557static const struct sun4i_spdif_quirks sun6i_a31_spdif_quirks = {
558	.reg_dac_txdata	= SUN4I_SPDIF_TXFIFO,
559	.val_fctl_ftx   = SUN4I_SPDIF_FCTL_FTX,
560	.has_reset	= true,
561	.mclk_multiplier = 1,
562};
563
564static const struct sun4i_spdif_quirks sun8i_h3_spdif_quirks = {
565	.reg_dac_txdata	= SUN8I_SPDIF_TXFIFO,
566	.val_fctl_ftx   = SUN4I_SPDIF_FCTL_FTX,
567	.has_reset	= true,
568	.mclk_multiplier = 4,
569};
570
571static const struct sun4i_spdif_quirks sun50i_h6_spdif_quirks = {
572	.reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
573	.val_fctl_ftx   = SUN50I_H6_SPDIF_FCTL_FTX,
574	.has_reset      = true,
575	.mclk_multiplier = 1,
576};
577
578static const struct sun4i_spdif_quirks sun55i_a523_spdif_quirks = {
579	.reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
580	.val_fctl_ftx   = SUN50I_H6_SPDIF_FCTL_FTX,
581	.has_reset      = true,
582	.mclk_multiplier = 1,
583	.tx_clk_name	= "tx",
584};
585
586static const struct of_device_id sun4i_spdif_of_match[] = {
587	{
588		.compatible = "allwinner,sun4i-a10-spdif",
589		.data = &sun4i_a10_spdif_quirks,
590	},
591	{
592		.compatible = "allwinner,sun6i-a31-spdif",
593		.data = &sun6i_a31_spdif_quirks,
594	},
595	{
596		.compatible = "allwinner,sun8i-h3-spdif",
597		.data = &sun8i_h3_spdif_quirks,
598	},
599	{
600		.compatible = "allwinner,sun50i-h6-spdif",
601		.data = &sun50i_h6_spdif_quirks,
602	},
603	{
604		.compatible = "allwinner,sun50i-h616-spdif",
605		/* Essentially the same as the H6, but without RX */
606		.data = &sun50i_h6_spdif_quirks,
607	},
608	{
609		.compatible = "allwinner,sun55i-a523-spdif",
610		/*
611		 * Almost the same as H6, but has split the TX and RX clocks,
612		 * has a separate reset bit for the RX side, and has some
613		 * expanded features for the RX side.
614		 */
615		.data = &sun55i_a523_spdif_quirks,
616	},
617	{ /* sentinel */ }
618};
619MODULE_DEVICE_TABLE(of, sun4i_spdif_of_match);
620
621static const struct snd_soc_component_driver sun4i_spdif_component = {
622	.name			= "sun4i-spdif",
623	.legacy_dai_naming	= 1,
624};
625
626static int sun4i_spdif_runtime_suspend(struct device *dev)
627{
628	struct sun4i_spdif_dev *host  = dev_get_drvdata(dev);
629
630	clk_disable_unprepare(host->spdif_clk);
631	clk_disable_unprepare(host->apb_clk);
632
633	return 0;
634}
635
636static int sun4i_spdif_runtime_resume(struct device *dev)
637{
638	struct sun4i_spdif_dev *host  = dev_get_drvdata(dev);
639	int ret;
640
641	ret = clk_prepare_enable(host->spdif_clk);
642	if (ret)
643		return ret;
644	ret = clk_prepare_enable(host->apb_clk);
645	if (ret)
646		clk_disable_unprepare(host->spdif_clk);
647
648	return ret;
649}
650
651static int sun4i_spdif_probe(struct platform_device *pdev)
652{
653	struct sun4i_spdif_dev *host;
654	struct resource *res;
655	const struct sun4i_spdif_quirks *quirks;
656	int ret;
657	void __iomem *base;
658	const char *tx_clk_name = "spdif";
659
660	dev_dbg(&pdev->dev, "Entered %s\n", __func__);
661
662	host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
663	if (!host)
664		return -ENOMEM;
665
666	host->pdev = pdev;
667	spin_lock_init(&host->lock);
668
669	/* Initialize this copy of the CPU DAI driver structure */
670	memcpy(&host->cpu_dai_drv, &sun4i_spdif_dai, sizeof(sun4i_spdif_dai));
671	host->cpu_dai_drv.name = dev_name(&pdev->dev);
672
673	/* Get the addresses */
674	base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
675	if (IS_ERR(base))
676		return PTR_ERR(base);
677
678	quirks = of_device_get_match_data(&pdev->dev);
679	if (quirks == NULL) {
680		dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
681		return -ENODEV;
682	}
683	host->quirks = quirks;
684
685	host->regmap = devm_regmap_init_mmio(&pdev->dev, base,
686						&sun4i_spdif_regmap_config);
687
688	/* Clocks */
689	host->apb_clk = devm_clk_get(&pdev->dev, "apb");
690	if (IS_ERR(host->apb_clk)) {
691		dev_err(&pdev->dev, "failed to get a apb clock.\n");
692		return PTR_ERR(host->apb_clk);
693	}
694
695	if (quirks->tx_clk_name)
696		tx_clk_name = quirks->tx_clk_name;
697	host->spdif_clk = devm_clk_get(&pdev->dev, tx_clk_name);
698	if (IS_ERR(host->spdif_clk)) {
699		dev_err(&pdev->dev, "failed to get the \"%s\" clock.\n",
700			tx_clk_name);
701		return PTR_ERR(host->spdif_clk);
702	}
703
704	host->dma_params_tx.addr = res->start + quirks->reg_dac_txdata;
705	host->dma_params_tx.maxburst = 8;
706	host->dma_params_tx.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
707
708	platform_set_drvdata(pdev, host);
709
710	if (quirks->has_reset) {
711		host->rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
712								      NULL);
713		if (PTR_ERR(host->rst) == -EPROBE_DEFER) {
714			ret = -EPROBE_DEFER;
715			dev_err(&pdev->dev, "Failed to get reset: %d\n", ret);
716			return ret;
717		}
718		if (!IS_ERR(host->rst))
719			reset_control_deassert(host->rst);
720	}
721
722	ret = devm_snd_soc_register_component(&pdev->dev,
723				&sun4i_spdif_component, &sun4i_spdif_dai, 1);
724	if (ret)
725		return ret;
726
727	pm_runtime_enable(&pdev->dev);
728	if (!pm_runtime_enabled(&pdev->dev)) {
729		ret = sun4i_spdif_runtime_resume(&pdev->dev);
730		if (ret)
731			goto err_unregister;
732	}
733
734	ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
735	if (ret)
736		goto err_suspend;
737	return 0;
738err_suspend:
739	if (!pm_runtime_status_suspended(&pdev->dev))
740		sun4i_spdif_runtime_suspend(&pdev->dev);
741err_unregister:
742	pm_runtime_disable(&pdev->dev);
743	return ret;
744}
745
746static void sun4i_spdif_remove(struct platform_device *pdev)
747{
748	pm_runtime_disable(&pdev->dev);
749	if (!pm_runtime_status_suspended(&pdev->dev))
750		sun4i_spdif_runtime_suspend(&pdev->dev);
751}
752
753static const struct dev_pm_ops sun4i_spdif_pm = {
754	RUNTIME_PM_OPS(sun4i_spdif_runtime_suspend,
755		       sun4i_spdif_runtime_resume, NULL)
756};
757
758static struct platform_driver sun4i_spdif_driver = {
759	.driver		= {
760		.name	= "sun4i-spdif",
761		.of_match_table = sun4i_spdif_of_match,
762		.pm	= pm_ptr(&sun4i_spdif_pm),
763	},
764	.probe		= sun4i_spdif_probe,
765	.remove		= sun4i_spdif_remove,
766};
767
768module_platform_driver(sun4i_spdif_driver);
769
770MODULE_AUTHOR("Marcus Cooper <codekipper@gmail.com>");
771MODULE_AUTHOR("Andrea Venturi <be17068@iperbole.bo.it>");
772MODULE_DESCRIPTION("Allwinner sun4i SPDIF SoC Interface");
773MODULE_LICENSE("GPL");
774MODULE_ALIAS("platform:sun4i-spdif");