stm32_sai.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * STM32 ALSA SoC Digital Audio Interface (SAI) driver.
  4 *
  5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
  6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
  7 */
  8
  9#include <linux/bitfield.h>
 10#include <linux/clk.h>
 11#include <linux/delay.h>
 12#include <linux/module.h>
 13#include <linux/of_platform.h>
 14#include <linux/pinctrl/consumer.h>
 15#include <linux/reset.h>
 16
 17#include <sound/dmaengine_pcm.h>
 18#include <sound/core.h>
 19
 20#include "stm32_sai.h"
 21
 22static int stm32_sai_get_parent_clk(struct stm32_sai_data *sai);
 23
 24static const struct stm32_sai_conf stm32_sai_conf_f4 = {
 25	.version = STM_SAI_STM32F4,
 26	.fifo_size = 8,
 27	.has_spdif_pdm = false,
 28	.get_sai_ck_parent = stm32_sai_get_parent_clk,
 29};
 30
 31/*
 32 * Default settings for STM32H7x socs and STM32MP1x.
 33 * These default settings will be overridden if the soc provides
 34 * support of hardware configuration registers.
 35 * - STM32H7: rely on default settings
 36 * - STM32MP1: retrieve settings from registers
 37 */
 38static const struct stm32_sai_conf stm32_sai_conf_h7 = {
 39	.version = STM_SAI_STM32H7,
 40	.fifo_size = 8,
 41	.has_spdif_pdm = true,
 42	.get_sai_ck_parent = stm32_sai_get_parent_clk,
 43};
 44
 45/*
 46 * STM32MP2x:
 47 * - do not use SAI parent clock source selection
 48 * - do not use DMA burst mode
 49 */
 50static const struct stm32_sai_conf stm32_sai_conf_mp25 = {
 51	.no_dma_burst = true,
 52};
 53
 54static const struct of_device_id stm32_sai_ids[] = {
 55	{ .compatible = "st,stm32f4-sai", .data = (void *)&stm32_sai_conf_f4 },
 56	{ .compatible = "st,stm32h7-sai", .data = (void *)&stm32_sai_conf_h7 },
 57	{ .compatible = "st,stm32mp25-sai", .data = (void *)&stm32_sai_conf_mp25 },
 58	{}
 59};
 60
 61static int stm32_sai_pclk_disable(struct device *dev)
 62{
 63	struct stm32_sai_data *sai = dev_get_drvdata(dev);
 64
 65	clk_disable_unprepare(sai->pclk);
 66
 67	return 0;
 68}
 69
 70static int stm32_sai_pclk_enable(struct device *dev)
 71{
 72	struct stm32_sai_data *sai = dev_get_drvdata(dev);
 73	int ret;
 74
 75	ret = clk_prepare_enable(sai->pclk);
 76	if (ret) {
 77		dev_err(&sai->pdev->dev, "failed to enable clock: %d\n", ret);
 78		return ret;
 79	}
 80
 81	return 0;
 82}
 83
 84static int stm32_sai_sync_conf_client(struct stm32_sai_data *sai, int synci)
 85{
 86	int ret;
 87
 88	/* Enable peripheral clock to allow GCR register access */
 89	ret = stm32_sai_pclk_enable(&sai->pdev->dev);
 90	if (ret)
 91		return ret;
 92
 93	writel_relaxed(FIELD_PREP(SAI_GCR_SYNCIN_MASK, (synci - 1)), sai->base);
 94
 95	stm32_sai_pclk_disable(&sai->pdev->dev);
 96
 97	return 0;
 98}
 99
100static int stm32_sai_sync_conf_provider(struct stm32_sai_data *sai, int synco)
101{
102	u32 prev_synco;
103	int ret;
104
105	/* Enable peripheral clock to allow GCR register access */
106	ret = stm32_sai_pclk_enable(&sai->pdev->dev);
107	if (ret)
108		return ret;
109
110	dev_dbg(&sai->pdev->dev, "Set %pOFn%s as synchro provider\n",
111		sai->pdev->dev.of_node,
112		synco == STM_SAI_SYNC_OUT_A ? "A" : "B");
113
114	prev_synco = FIELD_GET(SAI_GCR_SYNCOUT_MASK, readl_relaxed(sai->base));
115	if (prev_synco != STM_SAI_SYNC_OUT_NONE && synco != prev_synco) {
116		dev_err(&sai->pdev->dev, "%pOFn%s already set as sync provider\n",
117			sai->pdev->dev.of_node,
118			prev_synco == STM_SAI_SYNC_OUT_A ? "A" : "B");
119		stm32_sai_pclk_disable(&sai->pdev->dev);
120		return -EINVAL;
121	}
122
123	writel_relaxed(FIELD_PREP(SAI_GCR_SYNCOUT_MASK, synco), sai->base);
124
125	stm32_sai_pclk_disable(&sai->pdev->dev);
126
127	return 0;
128}
129
130static int stm32_sai_set_sync(struct stm32_sai_data *sai_client,
131			      struct device_node *np_provider,
132			      int synco, int synci)
133{
134	struct platform_device *pdev = of_find_device_by_node(np_provider);
135	struct stm32_sai_data *sai_provider;
136	int ret;
137
138	if (!pdev) {
139		dev_err(&sai_client->pdev->dev,
140			"Device not found for node %pOFn\n", np_provider);
141		return -ENODEV;
142	}
143
144	sai_provider = platform_get_drvdata(pdev);
145	put_device(&pdev->dev);
146	if (!sai_provider) {
147		dev_err(&sai_client->pdev->dev,
148			"SAI sync provider data not found\n");
149		return -EINVAL;
150	}
151
152	/* Configure sync client */
153	ret = stm32_sai_sync_conf_client(sai_client, synci);
154	if (ret < 0)
155		return ret;
156
157	/* Configure sync provider */
158	return stm32_sai_sync_conf_provider(sai_provider, synco);
159}
160
161static int stm32_sai_get_parent_clk(struct stm32_sai_data *sai)
162{
163	struct device *dev = &sai->pdev->dev;
164
165	sai->clk_x8k = devm_clk_get(dev, "x8k");
166	if (IS_ERR(sai->clk_x8k))
167		return dev_err_probe(dev, PTR_ERR(sai->clk_x8k),
168				     "missing x8k parent clock\n");
169
170	sai->clk_x11k = devm_clk_get(dev, "x11k");
171	if (IS_ERR(sai->clk_x11k))
172		return dev_err_probe(dev, PTR_ERR(sai->clk_x11k),
173				     "missing x11k parent clock\n");
174
175	return 0;
176}
177
178static int stm32_sai_probe(struct platform_device *pdev)
179{
180	struct stm32_sai_data *sai;
181	const struct stm32_sai_conf *conf;
182	struct reset_control *rst;
183	u32 val;
184	int ret;
185
186	sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
187	if (!sai)
188		return -ENOMEM;
189
190	sai->pdev = pdev;
191
192	sai->base = devm_platform_ioremap_resource(pdev, 0);
193	if (IS_ERR(sai->base))
194		return PTR_ERR(sai->base);
195
196	conf = device_get_match_data(&pdev->dev);
197	if (conf)
198		memcpy(&sai->conf, (const struct stm32_sai_conf *)conf,
199		       sizeof(struct stm32_sai_conf));
200	else
201		return -EINVAL;
202
203	if (!STM_SAI_IS_F4(sai)) {
204		sai->pclk = devm_clk_get(&pdev->dev, "pclk");
205		if (IS_ERR(sai->pclk))
206			return dev_err_probe(&pdev->dev, PTR_ERR(sai->pclk),
207					     "missing bus clock pclk\n");
208	}
209
210	if (sai->conf.get_sai_ck_parent) {
211		ret = sai->conf.get_sai_ck_parent(sai);
212		if (ret)
213			return ret;
214	}
215
216	/* init irqs */
217	sai->irq = platform_get_irq(pdev, 0);
218	if (sai->irq < 0)
219		return sai->irq;
220
221	/* reset */
222	rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
223	if (IS_ERR(rst))
224		return dev_err_probe(&pdev->dev, PTR_ERR(rst),
225				     "Reset controller error\n");
226
227	reset_control_assert(rst);
228	udelay(2);
229	reset_control_deassert(rst);
230
231	/* Enable peripheral clock to allow register access */
232	ret = clk_prepare_enable(sai->pclk);
233	if (ret) {
234		dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
235		return ret;
236	}
237
238	val = FIELD_GET(SAI_IDR_ID_MASK,
239			readl_relaxed(sai->base + STM_SAI_IDR));
240	if (val == SAI_IPIDR_NUMBER) {
241		val = readl_relaxed(sai->base + STM_SAI_HWCFGR);
242		sai->conf.fifo_size = FIELD_GET(SAI_HWCFGR_FIFO_SIZE, val);
243		sai->conf.has_spdif_pdm = !!FIELD_GET(SAI_HWCFGR_SPDIF_PDM,
244						      val);
245
246		val = readl_relaxed(sai->base + STM_SAI_VERR);
247		sai->conf.version = val;
248
249		dev_dbg(&pdev->dev, "SAI version: %lu.%lu registered\n",
250			FIELD_GET(SAI_VERR_MAJ_MASK, val),
251			FIELD_GET(SAI_VERR_MIN_MASK, val));
252	}
253	clk_disable_unprepare(sai->pclk);
254
255	sai->set_sync = &stm32_sai_set_sync;
256	platform_set_drvdata(pdev, sai);
257
258	return devm_of_platform_populate(&pdev->dev);
259}
260
261/*
262 * When pins are shared by two sai sub instances, pins have to be defined
263 * in sai parent node. In this case, pins state is not managed by alsa fw.
264 * These pins are managed in suspend/resume callbacks.
265 */
266static int stm32_sai_suspend(struct device *dev)
267{
268	struct stm32_sai_data *sai = dev_get_drvdata(dev);
269	int ret;
270
271	ret = stm32_sai_pclk_enable(dev);
272	if (ret)
273		return ret;
274
275	sai->gcr = readl_relaxed(sai->base);
276	stm32_sai_pclk_disable(dev);
277
278	return pinctrl_pm_select_sleep_state(dev);
279}
280
281static int stm32_sai_resume(struct device *dev)
282{
283	struct stm32_sai_data *sai = dev_get_drvdata(dev);
284	int ret;
285
286	ret = stm32_sai_pclk_enable(dev);
287	if (ret)
288		return ret;
289
290	writel_relaxed(sai->gcr, sai->base);
291	stm32_sai_pclk_disable(dev);
292
293	return pinctrl_pm_select_default_state(dev);
294}
295
296static const struct dev_pm_ops stm32_sai_pm_ops = {
297	SYSTEM_SLEEP_PM_OPS(stm32_sai_suspend, stm32_sai_resume)
298};
299
300MODULE_DEVICE_TABLE(of, stm32_sai_ids);
301
302static struct platform_driver stm32_sai_driver = {
303	.driver = {
304		.name = "st,stm32-sai",
305		.of_match_table = stm32_sai_ids,
306		.pm = pm_ptr(&stm32_sai_pm_ops),
307	},
308	.probe = stm32_sai_probe,
309};
310
311module_platform_driver(stm32_sai_driver);
312
313MODULE_DESCRIPTION("STM32 Soc SAI Interface");
314MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>");
315MODULE_ALIAS("platform:st,stm32-sai");
316MODULE_LICENSE("GPL v2");