stm32_i2s.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 *  STM32 ALSA SoC Digital Audio Interface (I2S) driver.
   4 *
   5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
   7 */
   8
   9#include <linux/bitfield.h>
  10#include <linux/clk.h>
  11#include <linux/clk-provider.h>
  12#include <linux/delay.h>
  13#include <linux/module.h>
  14#include <linux/of_irq.h>
  15#include <linux/of_platform.h>
  16#include <linux/pm_runtime.h>
  17#include <linux/regmap.h>
  18#include <linux/reset.h>
  19#include <linux/spinlock.h>
  20
  21#include <sound/dmaengine_pcm.h>
  22#include <sound/pcm_params.h>
  23
  24#define STM32_I2S_CR1_REG	0x0
  25#define STM32_I2S_CFG1_REG	0x08
  26#define STM32_I2S_CFG2_REG	0x0C
  27#define STM32_I2S_IER_REG	0x10
  28#define STM32_I2S_SR_REG	0x14
  29#define STM32_I2S_IFCR_REG	0x18
  30#define STM32_I2S_TXDR_REG	0X20
  31#define STM32_I2S_RXDR_REG	0x30
  32#define STM32_I2S_CGFR_REG	0X50
  33#define STM32_I2S_HWCFGR_REG	0x3F0
  34#define STM32_I2S_VERR_REG	0x3F4
  35#define STM32_I2S_IPIDR_REG	0x3F8
  36#define STM32_I2S_SIDR_REG	0x3FC
  37
  38/* Bit definition for SPI2S_CR1 register */
  39#define I2S_CR1_SPE		BIT(0)
  40#define I2S_CR1_CSTART		BIT(9)
  41#define I2S_CR1_CSUSP		BIT(10)
  42#define I2S_CR1_HDDIR		BIT(11)
  43#define I2S_CR1_SSI		BIT(12)
  44#define I2S_CR1_CRC33_17	BIT(13)
  45#define I2S_CR1_RCRCI		BIT(14)
  46#define I2S_CR1_TCRCI		BIT(15)
  47
  48/* Bit definition for SPI_CFG2 register */
  49#define I2S_CFG2_IOSWP_SHIFT	15
  50#define I2S_CFG2_IOSWP		BIT(I2S_CFG2_IOSWP_SHIFT)
  51#define I2S_CFG2_LSBFRST	BIT(23)
  52#define I2S_CFG2_AFCNTR		BIT(31)
  53
  54/* Bit definition for SPI_CFG1 register */
  55#define I2S_CFG1_FTHVL_SHIFT	5
  56#define I2S_CFG1_FTHVL_MASK	GENMASK(8, I2S_CFG1_FTHVL_SHIFT)
  57#define I2S_CFG1_FTHVL_SET(x)	((x) << I2S_CFG1_FTHVL_SHIFT)
  58
  59#define I2S_CFG1_TXDMAEN	BIT(15)
  60#define I2S_CFG1_RXDMAEN	BIT(14)
  61
  62/* Bit definition for SPI2S_IER register */
  63#define I2S_IER_RXPIE		BIT(0)
  64#define I2S_IER_TXPIE		BIT(1)
  65#define I2S_IER_DPXPIE		BIT(2)
  66#define I2S_IER_EOTIE		BIT(3)
  67#define I2S_IER_TXTFIE		BIT(4)
  68#define I2S_IER_UDRIE		BIT(5)
  69#define I2S_IER_OVRIE		BIT(6)
  70#define I2S_IER_CRCEIE		BIT(7)
  71#define I2S_IER_TIFREIE		BIT(8)
  72#define I2S_IER_MODFIE		BIT(9)
  73#define I2S_IER_TSERFIE		BIT(10)
  74
  75/* Bit definition for SPI2S_SR register */
  76#define I2S_SR_RXP		BIT(0)
  77#define I2S_SR_TXP		BIT(1)
  78#define I2S_SR_DPXP		BIT(2)
  79#define I2S_SR_EOT		BIT(3)
  80#define I2S_SR_TXTF		BIT(4)
  81#define I2S_SR_UDR		BIT(5)
  82#define I2S_SR_OVR		BIT(6)
  83#define I2S_SR_CRCERR		BIT(7)
  84#define I2S_SR_TIFRE		BIT(8)
  85#define I2S_SR_MODF		BIT(9)
  86#define I2S_SR_TSERF		BIT(10)
  87#define I2S_SR_SUSP		BIT(11)
  88#define I2S_SR_TXC		BIT(12)
  89#define I2S_SR_RXPLVL		GENMASK(14, 13)
  90#define I2S_SR_RXWNE		BIT(15)
  91
  92#define I2S_SR_MASK		GENMASK(15, 0)
  93
  94/* Bit definition for SPI_IFCR register */
  95#define I2S_IFCR_EOTC		BIT(3)
  96#define I2S_IFCR_TXTFC		BIT(4)
  97#define I2S_IFCR_UDRC		BIT(5)
  98#define I2S_IFCR_OVRC		BIT(6)
  99#define I2S_IFCR_CRCEC		BIT(7)
 100#define I2S_IFCR_TIFREC		BIT(8)
 101#define I2S_IFCR_MODFC		BIT(9)
 102#define I2S_IFCR_TSERFC		BIT(10)
 103#define I2S_IFCR_SUSPC		BIT(11)
 104
 105#define I2S_IFCR_MASK		GENMASK(11, 3)
 106
 107/* Bit definition for SPI_I2SCGFR register */
 108#define I2S_CGFR_I2SMOD		BIT(0)
 109
 110#define I2S_CGFR_I2SCFG_SHIFT	1
 111#define I2S_CGFR_I2SCFG_MASK	GENMASK(3, I2S_CGFR_I2SCFG_SHIFT)
 112#define I2S_CGFR_I2SCFG_SET(x)	((x) << I2S_CGFR_I2SCFG_SHIFT)
 113
 114#define I2S_CGFR_I2SSTD_SHIFT	4
 115#define I2S_CGFR_I2SSTD_MASK	GENMASK(5, I2S_CGFR_I2SSTD_SHIFT)
 116#define I2S_CGFR_I2SSTD_SET(x)	((x) << I2S_CGFR_I2SSTD_SHIFT)
 117
 118#define I2S_CGFR_PCMSYNC	BIT(7)
 119
 120#define I2S_CGFR_DATLEN_SHIFT	8
 121#define I2S_CGFR_DATLEN_MASK	GENMASK(9, I2S_CGFR_DATLEN_SHIFT)
 122#define I2S_CGFR_DATLEN_SET(x)	((x) << I2S_CGFR_DATLEN_SHIFT)
 123
 124#define I2S_CGFR_CHLEN_SHIFT	10
 125#define I2S_CGFR_CHLEN		BIT(I2S_CGFR_CHLEN_SHIFT)
 126#define I2S_CGFR_CKPOL		BIT(11)
 127#define I2S_CGFR_FIXCH		BIT(12)
 128#define I2S_CGFR_WSINV		BIT(13)
 129#define I2S_CGFR_DATFMT		BIT(14)
 130
 131#define I2S_CGFR_I2SDIV_SHIFT	16
 132#define I2S_CGFR_I2SDIV_BIT_H	23
 133#define I2S_CGFR_I2SDIV_MASK	GENMASK(I2S_CGFR_I2SDIV_BIT_H,\
 134				I2S_CGFR_I2SDIV_SHIFT)
 135#define I2S_CGFR_I2SDIV_SET(x)	((x) << I2S_CGFR_I2SDIV_SHIFT)
 136#define	I2S_CGFR_I2SDIV_MAX	((1 << (I2S_CGFR_I2SDIV_BIT_H -\
 137				I2S_CGFR_I2SDIV_SHIFT)) - 1)
 138
 139#define I2S_CGFR_ODD_SHIFT	24
 140#define I2S_CGFR_ODD		BIT(I2S_CGFR_ODD_SHIFT)
 141#define I2S_CGFR_MCKOE		BIT(25)
 142
 143/* Registers below apply to I2S version 1.1 and more */
 144
 145/* Bit definition for SPI_HWCFGR register */
 146#define I2S_HWCFGR_I2S_SUPPORT_MASK	GENMASK(15, 12)
 147
 148/* Bit definition for SPI_VERR register */
 149#define I2S_VERR_MIN_MASK	GENMASK(3, 0)
 150#define I2S_VERR_MAJ_MASK	GENMASK(7, 4)
 151
 152/* Bit definition for SPI_IPIDR register */
 153#define I2S_IPIDR_ID_MASK	GENMASK(31, 0)
 154
 155/* Bit definition for SPI_SIDR register */
 156#define I2S_SIDR_ID_MASK	GENMASK(31, 0)
 157
 158#define I2S_IPIDR_NUMBER	0x00130022
 159
 160enum i2s_master_mode {
 161	I2S_MS_NOT_SET,
 162	I2S_MS_MASTER,
 163	I2S_MS_SLAVE,
 164};
 165
 166enum i2s_mode {
 167	I2S_I2SMOD_TX_SLAVE,
 168	I2S_I2SMOD_RX_SLAVE,
 169	I2S_I2SMOD_TX_MASTER,
 170	I2S_I2SMOD_RX_MASTER,
 171	I2S_I2SMOD_FD_SLAVE,
 172	I2S_I2SMOD_FD_MASTER,
 173};
 174
 175enum i2s_fifo_th {
 176	I2S_FIFO_TH_NONE,
 177	I2S_FIFO_TH_ONE_QUARTER,
 178	I2S_FIFO_TH_HALF,
 179	I2S_FIFO_TH_THREE_QUARTER,
 180	I2S_FIFO_TH_FULL,
 181};
 182
 183enum i2s_std {
 184	I2S_STD_I2S,
 185	I2S_STD_LEFT_J,
 186	I2S_STD_RIGHT_J,
 187	I2S_STD_DSP,
 188};
 189
 190enum i2s_datlen {
 191	I2S_I2SMOD_DATLEN_16,
 192	I2S_I2SMOD_DATLEN_24,
 193	I2S_I2SMOD_DATLEN_32,
 194};
 195
 196#define STM32_I2S_FIFO_SIZE		16
 197
 198#define STM32_I2S_IS_MASTER(x)		((x)->ms_flg == I2S_MS_MASTER)
 199#define STM32_I2S_IS_SLAVE(x)		((x)->ms_flg == I2S_MS_SLAVE)
 200
 201#define STM32_I2S_NAME_LEN		32
 202#define STM32_I2S_RATE_11K		11025
 203#define STM32_I2S_MAX_SAMPLE_RATE_8K	192000
 204#define STM32_I2S_MAX_SAMPLE_RATE_11K	176400
 205#define STM32_I2S_CLK_RATE_TOLERANCE	1000 /* ppm */
 206
 207/**
 208 * struct stm32_i2s_data - private data of I2S
 209 * @conf: I2S configuration pointer
 210 * @regmap: I2S register map pointer
 211 * @pdev: device data pointer
 212 * @dai_drv: DAI driver pointer
 213 * @dma_data_tx: dma configuration data for tx channel
 214 * @dma_data_rx: dma configuration data for tx channel
 215 * @substream: PCM substream data pointer
 216 * @i2sclk: kernel clock feeding the I2S clock generator
 217 * @i2smclk: master clock from I2S mclk provider
 218 * @pclk: peripheral clock driving bus interface
 219 * @x8kclk: I2S parent clock for sampling frequencies multiple of 8kHz
 220 * @x11kclk: I2S parent clock for sampling frequencies multiple of 11kHz
 221 * @base:  mmio register base virtual address
 222 * @phys_addr: I2S registers physical base address
 223 * @lock_fd: lock to manage race conditions in full duplex mode
 224 * @irq_lock: prevent race condition with IRQ
 225 * @mclk_rate: master clock frequency (Hz)
 226 * @fmt: DAI protocol
 227 * @divider: prescaler division ratio
 228 * @div: prescaler div field
 229 * @odd: prescaler odd field
 230 * @i2s_clk_flg: flag set while exclusivity on I2S kernel clock is active
 231 * @refcount: keep count of opened streams on I2S
 232 * @ms_flg: master mode flag.
 233 * @set_i2s_clk_rate: set I2S kernel clock rate
 234 * @put_i2s_clk_rate: put I2S kernel clock rate
 235 */
 236struct stm32_i2s_data {
 237	const struct stm32_i2s_conf *conf;
 238	struct regmap *regmap;
 239	struct platform_device *pdev;
 240	struct snd_soc_dai_driver *dai_drv;
 241	struct snd_dmaengine_dai_dma_data dma_data_tx;
 242	struct snd_dmaengine_dai_dma_data dma_data_rx;
 243	struct snd_pcm_substream *substream;
 244	struct clk *i2sclk;
 245	struct clk *i2smclk;
 246	struct clk *pclk;
 247	struct clk *x8kclk;
 248	struct clk *x11kclk;
 249	void __iomem *base;
 250	dma_addr_t phys_addr;
 251	spinlock_t lock_fd; /* Manage race conditions for full duplex */
 252	spinlock_t irq_lock; /* used to prevent race condition with IRQ */
 253	unsigned int mclk_rate;
 254	unsigned int fmt;
 255	unsigned int divider;
 256	unsigned int div;
 257	bool odd;
 258	bool i2s_clk_flg;
 259	int refcount;
 260	int ms_flg;
 261	int (*set_i2s_clk_rate)(struct stm32_i2s_data *i2s, unsigned int rate);
 262	void (*put_i2s_clk_rate)(struct stm32_i2s_data *i2s);
 263};
 264
 265/**
 266 * struct stm32_i2s_conf - I2S configuration
 267 * @regmap_conf: regmap configuration pointer
 268 * @get_i2s_clk_parent: get parent clock of I2S kernel clock
 269 */
 270struct stm32_i2s_conf {
 271	const struct regmap_config *regmap_conf;
 272	int (*get_i2s_clk_parent)(struct stm32_i2s_data *i2s);
 273};
 274
 275struct stm32_i2smclk_data {
 276	struct clk_hw hw;
 277	unsigned long freq;
 278	struct stm32_i2s_data *i2s_data;
 279};
 280
 281#define to_mclk_data(_hw) container_of(_hw, struct stm32_i2smclk_data, hw)
 282
 283static int stm32_i2s_get_parent_clk(struct stm32_i2s_data *i2s);
 284
 285static int stm32_i2s_calc_clk_div(struct stm32_i2s_data *i2s,
 286				  unsigned long input_rate,
 287				  unsigned long output_rate)
 288{
 289	unsigned int ratio, div, divider = 1;
 290	bool odd;
 291
 292	ratio = DIV_ROUND_CLOSEST(input_rate, output_rate);
 293
 294	/* Check the parity of the divider */
 295	odd = ratio & 0x1;
 296
 297	/* Compute the div prescaler */
 298	div = ratio >> 1;
 299
 300	/* If div is 0 actual divider is 1 */
 301	if (div) {
 302		divider = ((2 * div) + odd);
 303		dev_dbg(&i2s->pdev->dev, "Divider: 2*%d(div)+%d(odd) = %d\n",
 304			div, odd, divider);
 305	}
 306
 307	/* Division by three is not allowed by I2S prescaler */
 308	if ((div == 1 && odd) || div > I2S_CGFR_I2SDIV_MAX) {
 309		dev_err(&i2s->pdev->dev, "Wrong divider setting\n");
 310		return -EINVAL;
 311	}
 312
 313	if (input_rate % divider)
 314		dev_dbg(&i2s->pdev->dev,
 315			"Rate not accurate. requested (%ld), actual (%ld)\n",
 316			output_rate, input_rate / divider);
 317
 318	i2s->div = div;
 319	i2s->odd = odd;
 320	i2s->divider = divider;
 321
 322	return 0;
 323}
 324
 325static int stm32_i2s_set_clk_div(struct stm32_i2s_data *i2s)
 326{
 327	u32 cgfr, cgfr_mask;
 328
 329	cgfr = I2S_CGFR_I2SDIV_SET(i2s->div) | (i2s->odd << I2S_CGFR_ODD_SHIFT);
 330	cgfr_mask = I2S_CGFR_I2SDIV_MASK | I2S_CGFR_ODD;
 331
 332	return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 333				  cgfr_mask, cgfr);
 334}
 335
 336static bool stm32_i2s_rate_accurate(struct stm32_i2s_data *i2s,
 337				    unsigned int max_rate, unsigned int rate)
 338{
 339	struct platform_device *pdev = i2s->pdev;
 340	u64 delta, dividend;
 341	int ratio;
 342
 343	if (!rate) {
 344		dev_err(&pdev->dev, "Unexpected null rate\n");
 345		return false;
 346	}
 347
 348	ratio = DIV_ROUND_CLOSEST(max_rate, rate);
 349	if (!ratio)
 350		return false;
 351
 352	dividend = mul_u32_u32(1000000, abs(max_rate - (ratio * rate)));
 353	delta = div_u64(dividend, max_rate);
 354
 355	if (delta <= STM32_I2S_CLK_RATE_TOLERANCE)
 356		return true;
 357
 358	dev_dbg(&pdev->dev, "Rate [%u] not accurate\n", rate);
 359
 360	return false;
 361}
 362
 363static int stm32_i2s_set_parent_clock(struct stm32_i2s_data *i2s,
 364				      unsigned int rate)
 365{
 366	struct platform_device *pdev = i2s->pdev;
 367	struct clk *parent_clk;
 368	int ret;
 369
 370	if (!(rate % STM32_I2S_RATE_11K))
 371		parent_clk = i2s->x11kclk;
 372	else
 373		parent_clk = i2s->x8kclk;
 374
 375	ret = clk_set_parent(i2s->i2sclk, parent_clk);
 376	if (ret)
 377		dev_err(&pdev->dev,
 378			"Error %d setting i2sclk parent clock\n", ret);
 379
 380	return ret;
 381}
 382
 383static void stm32_i2s_put_parent_rate(struct stm32_i2s_data *i2s)
 384{
 385	if (i2s->i2s_clk_flg) {
 386		i2s->i2s_clk_flg = false;
 387		clk_rate_exclusive_put(i2s->i2sclk);
 388	}
 389}
 390
 391static int stm32_i2s_set_parent_rate(struct stm32_i2s_data *i2s,
 392				     unsigned int rate)
 393{
 394	struct platform_device *pdev = i2s->pdev;
 395	unsigned int i2s_clk_rate, i2s_clk_max_rate, i2s_curr_rate, i2s_new_rate;
 396	int ret, div;
 397
 398	/*
 399	 * Set maximum expected kernel clock frequency
 400	 * - mclk on:
 401	 *   f_i2s_ck = MCKDIV * mclk-fs * fs
 402	 *   Here typical 256 ratio is assumed for mclk-fs
 403	 * - mclk off:
 404	 *   f_i2s_ck = MCKDIV * FRL * fs
 405	 *   Where FRL=[16,32], MCKDIV=[1..256]
 406	 *   f_i2s_ck = i2s_clk_max_rate * 32 / 256
 407	 */
 408	if (!(rate % STM32_I2S_RATE_11K))
 409		i2s_clk_max_rate = STM32_I2S_MAX_SAMPLE_RATE_11K * 256;
 410	else
 411		i2s_clk_max_rate = STM32_I2S_MAX_SAMPLE_RATE_8K * 256;
 412
 413	if (!i2s->i2smclk)
 414		i2s_clk_max_rate /= 8;
 415
 416	/* Request exclusivity, as the clock may be shared by I2S instances */
 417	clk_rate_exclusive_get(i2s->i2sclk);
 418	i2s->i2s_clk_flg = true;
 419
 420	/*
 421	 * Check current kernel clock rate. If it gives the expected accuracy
 422	 * return immediately.
 423	 */
 424	i2s_curr_rate = clk_get_rate(i2s->i2sclk);
 425	if (stm32_i2s_rate_accurate(i2s, i2s_clk_max_rate, i2s_curr_rate))
 426		return 0;
 427
 428	/*
 429	 * Otherwise try to set the maximum rate and check the new actual rate.
 430	 * If the new rate does not give the expected accuracy, try to set
 431	 * lower rates for the kernel clock.
 432	 */
 433	i2s_clk_rate = i2s_clk_max_rate;
 434	div = 1;
 435	do {
 436		/* Check new rate accuracy. Return if ok */
 437		i2s_new_rate = clk_round_rate(i2s->i2sclk, i2s_clk_rate);
 438		if (stm32_i2s_rate_accurate(i2s, i2s_clk_rate, i2s_new_rate)) {
 439			ret = clk_set_rate(i2s->i2sclk, i2s_clk_rate);
 440			if (ret) {
 441				dev_err(&pdev->dev, "Error %d setting i2s_clk_rate rate. %s",
 442					ret, ret == -EBUSY ?
 443					"Active stream rates may be in conflict\n" : "\n");
 444				goto err;
 445			}
 446
 447			return 0;
 448		}
 449
 450		/* Try a lower frequency */
 451		div++;
 452		i2s_clk_rate = i2s_clk_max_rate / div;
 453	} while (i2s_clk_rate > rate);
 454
 455	/* no accurate rate found */
 456	dev_err(&pdev->dev, "Failed to find an accurate rate");
 457
 458err:
 459	stm32_i2s_put_parent_rate(i2s);
 460
 461	return -EINVAL;
 462}
 463
 464static int stm32_i2smclk_determine_rate(struct clk_hw *hw,
 465					struct clk_rate_request *req)
 466{
 467	struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
 468	struct stm32_i2s_data *i2s = mclk->i2s_data;
 469	int ret;
 470
 471	ret = stm32_i2s_calc_clk_div(i2s, req->best_parent_rate, req->rate);
 472	if (ret)
 473		return ret;
 474
 475	mclk->freq = req->best_parent_rate / i2s->divider;
 476
 477	req->rate = mclk->freq;
 478
 479	return 0;
 480}
 481
 482static unsigned long stm32_i2smclk_recalc_rate(struct clk_hw *hw,
 483					       unsigned long parent_rate)
 484{
 485	struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
 486
 487	return mclk->freq;
 488}
 489
 490static int stm32_i2smclk_set_rate(struct clk_hw *hw, unsigned long rate,
 491				  unsigned long parent_rate)
 492{
 493	struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
 494	struct stm32_i2s_data *i2s = mclk->i2s_data;
 495	int ret;
 496
 497	ret = stm32_i2s_calc_clk_div(i2s, parent_rate, rate);
 498	if (ret)
 499		return ret;
 500
 501	ret = stm32_i2s_set_clk_div(i2s);
 502	if (ret)
 503		return ret;
 504
 505	mclk->freq = rate;
 506
 507	return 0;
 508}
 509
 510static int stm32_i2smclk_enable(struct clk_hw *hw)
 511{
 512	struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
 513	struct stm32_i2s_data *i2s = mclk->i2s_data;
 514
 515	dev_dbg(&i2s->pdev->dev, "Enable master clock\n");
 516
 517	return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 518				    I2S_CGFR_MCKOE, I2S_CGFR_MCKOE);
 519}
 520
 521static void stm32_i2smclk_disable(struct clk_hw *hw)
 522{
 523	struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
 524	struct stm32_i2s_data *i2s = mclk->i2s_data;
 525
 526	dev_dbg(&i2s->pdev->dev, "Disable master clock\n");
 527
 528	regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, I2S_CGFR_MCKOE, 0);
 529}
 530
 531static const struct clk_ops mclk_ops = {
 532	.enable = stm32_i2smclk_enable,
 533	.disable = stm32_i2smclk_disable,
 534	.recalc_rate = stm32_i2smclk_recalc_rate,
 535	.determine_rate = stm32_i2smclk_determine_rate,
 536	.set_rate = stm32_i2smclk_set_rate,
 537};
 538
 539static int stm32_i2s_add_mclk_provider(struct stm32_i2s_data *i2s)
 540{
 541	struct clk_hw *hw;
 542	struct stm32_i2smclk_data *mclk;
 543	struct device *dev = &i2s->pdev->dev;
 544	const char *pname = __clk_get_name(i2s->i2sclk);
 545	char *mclk_name, *p, *s = (char *)pname;
 546	int ret, i = 0;
 547
 548	mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL);
 549	if (!mclk)
 550		return -ENOMEM;
 551
 552	mclk_name = devm_kcalloc(dev, sizeof(char),
 553				 STM32_I2S_NAME_LEN, GFP_KERNEL);
 554	if (!mclk_name)
 555		return -ENOMEM;
 556
 557	/*
 558	 * Forge mclk clock name from parent clock name and suffix.
 559	 * String after "_" char is stripped in parent name.
 560	 */
 561	p = mclk_name;
 562	while (*s && *s != '_' && (i < (STM32_I2S_NAME_LEN - 7))) {
 563		*p++ = *s++;
 564		i++;
 565	}
 566	strcat(p, "_mclk");
 567
 568	mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0);
 569	mclk->i2s_data = i2s;
 570	hw = &mclk->hw;
 571
 572	dev_dbg(dev, "Register master clock %s\n", mclk_name);
 573	ret = devm_clk_hw_register(&i2s->pdev->dev, hw);
 574	if (ret) {
 575		dev_err(dev, "mclk register fails with error %d\n", ret);
 576		return ret;
 577	}
 578	i2s->i2smclk = hw->clk;
 579
 580	/* register mclk provider */
 581	return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
 582}
 583
 584static irqreturn_t stm32_i2s_isr(int irq, void *devid)
 585{
 586	struct stm32_i2s_data *i2s = (struct stm32_i2s_data *)devid;
 587	struct platform_device *pdev = i2s->pdev;
 588	u32 sr, ier;
 589	unsigned long flags;
 590	int err = 0;
 591
 592	regmap_read(i2s->regmap, STM32_I2S_SR_REG, &sr);
 593	regmap_read(i2s->regmap, STM32_I2S_IER_REG, &ier);
 594
 595	flags = sr & ier;
 596	if (!flags) {
 597		dev_dbg(&pdev->dev, "Spurious IRQ sr=0x%08x, ier=0x%08x\n",
 598			sr, ier);
 599		return IRQ_NONE;
 600	}
 601
 602	regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
 603			  I2S_IFCR_MASK, flags);
 604
 605	if (flags & I2S_SR_OVR) {
 606		dev_dbg(&pdev->dev, "Overrun\n");
 607		err = 1;
 608	}
 609
 610	if (flags & I2S_SR_UDR) {
 611		dev_dbg(&pdev->dev, "Underrun\n");
 612		err = 1;
 613	}
 614
 615	if (flags & I2S_SR_TIFRE)
 616		dev_dbg(&pdev->dev, "Frame error\n");
 617
 618	spin_lock(&i2s->irq_lock);
 619	if (err && i2s->substream)
 620		snd_pcm_stop_xrun(i2s->substream);
 621	spin_unlock(&i2s->irq_lock);
 622
 623	return IRQ_HANDLED;
 624}
 625
 626static bool stm32_i2s_readable_reg(struct device *dev, unsigned int reg)
 627{
 628	switch (reg) {
 629	case STM32_I2S_CR1_REG:
 630	case STM32_I2S_CFG1_REG:
 631	case STM32_I2S_CFG2_REG:
 632	case STM32_I2S_IER_REG:
 633	case STM32_I2S_SR_REG:
 634	case STM32_I2S_RXDR_REG:
 635	case STM32_I2S_CGFR_REG:
 636	case STM32_I2S_HWCFGR_REG:
 637	case STM32_I2S_VERR_REG:
 638	case STM32_I2S_IPIDR_REG:
 639	case STM32_I2S_SIDR_REG:
 640		return true;
 641	default:
 642		return false;
 643	}
 644}
 645
 646static bool stm32_i2s_volatile_reg(struct device *dev, unsigned int reg)
 647{
 648	switch (reg) {
 649	case STM32_I2S_SR_REG:
 650	case STM32_I2S_RXDR_REG:
 651		return true;
 652	default:
 653		return false;
 654	}
 655}
 656
 657static bool stm32_i2s_writeable_reg(struct device *dev, unsigned int reg)
 658{
 659	switch (reg) {
 660	case STM32_I2S_CR1_REG:
 661	case STM32_I2S_CFG1_REG:
 662	case STM32_I2S_CFG2_REG:
 663	case STM32_I2S_IER_REG:
 664	case STM32_I2S_IFCR_REG:
 665	case STM32_I2S_TXDR_REG:
 666	case STM32_I2S_CGFR_REG:
 667		return true;
 668	default:
 669		return false;
 670	}
 671}
 672
 673static int stm32_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
 674{
 675	struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 676	u32 cgfr;
 677	u32 cgfr_mask =  I2S_CGFR_I2SSTD_MASK | I2S_CGFR_CKPOL |
 678			 I2S_CGFR_WSINV | I2S_CGFR_I2SCFG_MASK;
 679
 680	dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
 681
 682	/*
 683	 * winv = 0 : default behavior (high/low) for all standards
 684	 * ckpol = 0 for all standards.
 685	 */
 686	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 687	case SND_SOC_DAIFMT_I2S:
 688		cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_I2S);
 689		break;
 690	case SND_SOC_DAIFMT_MSB:
 691		cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_LEFT_J);
 692		break;
 693	case SND_SOC_DAIFMT_LSB:
 694		cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_RIGHT_J);
 695		break;
 696	case SND_SOC_DAIFMT_DSP_A:
 697		cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_DSP);
 698		break;
 699	/* DSP_B not mapped on I2S PCM long format. 1 bit offset does not fit */
 700	default:
 701		dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
 702			fmt & SND_SOC_DAIFMT_FORMAT_MASK);
 703		return -EINVAL;
 704	}
 705
 706	/* DAI clock strobing */
 707	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 708	case SND_SOC_DAIFMT_NB_NF:
 709		break;
 710	case SND_SOC_DAIFMT_IB_NF:
 711		cgfr |= I2S_CGFR_CKPOL;
 712		break;
 713	case SND_SOC_DAIFMT_NB_IF:
 714		cgfr |= I2S_CGFR_WSINV;
 715		break;
 716	case SND_SOC_DAIFMT_IB_IF:
 717		cgfr |= I2S_CGFR_CKPOL;
 718		cgfr |= I2S_CGFR_WSINV;
 719		break;
 720	default:
 721		dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
 722			fmt & SND_SOC_DAIFMT_INV_MASK);
 723		return -EINVAL;
 724	}
 725
 726	/* DAI clock master masks */
 727	switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
 728	case SND_SOC_DAIFMT_BC_FC:
 729		i2s->ms_flg = I2S_MS_SLAVE;
 730		break;
 731	case SND_SOC_DAIFMT_BP_FP:
 732		i2s->ms_flg = I2S_MS_MASTER;
 733		break;
 734	default:
 735		dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
 736			fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK);
 737		return -EINVAL;
 738	}
 739
 740	i2s->fmt = fmt;
 741	return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 742				  cgfr_mask, cgfr);
 743}
 744
 745static int stm32_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
 746				int clk_id, unsigned int freq, int dir)
 747{
 748	struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 749	int ret = 0;
 750
 751	dev_dbg(cpu_dai->dev, "I2S MCLK frequency is %uHz. mode: %s, dir: %s\n",
 752		freq, STM32_I2S_IS_MASTER(i2s) ? "master" : "slave",
 753		dir ? "output" : "input");
 754
 755	/* MCLK generation is available only in master mode */
 756	if (dir == SND_SOC_CLOCK_OUT && STM32_I2S_IS_MASTER(i2s)) {
 757		if (!i2s->i2smclk) {
 758			dev_dbg(cpu_dai->dev, "No MCLK registered\n");
 759			return 0;
 760		}
 761
 762		/* Assume shutdown if requested frequency is 0Hz */
 763		if (!freq) {
 764			/* Release mclk rate only if rate was actually set */
 765			if (i2s->mclk_rate) {
 766				clk_rate_exclusive_put(i2s->i2smclk);
 767				i2s->mclk_rate = 0;
 768			}
 769
 770			if (i2s->put_i2s_clk_rate)
 771				i2s->put_i2s_clk_rate(i2s);
 772
 773			return regmap_update_bits(i2s->regmap,
 774						  STM32_I2S_CGFR_REG,
 775						  I2S_CGFR_MCKOE, 0);
 776		}
 777		/* If master clock is used, set parent clock now */
 778		ret = i2s->set_i2s_clk_rate(i2s, freq);
 779		if (ret)
 780			return ret;
 781		ret = clk_set_rate_exclusive(i2s->i2smclk, freq);
 782		if (ret) {
 783			dev_err(cpu_dai->dev, "Could not set mclk rate\n");
 784			return ret;
 785		}
 786		ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 787					 I2S_CGFR_MCKOE, I2S_CGFR_MCKOE);
 788		if (!ret)
 789			i2s->mclk_rate = freq;
 790	}
 791
 792	return ret;
 793}
 794
 795static int stm32_i2s_configure_clock(struct snd_soc_dai *cpu_dai,
 796				     struct snd_pcm_hw_params *params)
 797{
 798	struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 799	unsigned long i2s_clock_rate;
 800	unsigned int nb_bits, frame_len;
 801	unsigned int rate = params_rate(params);
 802	u32 cgfr;
 803	int ret;
 804
 805	if (!i2s->mclk_rate) {
 806		ret = i2s->set_i2s_clk_rate(i2s, rate);
 807		if (ret)
 808			return ret;
 809	}
 810	i2s_clock_rate = clk_get_rate(i2s->i2sclk);
 811
 812	/*
 813	 * mckl = mclk_ratio x ws
 814	 *   i2s mode : mclk_ratio = 256
 815	 *   dsp mode : mclk_ratio = 128
 816	 *
 817	 * mclk on
 818	 *   i2s mode : div = i2s_clk / (mclk_ratio * ws)
 819	 *   dsp mode : div = i2s_clk / (mclk_ratio * ws)
 820	 * mclk off
 821	 *   i2s mode : div = i2s_clk / (nb_bits x ws)
 822	 *   dsp mode : div = i2s_clk / (nb_bits x ws)
 823	 */
 824	if (i2s->mclk_rate) {
 825		ret = stm32_i2s_calc_clk_div(i2s, i2s_clock_rate,
 826					     i2s->mclk_rate);
 827		if (ret)
 828			return ret;
 829	} else {
 830		frame_len = 32;
 831		if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
 832		    SND_SOC_DAIFMT_DSP_A)
 833			frame_len = 16;
 834
 835		/* master clock not enabled */
 836		ret = regmap_read(i2s->regmap, STM32_I2S_CGFR_REG, &cgfr);
 837		if (ret < 0)
 838			return ret;
 839
 840		nb_bits = frame_len * (FIELD_GET(I2S_CGFR_CHLEN, cgfr) + 1);
 841		ret = stm32_i2s_calc_clk_div(i2s, i2s_clock_rate,
 842					     (nb_bits * rate));
 843		if (ret)
 844			return ret;
 845	}
 846
 847	ret = stm32_i2s_set_clk_div(i2s);
 848	if (ret < 0)
 849		return ret;
 850
 851	/* Set bitclock and frameclock to their inactive state */
 852	return regmap_update_bits(i2s->regmap, STM32_I2S_CFG2_REG,
 853				  I2S_CFG2_AFCNTR, I2S_CFG2_AFCNTR);
 854}
 855
 856static int stm32_i2s_configure(struct snd_soc_dai *cpu_dai,
 857			       struct snd_pcm_hw_params *params,
 858			       struct snd_pcm_substream *substream)
 859{
 860	struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 861	int format = params_width(params);
 862	u32 cfgr, cfgr_mask, cfg1;
 863	unsigned int fthlv;
 864	int ret;
 865
 866	switch (format) {
 867	case 16:
 868		cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_16);
 869		cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
 870		break;
 871	case 32:
 872		cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_32) |
 873					   I2S_CGFR_CHLEN;
 874		cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
 875		break;
 876	default:
 877		dev_err(cpu_dai->dev, "Unexpected format %d", format);
 878		return -EINVAL;
 879	}
 880
 881	if (STM32_I2S_IS_SLAVE(i2s)) {
 882		cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_SLAVE);
 883
 884		/* As data length is either 16 or 32 bits, fixch always set */
 885		cfgr |= I2S_CGFR_FIXCH;
 886		cfgr_mask |= I2S_CGFR_FIXCH;
 887	} else {
 888		cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_MASTER);
 889	}
 890	cfgr_mask |= I2S_CGFR_I2SCFG_MASK;
 891
 892	ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
 893				 cfgr_mask, cfgr);
 894	if (ret < 0)
 895		return ret;
 896
 897	fthlv = STM32_I2S_FIFO_SIZE * I2S_FIFO_TH_ONE_QUARTER / 4;
 898	cfg1 = I2S_CFG1_FTHVL_SET(fthlv - 1);
 899
 900	return regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
 901				  I2S_CFG1_FTHVL_MASK, cfg1);
 902}
 903
 904static int stm32_i2s_startup(struct snd_pcm_substream *substream,
 905			     struct snd_soc_dai *cpu_dai)
 906{
 907	struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 908	unsigned long flags;
 909	int ret;
 910
 911	spin_lock_irqsave(&i2s->irq_lock, flags);
 912	i2s->substream = substream;
 913	spin_unlock_irqrestore(&i2s->irq_lock, flags);
 914
 915	if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_DSP_A)
 916		snd_pcm_hw_constraint_single(substream->runtime,
 917					     SNDRV_PCM_HW_PARAM_CHANNELS, 2);
 918
 919	ret = clk_prepare_enable(i2s->i2sclk);
 920	if (ret < 0) {
 921		dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
 922		return ret;
 923	}
 924
 925	return regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
 926				 I2S_IFCR_MASK, I2S_IFCR_MASK);
 927}
 928
 929static int stm32_i2s_hw_params(struct snd_pcm_substream *substream,
 930			       struct snd_pcm_hw_params *params,
 931			       struct snd_soc_dai *cpu_dai)
 932{
 933	struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 934	int ret;
 935
 936	ret = stm32_i2s_configure(cpu_dai, params, substream);
 937	if (ret < 0) {
 938		dev_err(cpu_dai->dev, "Configuration returned error %d\n", ret);
 939		return ret;
 940	}
 941
 942	if (STM32_I2S_IS_MASTER(i2s))
 943		ret = stm32_i2s_configure_clock(cpu_dai, params);
 944
 945	return ret;
 946}
 947
 948static int stm32_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 949			     struct snd_soc_dai *cpu_dai)
 950{
 951	struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
 952	bool playback_flg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 953	u32 cfg1_mask, ier;
 954	int ret;
 955
 956	switch (cmd) {
 957	case SNDRV_PCM_TRIGGER_START:
 958	case SNDRV_PCM_TRIGGER_RESUME:
 959	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 960		/* Enable i2s */
 961		dev_dbg(cpu_dai->dev, "start I2S %s\n",
 962			snd_pcm_direction_name(substream->stream));
 963
 964		cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
 965		regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
 966				   cfg1_mask, cfg1_mask);
 967
 968		ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
 969					 I2S_CR1_SPE, I2S_CR1_SPE);
 970		if (ret < 0) {
 971			dev_err(cpu_dai->dev, "Error %d enabling I2S\n", ret);
 972			return ret;
 973		}
 974
 975		ret = regmap_write_bits(i2s->regmap, STM32_I2S_CR1_REG,
 976					I2S_CR1_CSTART, I2S_CR1_CSTART);
 977		if (ret < 0) {
 978			dev_err(cpu_dai->dev, "Error %d starting I2S\n", ret);
 979			return ret;
 980		}
 981
 982		regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
 983				  I2S_IFCR_MASK, I2S_IFCR_MASK);
 984
 985		spin_lock(&i2s->lock_fd);
 986		i2s->refcount++;
 987		if (playback_flg) {
 988			ier = I2S_IER_UDRIE;
 989		} else {
 990			ier = I2S_IER_OVRIE;
 991
 992			if (STM32_I2S_IS_MASTER(i2s) && i2s->refcount == 1)
 993				/* dummy write to gate bus clocks */
 994				regmap_write(i2s->regmap,
 995					     STM32_I2S_TXDR_REG, 0);
 996		}
 997		spin_unlock(&i2s->lock_fd);
 998
 999		if (STM32_I2S_IS_SLAVE(i2s))
1000			ier |= I2S_IER_TIFREIE;
1001
1002		regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, ier, ier);
1003		break;
1004	case SNDRV_PCM_TRIGGER_STOP:
1005	case SNDRV_PCM_TRIGGER_SUSPEND:
1006	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1007		dev_dbg(cpu_dai->dev, "stop I2S %s\n",
1008			snd_pcm_direction_name(substream->stream));
1009
1010		if (playback_flg)
1011			regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
1012					   I2S_IER_UDRIE,
1013					   (unsigned int)~I2S_IER_UDRIE);
1014		else
1015			regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
1016					   I2S_IER_OVRIE,
1017					   (unsigned int)~I2S_IER_OVRIE);
1018
1019		spin_lock(&i2s->lock_fd);
1020		i2s->refcount--;
1021		if (i2s->refcount) {
1022			spin_unlock(&i2s->lock_fd);
1023			break;
1024		}
1025
1026		ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
1027					 I2S_CR1_SPE, 0);
1028		if (ret < 0) {
1029			dev_err(cpu_dai->dev, "Error %d disabling I2S\n", ret);
1030			spin_unlock(&i2s->lock_fd);
1031			return ret;
1032		}
1033		spin_unlock(&i2s->lock_fd);
1034
1035		cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
1036		regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
1037				   cfg1_mask, 0);
1038		break;
1039	default:
1040		return -EINVAL;
1041	}
1042
1043	return 0;
1044}
1045
1046static void stm32_i2s_shutdown(struct snd_pcm_substream *substream,
1047			       struct snd_soc_dai *cpu_dai)
1048{
1049	struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
1050	unsigned long flags;
1051
1052	clk_disable_unprepare(i2s->i2sclk);
1053
1054	/*
1055	 * Release kernel clock if following conditions are fulfilled
1056	 * - Master clock is not used. Kernel clock won't be released trough sysclk
1057	 * - Put handler is defined. Involve that clock is managed exclusively
1058	 */
1059	if (!i2s->i2smclk && i2s->put_i2s_clk_rate)
1060		i2s->put_i2s_clk_rate(i2s);
1061
1062	spin_lock_irqsave(&i2s->irq_lock, flags);
1063	i2s->substream = NULL;
1064	spin_unlock_irqrestore(&i2s->irq_lock, flags);
1065}
1066
1067static int stm32_i2s_dai_probe(struct snd_soc_dai *cpu_dai)
1068{
1069	struct stm32_i2s_data *i2s = dev_get_drvdata(cpu_dai->dev);
1070	struct snd_dmaengine_dai_dma_data *dma_data_tx = &i2s->dma_data_tx;
1071	struct snd_dmaengine_dai_dma_data *dma_data_rx = &i2s->dma_data_rx;
1072
1073	/* Buswidth will be set by framework */
1074	dma_data_tx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
1075	dma_data_tx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_TXDR_REG;
1076	dma_data_tx->maxburst = 1;
1077	dma_data_rx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
1078	dma_data_rx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_RXDR_REG;
1079	dma_data_rx->maxburst = 1;
1080
1081	snd_soc_dai_init_dma_data(cpu_dai, dma_data_tx, dma_data_rx);
1082
1083	return 0;
1084}
1085
1086static const struct regmap_config stm32_h7_i2s_regmap_conf = {
1087	.reg_bits = 32,
1088	.reg_stride = 4,
1089	.val_bits = 32,
1090	.max_register = STM32_I2S_SIDR_REG,
1091	.readable_reg = stm32_i2s_readable_reg,
1092	.volatile_reg = stm32_i2s_volatile_reg,
1093	.writeable_reg = stm32_i2s_writeable_reg,
1094	.num_reg_defaults_raw = STM32_I2S_SIDR_REG / sizeof(u32) + 1,
1095	.fast_io = true,
1096	.cache_type = REGCACHE_FLAT,
1097};
1098
1099static const struct snd_soc_dai_ops stm32_i2s_pcm_dai_ops = {
1100	.probe		= stm32_i2s_dai_probe,
1101	.set_sysclk	= stm32_i2s_set_sysclk,
1102	.set_fmt	= stm32_i2s_set_dai_fmt,
1103	.startup	= stm32_i2s_startup,
1104	.hw_params	= stm32_i2s_hw_params,
1105	.trigger	= stm32_i2s_trigger,
1106	.shutdown	= stm32_i2s_shutdown,
1107};
1108
1109static const struct snd_pcm_hardware stm32_i2s_pcm_hw = {
1110	.info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
1111	.buffer_bytes_max = 8 * PAGE_SIZE,
1112	.period_bytes_min = 1024,
1113	.period_bytes_max = 4 * PAGE_SIZE,
1114	.periods_min = 2,
1115	.periods_max = 8,
1116};
1117
1118static const struct snd_dmaengine_pcm_config stm32_i2s_pcm_config = {
1119	.pcm_hardware	= &stm32_i2s_pcm_hw,
1120	.prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1121	.prealloc_buffer_size = PAGE_SIZE * 8,
1122};
1123
1124static const struct snd_soc_component_driver stm32_i2s_component = {
1125	.name = "stm32-i2s",
1126	.legacy_dai_naming = 1,
1127};
1128
1129static void stm32_i2s_dai_init(struct snd_soc_pcm_stream *stream,
1130			       char *stream_name)
1131{
1132	stream->stream_name = stream_name;
1133	stream->channels_min = 1;
1134	stream->channels_max = 2;
1135	stream->rates = SNDRV_PCM_RATE_8000_192000;
1136	stream->formats = SNDRV_PCM_FMTBIT_S16_LE |
1137				   SNDRV_PCM_FMTBIT_S32_LE;
1138}
1139
1140static int stm32_i2s_dais_init(struct platform_device *pdev,
1141			       struct stm32_i2s_data *i2s)
1142{
1143	struct snd_soc_dai_driver *dai_ptr;
1144
1145	dai_ptr = devm_kzalloc(&pdev->dev, sizeof(struct snd_soc_dai_driver),
1146			       GFP_KERNEL);
1147	if (!dai_ptr)
1148		return -ENOMEM;
1149
1150	dai_ptr->ops = &stm32_i2s_pcm_dai_ops;
1151	dai_ptr->id = 1;
1152	stm32_i2s_dai_init(&dai_ptr->playback, "playback");
1153	stm32_i2s_dai_init(&dai_ptr->capture, "capture");
1154	i2s->dai_drv = dai_ptr;
1155
1156	return 0;
1157}
1158
1159static const struct stm32_i2s_conf stm32_i2s_conf_h7 = {
1160	.regmap_conf = &stm32_h7_i2s_regmap_conf,
1161	.get_i2s_clk_parent = stm32_i2s_get_parent_clk,
1162};
1163
1164static const struct stm32_i2s_conf stm32_i2s_conf_mp25 = {
1165	.regmap_conf = &stm32_h7_i2s_regmap_conf
1166};
1167
1168static const struct of_device_id stm32_i2s_ids[] = {
1169	{ .compatible = "st,stm32h7-i2s", .data = &stm32_i2s_conf_h7 },
1170	{ .compatible = "st,stm32mp25-i2s", .data = &stm32_i2s_conf_mp25 },
1171	{},
1172};
1173
1174static int stm32_i2s_get_parent_clk(struct stm32_i2s_data *i2s)
1175{
1176	struct device *dev = &i2s->pdev->dev;
1177
1178	i2s->x8kclk = devm_clk_get(dev, "x8k");
1179	if (IS_ERR(i2s->x8kclk))
1180		return dev_err_probe(dev, PTR_ERR(i2s->x8kclk), "Cannot get x8k parent clock\n");
1181
1182	i2s->x11kclk = devm_clk_get(dev, "x11k");
1183	if (IS_ERR(i2s->x11kclk))
1184		return dev_err_probe(dev, PTR_ERR(i2s->x11kclk), "Cannot get x11k parent clock\n");
1185
1186	return 0;
1187}
1188
1189static int stm32_i2s_parse_dt(struct platform_device *pdev,
1190			      struct stm32_i2s_data *i2s)
1191{
1192	struct device_node *np = pdev->dev.of_node;
1193	struct reset_control *rst;
1194	struct resource *res;
1195	int irq, ret;
1196
1197	if (!np)
1198		return -ENODEV;
1199
1200	i2s->conf = device_get_match_data(&pdev->dev);
1201	if (!i2s->conf)
1202		return -EINVAL;
1203
1204	i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1205	if (IS_ERR(i2s->base))
1206		return PTR_ERR(i2s->base);
1207
1208	i2s->phys_addr = res->start;
1209
1210	/* Get clocks */
1211	i2s->pclk = devm_clk_get(&pdev->dev, "pclk");
1212	if (IS_ERR(i2s->pclk))
1213		return dev_err_probe(&pdev->dev, PTR_ERR(i2s->pclk),
1214				     "Could not get pclk\n");
1215
1216	i2s->i2sclk = devm_clk_get(&pdev->dev, "i2sclk");
1217	if (IS_ERR(i2s->i2sclk))
1218		return dev_err_probe(&pdev->dev, PTR_ERR(i2s->i2sclk),
1219				     "Could not get i2sclk\n");
1220
1221	if (i2s->conf->get_i2s_clk_parent) {
1222		i2s->set_i2s_clk_rate = stm32_i2s_set_parent_clock;
1223	} else {
1224		i2s->set_i2s_clk_rate = stm32_i2s_set_parent_rate;
1225		i2s->put_i2s_clk_rate = stm32_i2s_put_parent_rate;
1226	}
1227
1228	if (i2s->conf->get_i2s_clk_parent) {
1229		ret = i2s->conf->get_i2s_clk_parent(i2s);
1230		if (ret)
1231			return ret;
1232	}
1233
1234	/* Register mclk provider if requested */
1235	if (of_property_present(np, "#clock-cells")) {
1236		ret = stm32_i2s_add_mclk_provider(i2s);
1237		if (ret < 0)
1238			return ret;
1239	}
1240
1241	/* Get irqs */
1242	irq = platform_get_irq(pdev, 0);
1243	if (irq < 0)
1244		return irq;
1245
1246	ret = devm_request_irq(&pdev->dev, irq, stm32_i2s_isr, 0,
1247			       dev_name(&pdev->dev), i2s);
1248	if (ret) {
1249		dev_err(&pdev->dev, "irq request returned %d\n", ret);
1250		return ret;
1251	}
1252
1253	/* Reset */
1254	rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
1255	if (IS_ERR(rst))
1256		return dev_err_probe(&pdev->dev, PTR_ERR(rst),
1257				     "Reset controller error\n");
1258
1259	reset_control_assert(rst);
1260	udelay(2);
1261	reset_control_deassert(rst);
1262
1263	return 0;
1264}
1265
1266static void stm32_i2s_remove(struct platform_device *pdev)
1267{
1268	snd_dmaengine_pcm_unregister(&pdev->dev);
1269	snd_soc_unregister_component(&pdev->dev);
1270	pm_runtime_disable(&pdev->dev);
1271}
1272
1273static int stm32_i2s_probe(struct platform_device *pdev)
1274{
1275	struct stm32_i2s_data *i2s;
1276	u32 val;
1277	int ret;
1278
1279	i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
1280	if (!i2s)
1281		return -ENOMEM;
1282
1283	i2s->pdev = pdev;
1284	i2s->ms_flg = I2S_MS_NOT_SET;
1285	spin_lock_init(&i2s->lock_fd);
1286	spin_lock_init(&i2s->irq_lock);
1287	platform_set_drvdata(pdev, i2s);
1288
1289	ret = stm32_i2s_parse_dt(pdev, i2s);
1290	if (ret)
1291		return ret;
1292
1293	ret = stm32_i2s_dais_init(pdev, i2s);
1294	if (ret)
1295		return ret;
1296
1297	i2s->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "pclk",
1298						i2s->base, i2s->conf->regmap_conf);
1299	if (IS_ERR(i2s->regmap))
1300		return dev_err_probe(&pdev->dev, PTR_ERR(i2s->regmap),
1301				     "Regmap init error\n");
1302
1303	ret = snd_dmaengine_pcm_register(&pdev->dev, &stm32_i2s_pcm_config, 0);
1304	if (ret)
1305		return dev_err_probe(&pdev->dev, ret, "PCM DMA register error\n");
1306
1307	ret = snd_soc_register_component(&pdev->dev, &stm32_i2s_component,
1308					 i2s->dai_drv, 1);
1309	if (ret) {
1310		snd_dmaengine_pcm_unregister(&pdev->dev);
1311		return ret;
1312	}
1313
1314	/* Set SPI/I2S in i2s mode */
1315	ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
1316				 I2S_CGFR_I2SMOD, I2S_CGFR_I2SMOD);
1317	if (ret)
1318		goto error;
1319
1320	ret = regmap_read(i2s->regmap, STM32_I2S_IPIDR_REG, &val);
1321	if (ret)
1322		goto error;
1323
1324	if (val == I2S_IPIDR_NUMBER) {
1325		ret = regmap_read(i2s->regmap, STM32_I2S_HWCFGR_REG, &val);
1326		if (ret)
1327			goto error;
1328
1329		if (!FIELD_GET(I2S_HWCFGR_I2S_SUPPORT_MASK, val)) {
1330			dev_err(&pdev->dev,
1331				"Device does not support i2s mode\n");
1332			ret = -EPERM;
1333			goto error;
1334		}
1335
1336		ret = regmap_read(i2s->regmap, STM32_I2S_VERR_REG, &val);
1337		if (ret)
1338			goto error;
1339
1340		dev_dbg(&pdev->dev, "I2S version: %lu.%lu registered\n",
1341			FIELD_GET(I2S_VERR_MAJ_MASK, val),
1342			FIELD_GET(I2S_VERR_MIN_MASK, val));
1343	}
1344
1345	pm_runtime_enable(&pdev->dev);
1346
1347	return ret;
1348
1349error:
1350	stm32_i2s_remove(pdev);
1351
1352	return ret;
1353}
1354
1355MODULE_DEVICE_TABLE(of, stm32_i2s_ids);
1356
1357static int stm32_i2s_suspend(struct device *dev)
1358{
1359	struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
1360
1361	regcache_cache_only(i2s->regmap, true);
1362	regcache_mark_dirty(i2s->regmap);
1363
1364	return 0;
1365}
1366
1367static int stm32_i2s_resume(struct device *dev)
1368{
1369	struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
1370
1371	regcache_cache_only(i2s->regmap, false);
1372	return regcache_sync(i2s->regmap);
1373}
1374
1375static const struct dev_pm_ops stm32_i2s_pm_ops = {
1376	SYSTEM_SLEEP_PM_OPS(stm32_i2s_suspend, stm32_i2s_resume)
1377};
1378
1379static struct platform_driver stm32_i2s_driver = {
1380	.driver = {
1381		.name = "st,stm32-i2s",
1382		.of_match_table = stm32_i2s_ids,
1383		.pm = pm_ptr(&stm32_i2s_pm_ops),
1384	},
1385	.probe = stm32_i2s_probe,
1386	.remove = stm32_i2s_remove,
1387};
1388
1389module_platform_driver(stm32_i2s_driver);
1390
1391MODULE_DESCRIPTION("STM32 Soc i2s Interface");
1392MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>");
1393MODULE_ALIAS("platform:stm32-i2s");
1394MODULE_LICENSE("GPL v2");