ipc4-pcm.c

   1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
   2//
   3// This file is provided under a dual BSD/GPLv2 license.  When using or
   4// redistributing this file, you may do so under either license.
   5//
   6// Copyright(c) 2022 Intel Corporation
   7//
   8
   9#include <sound/pcm_params.h>
  10#include <sound/sof/ipc4/header.h>
  11#include "sof-audio.h"
  12#include "sof-priv.h"
  13#include "ops.h"
  14#include "ipc4-priv.h"
  15#include "ipc4-topology.h"
  16#include "ipc4-fw-reg.h"
  17
  18/**
  19 * struct sof_ipc4_timestamp_info - IPC4 timestamp info
  20 * @host_copier: the host copier of the pcm stream
  21 * @dai_copier: the dai copier of the pcm stream
  22 * @stream_start_offset: reported by fw in memory window (converted to
  23 *                       frames at host_copier sampling rate)
  24 * @stream_end_offset: reported by fw in memory window (converted to
  25 *                     frames at host_copier sampling rate)
  26 * @llp_offset: llp offset in memory window
  27 * @delay: Calculated and stored in pointer callback. The stored value is
  28 *         returned in the delay callback. Expressed in frames at host copier
  29 *         sampling rate.
  30 */
  31struct sof_ipc4_timestamp_info {
  32	struct sof_ipc4_copier *host_copier;
  33	struct sof_ipc4_copier *dai_copier;
  34	u64 stream_start_offset;
  35	u64 stream_end_offset;
  36	u32 llp_offset;
  37
  38	snd_pcm_sframes_t delay;
  39};
  40
  41/**
  42 * struct sof_ipc4_pcm_stream_priv - IPC4 specific private data
  43 * @time_info: pointer to time info struct if it is supported, otherwise NULL
  44 * @chain_dma_allocated: indicates the ChainDMA allocation state
  45 */
  46struct sof_ipc4_pcm_stream_priv {
  47	struct sof_ipc4_timestamp_info *time_info;
  48
  49	bool chain_dma_allocated;
  50};
  51
  52/*
  53 * Modulus to use to compare host and link position counters. The sampling
  54 * rates may be different, so the raw hardware counters will wrap
  55 * around at different times. To calculate differences, use
  56 * DELAY_BOUNDARY as a common modulus. This value must be smaller than
  57 * the wrap-around point of any hardware counter, and larger than any
  58 * valid delay measurement.
  59 */
  60#define DELAY_BOUNDARY		U32_MAX
  61
  62#define DELAY_MAX		(DELAY_BOUNDARY >> 1)
  63
  64static inline struct sof_ipc4_timestamp_info *
  65sof_ipc4_sps_to_time_info(struct snd_sof_pcm_stream *sps)
  66{
  67	struct sof_ipc4_pcm_stream_priv *stream_priv = sps->private;
  68
  69	return stream_priv->time_info;
  70}
  71
  72static
  73char *sof_ipc4_set_multi_pipeline_state_debug(struct snd_sof_dev *sdev, char *buf, size_t size,
  74					      struct ipc4_pipeline_set_state_data *trigger_list)
  75{
  76	int i, offset = 0;
  77
  78	for (i = 0; i < trigger_list->count; i++) {
  79		offset += snprintf(buf + offset, size - offset, " %d",
  80				   trigger_list->pipeline_instance_ids[i]);
  81
  82		if (offset >= size - 1) {
  83			buf[size - 1] = '\0';
  84			break;
  85		}
  86	}
  87	return buf;
  88}
  89
  90static int sof_ipc4_set_multi_pipeline_state(struct snd_sof_dev *sdev, u32 state,
  91					     struct ipc4_pipeline_set_state_data *trigger_list)
  92{
  93	struct sof_ipc4_msg msg = {{ 0 }};
  94	u32 primary, ipc_size;
  95	char debug_buf[32];
  96
  97	/* trigger a single pipeline */
  98	if (trigger_list->count == 1)
  99		return sof_ipc4_set_pipeline_state(sdev, trigger_list->pipeline_instance_ids[0],
 100						   state);
 101
 102	dev_dbg(sdev->dev, "Set pipelines %s to state %d%s",
 103		sof_ipc4_set_multi_pipeline_state_debug(sdev, debug_buf, sizeof(debug_buf),
 104							trigger_list),
 105		state, sof_ipc4_pipeline_state_str(state));
 106
 107	primary = state;
 108	primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_GLB_SET_PIPELINE_STATE);
 109	primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
 110	primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_FW_GEN_MSG);
 111	msg.primary = primary;
 112
 113	/* trigger multiple pipelines with a single IPC */
 114	msg.extension = SOF_IPC4_GLB_PIPE_STATE_EXT_MULTI;
 115
 116	/* ipc_size includes the count and the pipeline IDs for the number of pipelines */
 117	ipc_size = sizeof(u32) * (trigger_list->count + 1);
 118	msg.data_size = ipc_size;
 119	msg.data_ptr = trigger_list;
 120
 121	return sof_ipc_tx_message_no_reply(sdev->ipc, &msg, ipc_size);
 122}
 123
 124int sof_ipc4_set_pipeline_state(struct snd_sof_dev *sdev, u32 instance_id, u32 state)
 125{
 126	struct sof_ipc4_msg msg = {{ 0 }};
 127	u32 primary;
 128
 129	dev_dbg(sdev->dev, "Set pipeline %d to state %d%s", instance_id, state,
 130		sof_ipc4_pipeline_state_str(state));
 131
 132	primary = state;
 133	primary |= SOF_IPC4_GLB_PIPE_STATE_ID(instance_id);
 134	primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_GLB_SET_PIPELINE_STATE);
 135	primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
 136	primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_FW_GEN_MSG);
 137
 138	msg.primary = primary;
 139
 140	return sof_ipc_tx_message_no_reply(sdev->ipc, &msg, 0);
 141}
 142EXPORT_SYMBOL(sof_ipc4_set_pipeline_state);
 143
 144static void sof_ipc4_add_pipeline_by_priority(struct ipc4_pipeline_set_state_data *trigger_list,
 145					      struct snd_sof_widget *pipe_widget,
 146					      s8 *pipe_priority, bool ascend)
 147{
 148	struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
 149	int i, j;
 150
 151	for (i = 0; i < trigger_list->count; i++) {
 152		/* add pipeline from low priority to high */
 153		if (ascend && pipeline->priority < pipe_priority[i])
 154			break;
 155		/* add pipeline from high priority to low */
 156		else if (!ascend && pipeline->priority > pipe_priority[i])
 157			break;
 158	}
 159
 160	for (j = trigger_list->count - 1; j >= i; j--) {
 161		trigger_list->pipeline_instance_ids[j + 1] = trigger_list->pipeline_instance_ids[j];
 162		pipe_priority[j + 1] = pipe_priority[j];
 163	}
 164
 165	trigger_list->pipeline_instance_ids[i] = pipe_widget->instance_id;
 166	trigger_list->count++;
 167	pipe_priority[i] = pipeline->priority;
 168}
 169
 170static void
 171sof_ipc4_add_pipeline_to_trigger_list(struct snd_sof_dev *sdev, int state,
 172				      struct snd_sof_pipeline *spipe,
 173				      struct ipc4_pipeline_set_state_data *trigger_list,
 174				      s8 *pipe_priority)
 175{
 176	struct snd_sof_widget *pipe_widget = spipe->pipe_widget;
 177	struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
 178
 179	if (pipeline->skip_during_fe_trigger && state != SOF_IPC4_PIPE_RESET)
 180		return;
 181
 182	switch (state) {
 183	case SOF_IPC4_PIPE_RUNNING:
 184		/*
 185		 * Trigger pipeline if all PCMs containing it are paused or if it is RUNNING
 186		 * for the first time
 187		 */
 188		if (spipe->started_count == spipe->paused_count)
 189			sof_ipc4_add_pipeline_by_priority(trigger_list, pipe_widget, pipe_priority,
 190							  false);
 191		break;
 192	case SOF_IPC4_PIPE_RESET:
 193		/* RESET if the pipeline is neither running nor paused */
 194		if (!spipe->started_count && !spipe->paused_count)
 195			sof_ipc4_add_pipeline_by_priority(trigger_list, pipe_widget, pipe_priority,
 196							  true);
 197		break;
 198	case SOF_IPC4_PIPE_PAUSED:
 199		/* Pause the pipeline only when its started_count is 1 more than paused_count */
 200		if (spipe->paused_count == (spipe->started_count - 1))
 201			sof_ipc4_add_pipeline_by_priority(trigger_list, pipe_widget, pipe_priority,
 202							  true);
 203		break;
 204	default:
 205		break;
 206	}
 207}
 208
 209static void
 210sof_ipc4_update_pipeline_state(struct snd_sof_dev *sdev, int state, int cmd,
 211			       struct snd_sof_pipeline *spipe,
 212			       struct ipc4_pipeline_set_state_data *trigger_list)
 213{
 214	struct snd_sof_widget *pipe_widget = spipe->pipe_widget;
 215	struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
 216	int i;
 217
 218	if (pipeline->skip_during_fe_trigger && state != SOF_IPC4_PIPE_RESET)
 219		return;
 220
 221	/* set state for pipeline if it was just triggered */
 222	for (i = 0; i < trigger_list->count; i++) {
 223		if (trigger_list->pipeline_instance_ids[i] == pipe_widget->instance_id) {
 224			pipeline->state = state;
 225			break;
 226		}
 227	}
 228
 229	switch (state) {
 230	case SOF_IPC4_PIPE_PAUSED:
 231		switch (cmd) {
 232		case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 233			/*
 234			 * increment paused_count if the PAUSED is the final state during
 235			 * the PAUSE trigger
 236			 */
 237			spipe->paused_count++;
 238			break;
 239		case SNDRV_PCM_TRIGGER_STOP:
 240		case SNDRV_PCM_TRIGGER_SUSPEND:
 241			/*
 242			 * decrement started_count if PAUSED is the final state during the
 243			 * STOP trigger
 244			 */
 245			spipe->started_count--;
 246			break;
 247		default:
 248			break;
 249		}
 250		break;
 251	case SOF_IPC4_PIPE_RUNNING:
 252		switch (cmd) {
 253		case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 254			/* decrement paused_count for RELEASE */
 255			spipe->paused_count--;
 256			break;
 257		case SNDRV_PCM_TRIGGER_START:
 258		case SNDRV_PCM_TRIGGER_RESUME:
 259			/* increment started_count for START/RESUME */
 260			spipe->started_count++;
 261			break;
 262		default:
 263			break;
 264		}
 265		break;
 266	default:
 267		break;
 268	}
 269}
 270
 271/*
 272 * The picture below represents the pipeline state machine wrt PCM actions corresponding to the
 273 * triggers and ioctls
 274 *				+---------------+
 275 *				|               |
 276 *				|    INIT       |
 277 *				|               |
 278 *				+-------+-------+
 279 *					|
 280 *					|
 281 *					| START
 282 *					|
 283 *					|
 284 * +----------------+		   +------v-------+		  +-------------+
 285 * |                |   START     |              |   HW_FREE	  |             |
 286 * |   RUNNING      <-------------+  PAUSED      +--------------> +   RESET     |
 287 * |                |   PAUSE     |              |		  |             |
 288 * +------+---------+   RELEASE   +---------+----+		  +-------------+
 289 *	  |				     ^
 290 *	  |				     |
 291 *	  |				     |
 292 *	  |				     |
 293 *	  |		PAUSE		     |
 294 *	  +---------------------------------+
 295 *			STOP/SUSPEND
 296 *
 297 * Note that during system suspend, the suspend trigger is followed by a hw_free in
 298 * sof_pcm_trigger(). So, the final state during suspend would be RESET.
 299 * Also, since the SOF driver doesn't support full resume, streams would be restarted with the
 300 * prepare ioctl before the START trigger.
 301 */
 302
 303/*
 304 * Chained DMA is a special case where there is no processing on
 305 * DSP. The samples are just moved over by host side DMA to a single
 306 * buffer on DSP and directly from there to link DMA. However, the
 307 * model on SOF driver has two notional pipelines, one at host DAI,
 308 * and another at link DAI. They both shall have the use_chain_dma
 309 * attribute.
 310 */
 311
 312static int sof_ipc4_chain_dma_trigger(struct snd_sof_dev *sdev,
 313				      struct snd_sof_pcm *spcm, int direction,
 314				      struct snd_sof_pcm_stream_pipeline_list *pipeline_list,
 315				      int state, int cmd)
 316{
 317	struct sof_ipc4_fw_data *ipc4_data = sdev->private;
 318	struct sof_ipc4_pcm_stream_priv *stream_priv;
 319	bool allocate, enable, set_fifo_size;
 320	struct sof_ipc4_msg msg = {{ 0 }};
 321	int ret, i;
 322
 323	stream_priv = spcm->stream[direction].private;
 324
 325	switch (state) {
 326	case SOF_IPC4_PIPE_RUNNING: /* Allocate and start chained dma */
 327		allocate = true;
 328		enable = true;
 329		/*
 330		 * SOF assumes creation of a new stream from the presence of fifo_size
 331		 * in the message, so we must leave it out in pause release case.
 332		 */
 333		if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE)
 334			set_fifo_size = false;
 335		else
 336			set_fifo_size = true;
 337		break;
 338	case SOF_IPC4_PIPE_PAUSED: /* Disable chained DMA. */
 339		allocate = true;
 340		enable = false;
 341		set_fifo_size = false;
 342		break;
 343	case SOF_IPC4_PIPE_RESET: /* Disable and free chained DMA. */
 344
 345		/* ChainDMA can only be reset if it has been allocated */
 346		if (!stream_priv->chain_dma_allocated)
 347			return 0;
 348
 349		allocate = false;
 350		enable = false;
 351		set_fifo_size = false;
 352		break;
 353	default:
 354		spcm_err(spcm, direction, "Unexpected pipeline state %d\n", state);
 355		return -EINVAL;
 356	}
 357
 358	msg.primary = SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_GLB_CHAIN_DMA);
 359	msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
 360	msg.primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_FW_GEN_MSG);
 361
 362	/*
 363	 * To set-up the DMA chain, the host DMA ID and SCS setting
 364	 * are retrieved from the host pipeline configuration. Likewise
 365	 * the link DMA ID and fifo_size are retrieved from the link
 366	 * pipeline configuration.
 367	 */
 368	for (i = 0; i < pipeline_list->count; i++) {
 369		struct snd_sof_pipeline *spipe = pipeline_list->pipelines[i];
 370		struct snd_sof_widget *pipe_widget = spipe->pipe_widget;
 371		struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
 372
 373		if (!pipeline->use_chain_dma) {
 374			spcm_err(spcm, direction,
 375				 "All pipelines in chained DMA path should have use_chain_dma attribute set.");
 376			return -EINVAL;
 377		}
 378
 379		msg.primary |= pipeline->msg.primary;
 380
 381		/* Add fifo_size (actually DMA buffer size) field to the message */
 382		if (set_fifo_size)
 383			msg.extension |= pipeline->msg.extension;
 384	}
 385
 386	if (direction == SNDRV_PCM_STREAM_CAPTURE) {
 387		/*
 388		 * For ChainDMA the DMA ids are unique with the following mapping:
 389		 * playback:  0 - (num_playback_streams - 1)
 390		 * capture:   num_playback_streams - (num_playback_streams +
 391		 *				      num_capture_streams - 1)
 392		 *
 393		 * Add the num_playback_streams offset to the DMA ids stored in
 394		 * msg.primary in case capture
 395		 */
 396		msg.primary +=  SOF_IPC4_GLB_CHAIN_DMA_HOST_ID(ipc4_data->num_playback_streams);
 397		msg.primary +=  SOF_IPC4_GLB_CHAIN_DMA_LINK_ID(ipc4_data->num_playback_streams);
 398	}
 399
 400	if (allocate)
 401		msg.primary |= SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_MASK;
 402
 403	if (enable)
 404		msg.primary |= SOF_IPC4_GLB_CHAIN_DMA_ENABLE_MASK;
 405
 406	ret = sof_ipc_tx_message_no_reply(sdev->ipc, &msg, 0);
 407	/* Update the ChainDMA allocation state */
 408	if (!ret)
 409		stream_priv->chain_dma_allocated = allocate;
 410
 411	return ret;
 412}
 413
 414static int sof_ipc4_trigger_pipelines(struct snd_soc_component *component,
 415				      struct snd_pcm_substream *substream, int state, int cmd)
 416{
 417	struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
 418	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
 419	struct snd_sof_pcm_stream_pipeline_list *pipeline_list;
 420	struct sof_ipc4_fw_data *ipc4_data = sdev->private;
 421	struct ipc4_pipeline_set_state_data *trigger_list;
 422	struct snd_sof_widget *pipe_widget;
 423	struct sof_ipc4_pipeline *pipeline;
 424	struct snd_sof_pipeline *spipe;
 425	struct snd_sof_pcm *spcm;
 426	u8 *pipe_priority;
 427	int ret;
 428	int i;
 429
 430	spcm = snd_sof_find_spcm_dai(component, rtd);
 431	if (!spcm)
 432		return -EINVAL;
 433
 434	spcm_dbg(spcm, substream->stream, "cmd: %d, state: %d\n", cmd, state);
 435
 436	pipeline_list = &spcm->stream[substream->stream].pipeline_list;
 437
 438	/* nothing to trigger if the list is empty */
 439	if (!pipeline_list->pipelines || !pipeline_list->count)
 440		return 0;
 441
 442	spipe = pipeline_list->pipelines[0];
 443	pipe_widget = spipe->pipe_widget;
 444	pipeline = pipe_widget->private;
 445
 446	/*
 447	 * If use_chain_dma attribute is set we proceed to chained DMA
 448	 * trigger function that handles the rest for the substream.
 449	 */
 450	if (pipeline->use_chain_dma) {
 451		struct sof_ipc4_timestamp_info *time_info;
 452
 453		time_info = sof_ipc4_sps_to_time_info(&spcm->stream[substream->stream]);
 454
 455		ret = sof_ipc4_chain_dma_trigger(sdev, spcm, substream->stream,
 456						 pipeline_list, state, cmd);
 457		if (ret || !time_info)
 458			return ret;
 459
 460		if (state == SOF_IPC4_PIPE_PAUSED) {
 461			/*
 462			 * Record the DAI position for delay reporting
 463			 * To handle multiple pause/resume/xrun we need to add
 464			 * the positions to simulate how the firmware behaves
 465			 */
 466			u64 pos = snd_sof_pcm_get_dai_frame_counter(sdev, component,
 467								    substream);
 468
 469			time_info->stream_end_offset += pos;
 470		} else if (state == SOF_IPC4_PIPE_RESET) {
 471			/* Reset the end offset as the stream is stopped */
 472			time_info->stream_end_offset = 0;
 473		}
 474
 475		return 0;
 476	}
 477
 478	/* allocate memory for the pipeline data */
 479	trigger_list = kzalloc(struct_size(trigger_list, pipeline_instance_ids,
 480					   pipeline_list->count), GFP_KERNEL);
 481	if (!trigger_list)
 482		return -ENOMEM;
 483
 484	pipe_priority = kzalloc(pipeline_list->count, GFP_KERNEL);
 485	if (!pipe_priority) {
 486		kfree(trigger_list);
 487		return -ENOMEM;
 488	}
 489
 490	mutex_lock(&ipc4_data->pipeline_state_mutex);
 491
 492	/*
 493	 * IPC4 requires pipelines to be triggered in order starting at the sink and
 494	 * walking all the way to the source. So traverse the pipeline_list in the order
 495	 * sink->source when starting PCM's and in the reverse order to pause/stop PCM's.
 496	 * Skip the pipelines that have their skip_during_fe_trigger flag set. If there is a fork
 497	 * in the pipeline, the order of triggering between the left/right paths will be
 498	 * indeterministic. But the sink->source trigger order sink->source would still be
 499	 * guaranteed for each fork independently.
 500	 */
 501	if (state == SOF_IPC4_PIPE_RUNNING || state == SOF_IPC4_PIPE_RESET)
 502		for (i = pipeline_list->count - 1; i >= 0; i--) {
 503			spipe = pipeline_list->pipelines[i];
 504			sof_ipc4_add_pipeline_to_trigger_list(sdev, state, spipe, trigger_list,
 505							      pipe_priority);
 506		}
 507	else
 508		for (i = 0; i < pipeline_list->count; i++) {
 509			spipe = pipeline_list->pipelines[i];
 510			sof_ipc4_add_pipeline_to_trigger_list(sdev, state, spipe, trigger_list,
 511							      pipe_priority);
 512		}
 513
 514	/* return if all pipelines are in the requested state already */
 515	if (!trigger_list->count) {
 516		ret = 0;
 517		goto free;
 518	}
 519
 520	/* no need to pause before reset or before pause release */
 521	if (state == SOF_IPC4_PIPE_RESET || cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE)
 522		goto skip_pause_transition;
 523
 524	/*
 525	 * set paused state for pipelines if the final state is PAUSED or when the pipeline
 526	 * is set to RUNNING for the first time after the PCM is started.
 527	 */
 528	ret = sof_ipc4_set_multi_pipeline_state(sdev, SOF_IPC4_PIPE_PAUSED, trigger_list);
 529	if (ret < 0) {
 530		spcm_err(spcm, substream->stream, "failed to pause all pipelines\n");
 531		goto free;
 532	}
 533
 534	/* update PAUSED state for all pipelines just triggered */
 535	for (i = 0; i < pipeline_list->count ; i++) {
 536		spipe = pipeline_list->pipelines[i];
 537		sof_ipc4_update_pipeline_state(sdev, SOF_IPC4_PIPE_PAUSED, cmd, spipe,
 538					       trigger_list);
 539	}
 540
 541	/* return if this is the final state */
 542	if (state == SOF_IPC4_PIPE_PAUSED) {
 543		struct sof_ipc4_timestamp_info *time_info;
 544
 545		/*
 546		 * Invalidate the stream_start_offset to make sure that it is
 547		 * going to be updated if the stream resumes
 548		 */
 549		time_info = sof_ipc4_sps_to_time_info(&spcm->stream[substream->stream]);
 550		if (time_info)
 551			time_info->stream_start_offset = SOF_IPC4_INVALID_STREAM_POSITION;
 552
 553		goto free;
 554	}
 555skip_pause_transition:
 556	/* else set the RUNNING/RESET state in the DSP */
 557	ret = sof_ipc4_set_multi_pipeline_state(sdev, state, trigger_list);
 558	if (ret < 0) {
 559		spcm_err(spcm, substream->stream,
 560			 "failed to set final state %d for all pipelines\n",
 561			 state);
 562		/*
 563		 * workaround: if the firmware is crashed while setting the
 564		 * pipelines to reset state we must ignore the error code and
 565		 * reset it to 0.
 566		 * Since the firmware is crashed we will not send IPC messages
 567		 * and we are going to see errors printed, but the state of the
 568		 * widgets will be correct for the next boot.
 569		 */
 570		if (sdev->fw_state != SOF_FW_CRASHED || state != SOF_IPC4_PIPE_RESET)
 571			goto free;
 572
 573		ret = 0;
 574	}
 575
 576	/* update RUNNING/RESET state for all pipelines that were just triggered */
 577	for (i = 0; i < pipeline_list->count; i++) {
 578		spipe = pipeline_list->pipelines[i];
 579		sof_ipc4_update_pipeline_state(sdev, state, cmd, spipe, trigger_list);
 580	}
 581
 582free:
 583	mutex_unlock(&ipc4_data->pipeline_state_mutex);
 584	kfree(trigger_list);
 585	kfree(pipe_priority);
 586	return ret;
 587}
 588
 589static int sof_ipc4_pcm_trigger(struct snd_soc_component *component,
 590				struct snd_pcm_substream *substream, int cmd)
 591{
 592	int state;
 593
 594	/* determine the pipeline state */
 595	switch (cmd) {
 596	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 597	case SNDRV_PCM_TRIGGER_RESUME:
 598	case SNDRV_PCM_TRIGGER_START:
 599		state = SOF_IPC4_PIPE_RUNNING;
 600		break;
 601	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 602	case SNDRV_PCM_TRIGGER_SUSPEND:
 603	case SNDRV_PCM_TRIGGER_STOP:
 604		state = SOF_IPC4_PIPE_PAUSED;
 605		break;
 606	default:
 607		dev_err(component->dev, "%s: unhandled trigger cmd %d\n", __func__, cmd);
 608		return -EINVAL;
 609	}
 610
 611	/* set the pipeline state */
 612	return sof_ipc4_trigger_pipelines(component, substream, state, cmd);
 613}
 614
 615static int sof_ipc4_pcm_hw_free(struct snd_soc_component *component,
 616				struct snd_pcm_substream *substream)
 617{
 618	/* command is not relevant with RESET, so just pass 0 */
 619	return sof_ipc4_trigger_pipelines(component, substream, SOF_IPC4_PIPE_RESET, 0);
 620}
 621
 622static int ipc4_ssp_dai_config_pcm_params_match(struct snd_sof_dev *sdev,
 623						const char *link_name,
 624						struct snd_pcm_hw_params *params)
 625{
 626	struct snd_sof_dai_link *slink;
 627	struct snd_sof_dai *dai;
 628	bool dai_link_found = false;
 629	int current_config = -1;
 630	bool partial_match;
 631	int i;
 632
 633	list_for_each_entry(slink, &sdev->dai_link_list, list) {
 634		if (!strcmp(slink->link->name, link_name)) {
 635			dai_link_found = true;
 636			break;
 637		}
 638	}
 639
 640	if (!dai_link_found)
 641		return 0;
 642
 643	/*
 644	 * Find the first best matching hardware config:
 645	 * rate + format + channels are matching
 646	 * rate + channel are matching
 647	 *
 648	 * The copier cannot do rate and/or channel conversion.
 649	 */
 650	for (i = 0; i < slink->num_hw_configs; i++) {
 651		struct snd_soc_tplg_hw_config *hw_config = &slink->hw_configs[i];
 652
 653		if (params_rate(params) == le32_to_cpu(hw_config->fsync_rate) &&
 654		    params_width(params) == le32_to_cpu(hw_config->tdm_slot_width) &&
 655		    params_channels(params) <= le32_to_cpu(hw_config->tdm_slots)) {
 656			current_config = le32_to_cpu(hw_config->id);
 657			partial_match = false;
 658			/* best match found */
 659			break;
 660		} else if (current_config < 0 &&
 661			   params_rate(params) == le32_to_cpu(hw_config->fsync_rate) &&
 662			   params_channels(params) <= le32_to_cpu(hw_config->tdm_slots)) {
 663			current_config = le32_to_cpu(hw_config->id);
 664			partial_match = true;
 665			/* keep looking for better match */
 666		}
 667	}
 668
 669	if (current_config < 0) {
 670		dev_err(sdev->dev,
 671			"%s: No suitable hw_config found for %s (num_hw_configs: %d)\n",
 672			__func__, slink->link->name, slink->num_hw_configs);
 673		return -EINVAL;
 674	}
 675
 676	dev_dbg(sdev->dev,
 677		"hw_config for %s: %d (num_hw_configs: %d) with %s match\n",
 678		slink->link->name, current_config, slink->num_hw_configs,
 679		partial_match ? "partial" : "full");
 680	list_for_each_entry(dai, &sdev->dai_list, list)
 681		if (!strcmp(slink->link->name, dai->name))
 682			dai->current_config = current_config;
 683
 684	return 0;
 685}
 686
 687/*
 688 * Fixup DAI link parameters for sampling rate based on
 689 * DAI copier configuration.
 690 */
 691static int sof_ipc4_pcm_dai_link_fixup_rate(struct snd_sof_dev *sdev,
 692					    struct snd_pcm_hw_params *params,
 693					    struct sof_ipc4_copier *ipc4_copier)
 694{
 695	struct sof_ipc4_pin_format *pin_fmts = ipc4_copier->available_fmt.input_pin_fmts;
 696	struct snd_interval *rate = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
 697	int num_input_formats = ipc4_copier->available_fmt.num_input_formats;
 698	unsigned int fe_rate = params_rate(params);
 699	bool fe_be_rate_match = false;
 700	bool single_be_rate = true;
 701	unsigned int be_rate;
 702	int i;
 703
 704	if (WARN_ON_ONCE(!num_input_formats))
 705		return -EINVAL;
 706
 707	/*
 708	 * Copier does not change sampling rate, so we
 709	 * need to only consider the input pin information.
 710	 */
 711	be_rate = pin_fmts[0].audio_fmt.sampling_frequency;
 712	for (i = 0; i < num_input_formats; i++) {
 713		unsigned int val = pin_fmts[i].audio_fmt.sampling_frequency;
 714
 715		if (val != be_rate)
 716			single_be_rate = false;
 717
 718		if (val == fe_rate) {
 719			fe_be_rate_match = true;
 720			break;
 721		}
 722	}
 723
 724	/*
 725	 * If rate is different than FE rate, topology must
 726	 * contain an SRC. But we do require topology to
 727	 * define a single rate in the DAI copier config in
 728	 * this case (FE rate may be variable).
 729	 */
 730	if (!fe_be_rate_match) {
 731		if (!single_be_rate) {
 732			dev_err(sdev->dev, "Unable to select sampling rate for DAI link\n");
 733			return -EINVAL;
 734		}
 735
 736		rate->min = be_rate;
 737		rate->max = rate->min;
 738	}
 739
 740	return 0;
 741}
 742
 743static int sof_ipc4_pcm_dai_link_fixup_channels(struct snd_sof_dev *sdev,
 744						struct snd_pcm_hw_params *params,
 745						struct sof_ipc4_copier *ipc4_copier)
 746{
 747	struct sof_ipc4_pin_format *pin_fmts = ipc4_copier->available_fmt.input_pin_fmts;
 748	struct snd_interval *channels = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
 749	int num_input_formats = ipc4_copier->available_fmt.num_input_formats;
 750	unsigned int fe_channels = params_channels(params);
 751	bool fe_be_match = false;
 752	bool single_be_channels = true;
 753	unsigned int be_channels, val;
 754	int i;
 755
 756	if (WARN_ON_ONCE(!num_input_formats))
 757		return -EINVAL;
 758
 759	/*
 760	 * Copier does not change channels, so we
 761	 * need to only consider the input pin information.
 762	 */
 763	be_channels = SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(pin_fmts[0].audio_fmt.fmt_cfg);
 764	for (i = 0; i < num_input_formats; i++) {
 765		val = SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(pin_fmts[i].audio_fmt.fmt_cfg);
 766
 767		if (val != be_channels)
 768			single_be_channels = false;
 769
 770		if (val == fe_channels) {
 771			fe_be_match = true;
 772			break;
 773		}
 774	}
 775
 776	/*
 777	 * If channels is different than FE channels, topology must contain a
 778	 * module which can change the number of channels. But we do require
 779	 * topology to define a single channels in the DAI copier config in
 780	 * this case (FE channels may be variable).
 781	 */
 782	if (!fe_be_match) {
 783		if (!single_be_channels) {
 784			dev_err(sdev->dev, "Unable to select channels for DAI link\n");
 785			return -EINVAL;
 786		}
 787
 788		channels->min = be_channels;
 789		channels->max = be_channels;
 790	}
 791
 792	return 0;
 793}
 794
 795static int sof_ipc4_pcm_dai_link_fixup(struct snd_soc_pcm_runtime *rtd,
 796				       struct snd_pcm_hw_params *params)
 797{
 798	struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, SOF_AUDIO_PCM_DRV_NAME);
 799	struct snd_sof_dai *dai = snd_sof_find_dai(component, rtd->dai_link->name);
 800	struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
 801	struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
 802	struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
 803	struct sof_ipc4_audio_format *ipc4_fmt;
 804	struct sof_ipc4_copier *ipc4_copier;
 805	bool single_bitdepth = false;
 806	u32 valid_bits = 0;
 807	int dir, ret;
 808
 809	if (!dai) {
 810		dev_err(component->dev, "%s: No DAI found with name %s\n", __func__,
 811			rtd->dai_link->name);
 812		return -EINVAL;
 813	}
 814
 815	ipc4_copier = dai->private;
 816	if (!ipc4_copier) {
 817		dev_err(component->dev, "%s: No private data found for DAI %s\n",
 818			__func__, rtd->dai_link->name);
 819		return -EINVAL;
 820	}
 821
 822	for_each_pcm_streams(dir) {
 823		struct snd_soc_dapm_widget *w = snd_soc_dai_get_widget(cpu_dai, dir);
 824
 825		if (w) {
 826			struct sof_ipc4_available_audio_format *available_fmt =
 827				&ipc4_copier->available_fmt;
 828			struct snd_sof_widget *swidget = w->dobj.private;
 829			struct snd_sof_widget *pipe_widget = swidget->spipe->pipe_widget;
 830			struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
 831
 832			/* Chain DMA does not use copiers, so no fixup needed */
 833			if (pipeline->use_chain_dma)
 834				return 0;
 835
 836			if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
 837				if (sof_ipc4_copier_is_single_bitdepth(sdev,
 838					available_fmt->output_pin_fmts,
 839					available_fmt->num_output_formats)) {
 840					ipc4_fmt = &available_fmt->output_pin_fmts->audio_fmt;
 841					single_bitdepth = true;
 842				}
 843			} else {
 844				if (sof_ipc4_copier_is_single_bitdepth(sdev,
 845					available_fmt->input_pin_fmts,
 846					available_fmt->num_input_formats)) {
 847					ipc4_fmt = &available_fmt->input_pin_fmts->audio_fmt;
 848					single_bitdepth = true;
 849				}
 850			}
 851		}
 852	}
 853
 854	ret = sof_ipc4_pcm_dai_link_fixup_rate(sdev, params, ipc4_copier);
 855	if (ret)
 856		return ret;
 857
 858	ret = sof_ipc4_pcm_dai_link_fixup_channels(sdev, params, ipc4_copier);
 859	if (ret)
 860		return ret;
 861
 862	if (single_bitdepth) {
 863		snd_mask_none(fmt);
 864		valid_bits = SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH(ipc4_fmt->fmt_cfg);
 865		dev_dbg(component->dev, "Set %s to %d bit format\n", dai->name, valid_bits);
 866	}
 867
 868	/* Set format if it is specified */
 869	switch (valid_bits) {
 870	case 16:
 871		snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S16_LE);
 872		break;
 873	case 24:
 874		snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S24_LE);
 875		break;
 876	case 32:
 877		snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S32_LE);
 878		break;
 879	default:
 880		break;
 881	}
 882
 883	if (ipc4_copier->dai_type == SOF_DAI_INTEL_SSP)
 884		return ipc4_ssp_dai_config_pcm_params_match(sdev,
 885							    (char *)rtd->dai_link->name,
 886							    params);
 887
 888	return 0;
 889}
 890
 891static void sof_ipc4_pcm_free(struct snd_sof_dev *sdev, struct snd_sof_pcm *spcm)
 892{
 893	struct snd_sof_pcm_stream_pipeline_list *pipeline_list;
 894	struct sof_ipc4_pcm_stream_priv *stream_priv;
 895	int stream;
 896
 897	for_each_pcm_streams(stream) {
 898		pipeline_list = &spcm->stream[stream].pipeline_list;
 899		kfree(pipeline_list->pipelines);
 900		pipeline_list->pipelines = NULL;
 901
 902		stream_priv = spcm->stream[stream].private;
 903		kfree(stream_priv->time_info);
 904		kfree(spcm->stream[stream].private);
 905		spcm->stream[stream].private = NULL;
 906	}
 907}
 908
 909static int sof_ipc4_pcm_setup(struct snd_sof_dev *sdev, struct snd_sof_pcm *spcm)
 910{
 911	struct snd_sof_pcm_stream_pipeline_list *pipeline_list;
 912	struct sof_ipc4_fw_data *ipc4_data = sdev->private;
 913	struct sof_ipc4_pcm_stream_priv *stream_priv;
 914	struct sof_ipc4_timestamp_info *time_info;
 915	bool support_info = true;
 916	u32 abi_version;
 917	u32 abi_offset;
 918	int stream;
 919
 920	abi_offset = offsetof(struct sof_ipc4_fw_registers, abi_ver);
 921	sof_mailbox_read(sdev, sdev->fw_info_box.offset + abi_offset, &abi_version,
 922			 sizeof(abi_version));
 923
 924	if (abi_version < SOF_IPC4_FW_REGS_ABI_VER)
 925		support_info = false;
 926
 927	/* For delay reporting the get_host_byte_counter callback is needed */
 928	if (!sof_ops(sdev) || !sof_ops(sdev)->get_host_byte_counter)
 929		support_info = false;
 930
 931	for_each_pcm_streams(stream) {
 932		pipeline_list = &spcm->stream[stream].pipeline_list;
 933
 934		/* allocate memory for max number of pipeline IDs */
 935		pipeline_list->pipelines = kcalloc(ipc4_data->max_num_pipelines,
 936						   sizeof(*pipeline_list->pipelines),
 937						   GFP_KERNEL);
 938		if (!pipeline_list->pipelines) {
 939			sof_ipc4_pcm_free(sdev, spcm);
 940			return -ENOMEM;
 941		}
 942
 943		stream_priv = kzalloc(sizeof(*stream_priv), GFP_KERNEL);
 944		if (!stream_priv) {
 945			sof_ipc4_pcm_free(sdev, spcm);
 946			return -ENOMEM;
 947		}
 948
 949		spcm->stream[stream].private = stream_priv;
 950
 951		/* Delay reporting is only supported on playback */
 952		if (!support_info || stream == SNDRV_PCM_STREAM_CAPTURE)
 953			continue;
 954
 955		time_info = kzalloc(sizeof(*time_info), GFP_KERNEL);
 956		if (!time_info) {
 957			sof_ipc4_pcm_free(sdev, spcm);
 958			return -ENOMEM;
 959		}
 960
 961		stream_priv->time_info = time_info;
 962	}
 963
 964	return 0;
 965}
 966
 967static void sof_ipc4_build_time_info(struct snd_sof_dev *sdev, struct snd_sof_pcm_stream *sps)
 968{
 969	struct sof_ipc4_copier *host_copier = NULL;
 970	struct sof_ipc4_copier *dai_copier = NULL;
 971	struct sof_ipc4_llp_reading_slot llp_slot;
 972	struct sof_ipc4_timestamp_info *time_info;
 973	struct snd_soc_dapm_widget *widget;
 974	struct snd_sof_dai *dai;
 975	int i;
 976
 977	/* find host & dai to locate info in memory window */
 978	for_each_dapm_widgets(sps->list, i, widget) {
 979		struct snd_sof_widget *swidget = widget->dobj.private;
 980
 981		if (!swidget)
 982			continue;
 983
 984		if (WIDGET_IS_AIF(swidget->widget->id)) {
 985			host_copier = swidget->private;
 986		} else if (WIDGET_IS_DAI(swidget->widget->id)) {
 987			dai = swidget->private;
 988			dai_copier = dai->private;
 989		}
 990	}
 991
 992	/* both host and dai copier must be valid for time_info */
 993	if (!host_copier || !dai_copier) {
 994		dev_err(sdev->dev, "host or dai copier are not found\n");
 995		return;
 996	}
 997
 998	time_info = sof_ipc4_sps_to_time_info(sps);
 999	time_info->host_copier = host_copier;
1000	time_info->dai_copier = dai_copier;
1001	time_info->llp_offset = offsetof(struct sof_ipc4_fw_registers,
1002					 llp_gpdma_reading_slots) + sdev->fw_info_box.offset;
1003
1004	/* find llp slot used by current dai */
1005	for (i = 0; i < SOF_IPC4_MAX_LLP_GPDMA_READING_SLOTS; i++) {
1006		sof_mailbox_read(sdev, time_info->llp_offset, &llp_slot, sizeof(llp_slot));
1007		if (llp_slot.node_id == dai_copier->data.gtw_cfg.node_id)
1008			break;
1009
1010		time_info->llp_offset += sizeof(llp_slot);
1011	}
1012
1013	if (i < SOF_IPC4_MAX_LLP_GPDMA_READING_SLOTS)
1014		return;
1015
1016	/* if no llp gpdma slot is used, check aggregated sdw slot */
1017	time_info->llp_offset = offsetof(struct sof_ipc4_fw_registers,
1018					 llp_sndw_reading_slots) + sdev->fw_info_box.offset;
1019	for (i = 0; i < SOF_IPC4_MAX_LLP_SNDW_READING_SLOTS; i++) {
1020		sof_mailbox_read(sdev, time_info->llp_offset, &llp_slot, sizeof(llp_slot));
1021		if (llp_slot.node_id == dai_copier->data.gtw_cfg.node_id)
1022			break;
1023
1024		time_info->llp_offset += sizeof(llp_slot);
1025	}
1026
1027	if (i < SOF_IPC4_MAX_LLP_SNDW_READING_SLOTS)
1028		return;
1029
1030	/* check EVAD slot */
1031	time_info->llp_offset = offsetof(struct sof_ipc4_fw_registers,
1032					 llp_evad_reading_slot) + sdev->fw_info_box.offset;
1033	sof_mailbox_read(sdev, time_info->llp_offset, &llp_slot, sizeof(llp_slot));
1034	if (llp_slot.node_id != dai_copier->data.gtw_cfg.node_id)
1035		time_info->llp_offset = 0;
1036}
1037
1038static int sof_ipc4_pcm_hw_params(struct snd_soc_component *component,
1039				  struct snd_pcm_substream *substream,
1040				  struct snd_pcm_hw_params *params,
1041				  struct snd_sof_platform_stream_params *platform_params)
1042{
1043	struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
1044	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
1045	struct sof_ipc4_timestamp_info *time_info;
1046	struct snd_sof_pcm *spcm;
1047
1048	spcm = snd_sof_find_spcm_dai(component, rtd);
1049	if (!spcm)
1050		return -EINVAL;
1051
1052	time_info = sof_ipc4_sps_to_time_info(&spcm->stream[substream->stream]);
1053	/* delay calculation is not supported by current fw_reg ABI */
1054	if (!time_info)
1055		return 0;
1056
1057	time_info->stream_start_offset = SOF_IPC4_INVALID_STREAM_POSITION;
1058	time_info->llp_offset = 0;
1059
1060	sof_ipc4_build_time_info(sdev, &spcm->stream[substream->stream]);
1061
1062	return 0;
1063}
1064
1065static u64 sof_ipc4_frames_dai_to_host(struct sof_ipc4_timestamp_info *time_info, u64 value)
1066{
1067	u64 dai_rate, host_rate;
1068
1069	if (!time_info->dai_copier || !time_info->host_copier)
1070		return value;
1071
1072	/*
1073	 * copiers do not change sampling rate, so we can use the
1074	 * out_format independently of stream direction
1075	 */
1076	dai_rate = time_info->dai_copier->data.out_format.sampling_frequency;
1077	host_rate = time_info->host_copier->data.out_format.sampling_frequency;
1078
1079	if (!dai_rate || !host_rate || dai_rate == host_rate)
1080		return value;
1081
1082	/* take care not to overflow u64, rates can be up to 768000 */
1083	if (value > U32_MAX) {
1084		value = div64_u64(value, dai_rate);
1085		value *= host_rate;
1086	} else {
1087		value *= host_rate;
1088		value = div64_u64(value, dai_rate);
1089	}
1090
1091	return value;
1092}
1093
1094static int sof_ipc4_get_stream_start_offset(struct snd_sof_dev *sdev,
1095					    struct snd_pcm_substream *substream,
1096					    struct snd_sof_pcm_stream *sps,
1097					    struct sof_ipc4_timestamp_info *time_info)
1098{
1099	struct sof_ipc4_copier *host_copier = time_info->host_copier;
1100	struct sof_ipc4_copier *dai_copier = time_info->dai_copier;
1101	struct sof_ipc4_pipeline_registers ppl_reg;
1102	u32 dai_sample_size;
1103	u32 ch, node_index;
1104	u32 offset;
1105
1106	if (!host_copier || !dai_copier)
1107		return -EINVAL;
1108
1109	if (host_copier->data.gtw_cfg.node_id == SOF_IPC4_INVALID_NODE_ID) {
1110		return -EINVAL;
1111	} else if (host_copier->data.gtw_cfg.node_id == SOF_IPC4_CHAIN_DMA_NODE_ID) {
1112		/*
1113		 * While the firmware does not support time_info reporting for
1114		 * streams using ChainDMA, it is granted that ChainDMA can only
1115		 * be used on Host+Link pairs where the link position is
1116		 * accessible from the host side.
1117		 *
1118		 * Enable delay calculation in case of ChainDMA via host
1119		 * accessible registers.
1120		 *
1121		 * The ChainDMA prefills the link DMA with a preamble
1122		 * of zero samples. Set the stream start offset based
1123		 * on size of the preamble (driver provided fifo size
1124		 * multiplied by 2.5). We add 1ms of margin as the FW
1125		 * will align the buffer size to DMA hardware
1126		 * alignment that is not known to host.
1127		 */
1128		int pre_ms = SOF_IPC4_CHAIN_DMA_BUF_SIZE_MS * 5 / 2 + 1;
1129
1130		time_info->stream_start_offset = pre_ms * substream->runtime->rate / MSEC_PER_SEC;
1131		goto out;
1132	}
1133
1134	node_index = SOF_IPC4_NODE_INDEX(host_copier->data.gtw_cfg.node_id);
1135	offset = offsetof(struct sof_ipc4_fw_registers, pipeline_regs) + node_index * sizeof(ppl_reg);
1136	sof_mailbox_read(sdev, sdev->fw_info_box.offset + offset, &ppl_reg, sizeof(ppl_reg));
1137	if (ppl_reg.stream_start_offset == SOF_IPC4_INVALID_STREAM_POSITION)
1138		return -EINVAL;
1139
1140	ch = dai_copier->data.out_format.fmt_cfg;
1141	ch = SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(ch);
1142	dai_sample_size = (dai_copier->data.out_format.bit_depth >> 3) * ch;
1143
1144	/* convert offsets to frame count */
1145	time_info->stream_start_offset = ppl_reg.stream_start_offset;
1146	do_div(time_info->stream_start_offset, dai_sample_size);
1147	time_info->stream_end_offset = ppl_reg.stream_end_offset;
1148	do_div(time_info->stream_end_offset, dai_sample_size);
1149
1150	/* convert to host frame time */
1151	time_info->stream_start_offset =
1152		sof_ipc4_frames_dai_to_host(time_info, time_info->stream_start_offset);
1153	time_info->stream_end_offset =
1154		sof_ipc4_frames_dai_to_host(time_info, time_info->stream_end_offset);
1155
1156out:
1157	/* Initialize the delay value to 0 (no delay) */
1158	time_info->delay = 0;
1159
1160	return 0;
1161}
1162
1163static int sof_ipc4_pcm_pointer(struct snd_soc_component *component,
1164				struct snd_pcm_substream *substream,
1165				snd_pcm_uframes_t *pointer)
1166{
1167	struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
1168	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
1169	struct sof_ipc4_timestamp_info *time_info;
1170	struct sof_ipc4_llp_reading_slot llp;
1171	snd_pcm_uframes_t head_cnt, tail_cnt;
1172	struct snd_sof_pcm_stream *sps;
1173	u64 dai_cnt, host_cnt, host_ptr;
1174	struct snd_sof_pcm *spcm;
1175	int ret;
1176
1177	spcm = snd_sof_find_spcm_dai(component, rtd);
1178	if (!spcm)
1179		return -EOPNOTSUPP;
1180
1181	sps = &spcm->stream[substream->stream];
1182	time_info = sof_ipc4_sps_to_time_info(sps);
1183	if (!time_info)
1184		return -EOPNOTSUPP;
1185
1186	/*
1187	 * stream_start_offset is updated to memory window by FW based on
1188	 * pipeline statistics and it may be invalid if host query happens before
1189	 * the statistics is complete. And it will not change after the first initiailization.
1190	 */
1191	if (time_info->stream_start_offset == SOF_IPC4_INVALID_STREAM_POSITION) {
1192		ret = sof_ipc4_get_stream_start_offset(sdev, substream, sps, time_info);
1193		if (ret < 0)
1194			return -EOPNOTSUPP;
1195	}
1196
1197	/* For delay calculation we need the host counter */
1198	host_cnt = snd_sof_pcm_get_host_byte_counter(sdev, component, substream);
1199
1200	/* Store the original value to host_ptr */
1201	host_ptr = host_cnt;
1202
1203	/* convert the host_cnt to frames */
1204	host_cnt = div64_u64(host_cnt, frames_to_bytes(substream->runtime, 1));
1205
1206	/*
1207	 * If the LLP counter is not reported by firmware in the SRAM window
1208	 * then read the dai (link) counter via host accessible means if
1209	 * available.
1210	 */
1211	if (!time_info->llp_offset) {
1212		dai_cnt = snd_sof_pcm_get_dai_frame_counter(sdev, component, substream);
1213		if (!dai_cnt)
1214			return -EOPNOTSUPP;
1215	} else {
1216		sof_mailbox_read(sdev, time_info->llp_offset, &llp, sizeof(llp));
1217		dai_cnt = ((u64)llp.reading.llp_u << 32) | llp.reading.llp_l;
1218	}
1219
1220	dai_cnt = sof_ipc4_frames_dai_to_host(time_info, dai_cnt);
1221	dai_cnt += time_info->stream_end_offset;
1222
1223	/* In two cases dai dma counter is not accurate
1224	 * (1) dai pipeline is started before host pipeline
1225	 * (2) multiple streams mixed into one. Each stream has the same dai dma
1226	 *     counter
1227	 *
1228	 * Firmware calculates correct stream_start_offset for all cases
1229	 * including above two.
1230	 * Driver subtracts stream_start_offset from dai dma counter to get
1231	 * accurate one
1232	 */
1233
1234	/*
1235	 * On stream start the dai counter might not yet have reached the
1236	 * stream_start_offset value which means that no frames have left the
1237	 * DSP yet from the audio stream (on playback, capture streams have
1238	 * offset of 0 as we start capturing right away).
1239	 * In this case we need to adjust the distance between the counters by
1240	 * increasing the host counter by (offset - dai_counter).
1241	 * Otherwise the dai_counter needs to be adjusted to reflect the number
1242	 * of valid frames passed on the DAI side.
1243	 *
1244	 * The delay is the difference between the counters on the two
1245	 * sides of the DSP.
1246	 */
1247	if (dai_cnt < time_info->stream_start_offset) {
1248		host_cnt += time_info->stream_start_offset - dai_cnt;
1249		dai_cnt = 0;
1250	} else {
1251		dai_cnt -= time_info->stream_start_offset;
1252	}
1253
1254	/* Convert to a common base before comparisons */
1255	dai_cnt &= DELAY_BOUNDARY;
1256	host_cnt &= DELAY_BOUNDARY;
1257
1258	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1259		head_cnt = host_cnt;
1260		tail_cnt = dai_cnt;
1261	} else {
1262		head_cnt = dai_cnt;
1263		tail_cnt = host_cnt;
1264	}
1265
1266	if (unlikely(head_cnt < tail_cnt))
1267		time_info->delay = DELAY_BOUNDARY - tail_cnt + head_cnt;
1268	else
1269		time_info->delay = head_cnt - tail_cnt;
1270
1271	if (time_info->delay > DELAY_MAX) {
1272		spcm_dbg_ratelimited(spcm, substream->stream,
1273				     "inaccurate delay, host %llu dai_cnt %llu",
1274				     host_cnt, dai_cnt);
1275		time_info->delay = 0;
1276	}
1277
1278	/*
1279	 * Convert the host byte counter to PCM pointer which wraps in buffer
1280	 * and it is in frames
1281	 */
1282	div64_u64_rem(host_ptr, snd_pcm_lib_buffer_bytes(substream), &host_ptr);
1283	*pointer = bytes_to_frames(substream->runtime, host_ptr);
1284
1285	return 0;
1286}
1287
1288static snd_pcm_sframes_t sof_ipc4_pcm_delay(struct snd_soc_component *component,
1289					    struct snd_pcm_substream *substream)
1290{
1291	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
1292	struct sof_ipc4_timestamp_info *time_info;
1293	struct snd_sof_pcm *spcm;
1294
1295	spcm = snd_sof_find_spcm_dai(component, rtd);
1296	if (!spcm)
1297		return 0;
1298
1299	time_info = sof_ipc4_sps_to_time_info(&spcm->stream[substream->stream]);
1300	/*
1301	 * Report the stored delay value calculated in the pointer callback.
1302	 * In the unlikely event that the calculation was skipped/aborted, the
1303	 * default 0 delay returned.
1304	 */
1305	if (time_info)
1306		return time_info->delay;
1307
1308	/* No delay information available, report 0 as delay */
1309	return 0;
1310
1311}
1312
1313const struct sof_ipc_pcm_ops ipc4_pcm_ops = {
1314	.hw_params = sof_ipc4_pcm_hw_params,
1315	.trigger = sof_ipc4_pcm_trigger,
1316	.hw_free = sof_ipc4_pcm_hw_free,
1317	.dai_link_fixup = sof_ipc4_pcm_dai_link_fixup,
1318	.pcm_setup = sof_ipc4_pcm_setup,
1319	.pcm_free = sof_ipc4_pcm_free,
1320	.pointer = sof_ipc4_pcm_pointer,
1321	.delay = sof_ipc4_pcm_delay,
1322	.ipc_first_on_start = true,
1323	.platform_stop_during_hw_free = true,
1324};