shim.h

  1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
  2/*
  3 * This file is provided under a dual BSD/GPLv2 license.  When using or
  4 * redistributing this file, you may do so under either license.
  5 *
  6 * Copyright(c) 2017 Intel Corporation
  7 *
  8 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
  9 */
 10
 11#ifndef __SOF_INTEL_SHIM_H
 12#define __SOF_INTEL_SHIM_H
 13
 14enum sof_intel_hw_ip_version {
 15	SOF_INTEL_TANGIER,
 16	SOF_INTEL_BAYTRAIL,
 17	SOF_INTEL_BROADWELL,
 18	SOF_INTEL_CAVS_1_5,	/* SkyLake, KabyLake, AmberLake */
 19	SOF_INTEL_CAVS_1_5_PLUS,/* ApolloLake, GeminiLake */
 20	SOF_INTEL_CAVS_1_8,	/* CannonLake, CometLake, CoffeeLake */
 21	SOF_INTEL_CAVS_2_0,	/* IceLake, JasperLake */
 22	SOF_INTEL_CAVS_2_5,	/* TigerLake, AlderLake */
 23	SOF_INTEL_ACE_1_0,	/* MeteorLake */
 24	SOF_INTEL_ACE_2_0,	/* LunarLake */
 25	SOF_INTEL_ACE_3_0,	/* PantherLake */
 26	SOF_INTEL_ACE_4_0,	/* NovaLake */
 27};
 28
 29/*
 30 * SHIM registers for BYT, BSW, CHT, BDW
 31 */
 32
 33#define SHIM_CSR		(SHIM_OFFSET + 0x00)
 34#define SHIM_PISR		(SHIM_OFFSET + 0x08)
 35#define SHIM_PIMR		(SHIM_OFFSET + 0x10)
 36#define SHIM_ISRX		(SHIM_OFFSET + 0x18)
 37#define SHIM_ISRD		(SHIM_OFFSET + 0x20)
 38#define SHIM_IMRX		(SHIM_OFFSET + 0x28)
 39#define SHIM_IMRD		(SHIM_OFFSET + 0x30)
 40#define SHIM_IPCX		(SHIM_OFFSET + 0x38)
 41#define SHIM_IPCD		(SHIM_OFFSET + 0x40)
 42#define SHIM_ISRSC		(SHIM_OFFSET + 0x48)
 43#define SHIM_ISRLPESC		(SHIM_OFFSET + 0x50)
 44#define SHIM_IMRSC		(SHIM_OFFSET + 0x58)
 45#define SHIM_IMRLPESC		(SHIM_OFFSET + 0x60)
 46#define SHIM_IPCSC		(SHIM_OFFSET + 0x68)
 47#define SHIM_IPCLPESC		(SHIM_OFFSET + 0x70)
 48#define SHIM_CLKCTL		(SHIM_OFFSET + 0x78)
 49#define SHIM_CSR2		(SHIM_OFFSET + 0x80)
 50#define SHIM_LTRC		(SHIM_OFFSET + 0xE0)
 51#define SHIM_HMDC		(SHIM_OFFSET + 0xE8)
 52
 53#define SHIM_PWMCTRL		0x1000
 54
 55/*
 56 * SST SHIM register bits for BYT, BSW, CHT, BDW
 57 * Register bit naming and functionaility can differ between devices.
 58 */
 59
 60/* CSR / CS */
 61#define SHIM_CSR_RST		BIT(1)
 62#define SHIM_CSR_SBCS0		BIT(2)
 63#define SHIM_CSR_SBCS1		BIT(3)
 64#define SHIM_CSR_DCS(x)		((x) << 4)
 65#define SHIM_CSR_DCS_MASK	(0x7 << 4)
 66#define SHIM_CSR_STALL		BIT(10)
 67#define SHIM_CSR_S0IOCS		BIT(21)
 68#define SHIM_CSR_S1IOCS		BIT(23)
 69#define SHIM_CSR_LPCS		BIT(31)
 70#define SHIM_CSR_24MHZ_LPCS \
 71	(SHIM_CSR_SBCS0 | SHIM_CSR_SBCS1 | SHIM_CSR_LPCS)
 72#define SHIM_CSR_24MHZ_NO_LPCS	(SHIM_CSR_SBCS0 | SHIM_CSR_SBCS1)
 73#define SHIM_BYT_CSR_RST	BIT(0)
 74#define SHIM_BYT_CSR_VECTOR_SEL	BIT(1)
 75#define SHIM_BYT_CSR_STALL	BIT(2)
 76#define SHIM_BYT_CSR_PWAITMODE	BIT(3)
 77
 78/*  ISRX / ISC */
 79#define SHIM_ISRX_BUSY		BIT(1)
 80#define SHIM_ISRX_DONE		BIT(0)
 81#define SHIM_BYT_ISRX_REQUEST	BIT(1)
 82
 83/*  ISRD / ISD */
 84#define SHIM_ISRD_BUSY		BIT(1)
 85#define SHIM_ISRD_DONE		BIT(0)
 86
 87/* IMRX / IMC */
 88#define SHIM_IMRX_BUSY		BIT(1)
 89#define SHIM_IMRX_DONE		BIT(0)
 90#define SHIM_BYT_IMRX_REQUEST	BIT(1)
 91
 92/* IMRD / IMD */
 93#define SHIM_IMRD_DONE		BIT(0)
 94#define SHIM_IMRD_BUSY		BIT(1)
 95#define SHIM_IMRD_SSP0		BIT(16)
 96#define SHIM_IMRD_DMAC0		BIT(21)
 97#define SHIM_IMRD_DMAC1		BIT(22)
 98#define SHIM_IMRD_DMAC		(SHIM_IMRD_DMAC0 | SHIM_IMRD_DMAC1)
 99
100/*  IPCX / IPCC */
101#define	SHIM_IPCX_DONE		BIT(30)
102#define	SHIM_IPCX_BUSY		BIT(31)
103#define SHIM_BYT_IPCX_DONE	BIT_ULL(62)
104#define SHIM_BYT_IPCX_BUSY	BIT_ULL(63)
105
106/*  IPCD */
107#define	SHIM_IPCD_DONE		BIT(30)
108#define	SHIM_IPCD_BUSY		BIT(31)
109#define SHIM_BYT_IPCD_DONE	BIT_ULL(62)
110#define SHIM_BYT_IPCD_BUSY	BIT_ULL(63)
111
112/* CLKCTL */
113#define SHIM_CLKCTL_SMOS(x)	((x) << 24)
114#define SHIM_CLKCTL_MASK	(3 << 24)
115#define SHIM_CLKCTL_DCPLCG	BIT(18)
116#define SHIM_CLKCTL_SCOE1	BIT(17)
117#define SHIM_CLKCTL_SCOE0	BIT(16)
118
119/* CSR2 / CS2 */
120#define SHIM_CSR2_SDFD_SSP0	BIT(1)
121#define SHIM_CSR2_SDFD_SSP1	BIT(2)
122
123/* LTRC */
124#define SHIM_LTRC_VAL(x)	((x) << 0)
125
126/* HMDC */
127#define SHIM_HMDC_HDDA0(x)	((x) << 0)
128#define SHIM_HMDC_HDDA1(x)	((x) << 7)
129#define SHIM_HMDC_HDDA_E0_CH0	1
130#define SHIM_HMDC_HDDA_E0_CH1	2
131#define SHIM_HMDC_HDDA_E0_CH2	4
132#define SHIM_HMDC_HDDA_E0_CH3	8
133#define SHIM_HMDC_HDDA_E1_CH0	SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH0)
134#define SHIM_HMDC_HDDA_E1_CH1	SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH1)
135#define SHIM_HMDC_HDDA_E1_CH2	SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH2)
136#define SHIM_HMDC_HDDA_E1_CH3	SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH3)
137#define SHIM_HMDC_HDDA_E0_ALLCH	\
138	(SHIM_HMDC_HDDA_E0_CH0 | SHIM_HMDC_HDDA_E0_CH1 | \
139	 SHIM_HMDC_HDDA_E0_CH2 | SHIM_HMDC_HDDA_E0_CH3)
140#define SHIM_HMDC_HDDA_E1_ALLCH	\
141	(SHIM_HMDC_HDDA_E1_CH0 | SHIM_HMDC_HDDA_E1_CH1 | \
142	 SHIM_HMDC_HDDA_E1_CH2 | SHIM_HMDC_HDDA_E1_CH3)
143
144/* Audio DSP PCI registers */
145#define PCI_VDRTCTL0		0xa0
146#define PCI_VDRTCTL1		0xa4
147#define PCI_VDRTCTL2		0xa8
148#define PCI_VDRTCTL3		0xaC
149
150/* VDRTCTL0 */
151#define PCI_VDRTCL0_D3PGD		BIT(0)
152#define PCI_VDRTCL0_D3SRAMPGD		BIT(1)
153#define PCI_VDRTCL0_DSRAMPGE_SHIFT	12
154#define PCI_VDRTCL0_DSRAMPGE_MASK	GENMASK(PCI_VDRTCL0_DSRAMPGE_SHIFT + 19,\
155						PCI_VDRTCL0_DSRAMPGE_SHIFT)
156#define PCI_VDRTCL0_ISRAMPGE_SHIFT	2
157#define PCI_VDRTCL0_ISRAMPGE_MASK	GENMASK(PCI_VDRTCL0_ISRAMPGE_SHIFT + 9,\
158						PCI_VDRTCL0_ISRAMPGE_SHIFT)
159
160/* VDRTCTL2 */
161#define PCI_VDRTCL2_DCLCGE		BIT(1)
162#define PCI_VDRTCL2_DTCGE		BIT(10)
163#define PCI_VDRTCL2_APLLSE_MASK		BIT(31)
164
165/* PMCS */
166#define PCI_PMCS		0x84
167#define PCI_PMCS_PS_MASK	0x3
168
169/* Intel quirks */
170#define SOF_INTEL_PROCEN_FMT_QUIRK BIT(0)
171
172/* DSP hardware descriptor */
173struct sof_intel_dsp_desc {
174	int cores_num;
175	int host_managed_cores_mask;
176	int init_core_mask; /* cores available after fw boot */
177	int ipc_req;
178	int ipc_req_mask;
179	int ipc_ack;
180	int ipc_ack_mask;
181	int ipc_ctl;
182	int rom_status_reg;
183	int rom_init_timeout;
184	int ssp_count;			/* ssp count of the platform */
185	int ssp_base_offset;		/* base address of the SSPs */
186	u32 sdw_shim_base;
187	u32 sdw_alh_base;
188	u32 d0i3_offset;
189	u32 quirks;
190	const char *platform;
191	enum sof_intel_hw_ip_version hw_ip_version;
192	int (*read_sdw_lcount)(struct snd_sof_dev *sdev);
193	void (*enable_sdw_irq)(struct snd_sof_dev *sdev, bool enable);
194	bool (*check_sdw_irq)(struct snd_sof_dev *sdev);
195	bool (*check_sdw_wakeen_irq)(struct snd_sof_dev *sdev);
196	void (*sdw_process_wakeen)(struct snd_sof_dev *sdev);
197	bool (*check_ipc_irq)(struct snd_sof_dev *sdev);
198	bool (*check_mic_privacy_irq)(struct snd_sof_dev *sdev, bool alt, int elid);
199	void (*process_mic_privacy)(struct snd_sof_dev *sdev, bool alt, int elid);
200	int (*power_down_dsp)(struct snd_sof_dev *sdev);
201	int (*disable_interrupts)(struct snd_sof_dev *sdev);
202	int (*cl_init)(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot);
203};
204
205extern const struct snd_sof_dsp_ops sof_tng_ops;
206
207extern const struct sof_intel_dsp_desc tng_chip_info;
208
209struct sof_intel_stream {
210	size_t posn_offset;
211};
212
213static inline const struct sof_intel_dsp_desc *get_chip_info(struct snd_sof_pdata *pdata)
214{
215	const struct sof_dev_desc *desc = pdata->desc;
216
217	return desc->chip_info;
218}
219
220#endif