ptl.c

  1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
  2//
  3// Copyright(c) 2025 Intel Corporation
  4
  5/*
  6 * Hardware interface for audio DSP on PantherLake.
  7 */
  8
  9#include <sound/hda_register.h>
 10#include <sound/hda-mlink.h>
 11#include <sound/sof/ipc4/header.h>
 12#include "../ipc4-priv.h"
 13#include "../ops.h"
 14#include "hda.h"
 15#include "hda-ipc.h"
 16#include "../sof-audio.h"
 17#include "mtl.h"
 18#include "lnl.h"
 19#include "ptl.h"
 20
 21static bool sof_ptl_check_mic_privacy_irq(struct snd_sof_dev *sdev, bool alt,
 22					  int elid)
 23{
 24	if (!alt || elid != AZX_REG_ML_LEPTR_ID_SDW)
 25		return false;
 26
 27	return hdac_bus_eml_is_mic_privacy_changed(sof_to_bus(sdev), alt, elid);
 28}
 29
 30static void sof_ptl_mic_privacy_work(struct work_struct *work)
 31{
 32	struct sof_intel_hda_dev *hdev = container_of(work,
 33						      struct sof_intel_hda_dev,
 34						      mic_privacy.work);
 35	struct hdac_bus *bus = &hdev->hbus.core;
 36	struct snd_sof_dev *sdev = dev_get_drvdata(bus->dev);
 37	bool state;
 38
 39	/*
 40	 * The microphone privacy state is only available via Soundwire shim
 41	 * in PTL
 42	 * The work is only scheduled on change.
 43	 */
 44	state = hdac_bus_eml_get_mic_privacy_state(bus, 1,
 45						   AZX_REG_ML_LEPTR_ID_SDW);
 46	sof_ipc4_mic_privacy_state_change(sdev, state);
 47}
 48
 49static void sof_ptl_process_mic_privacy(struct snd_sof_dev *sdev, bool alt,
 50					int elid)
 51{
 52	struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
 53
 54	if (!alt || elid != AZX_REG_ML_LEPTR_ID_SDW)
 55		return;
 56
 57	/*
 58	 * Schedule the work to read the microphone privacy state and send IPC
 59	 * message about the new state to the firmware
 60	 */
 61	schedule_work(&hdev->mic_privacy.work);
 62}
 63
 64static void sof_ptl_set_mic_privacy(struct snd_sof_dev *sdev,
 65				    struct sof_ipc4_intel_mic_privacy_cap *caps)
 66{
 67	struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
 68	u32 micpvcp;
 69
 70	if (!caps || !caps->capabilities_length)
 71		return;
 72
 73	micpvcp = caps->capabilities[0];
 74
 75	/* No need to set the mic privacy if it is not enabled or forced */
 76	if (!(micpvcp & PTL_MICPVCP_DDZE_ENABLED) ||
 77	    micpvcp & PTL_MICPVCP_DDZE_FORCED)
 78		return;
 79
 80	hdac_bus_eml_set_mic_privacy_mask(sof_to_bus(sdev), true,
 81					  AZX_REG_ML_LEPTR_ID_SDW,
 82					  PTL_MICPVCP_GET_SDW_MASK(micpvcp));
 83
 84	INIT_WORK(&hdev->mic_privacy.work, sof_ptl_mic_privacy_work);
 85	hdev->mic_privacy.active = true;
 86}
 87
 88int sof_ptl_set_ops(struct snd_sof_dev *sdev, struct snd_sof_dsp_ops *dsp_ops)
 89{
 90	struct sof_ipc4_fw_data *ipc4_data;
 91	int ret;
 92
 93	ret = sof_lnl_set_ops(sdev, dsp_ops);
 94	if (ret)
 95		return ret;
 96
 97	ipc4_data = sdev->private;
 98	ipc4_data->intel_configure_mic_privacy = sof_ptl_set_mic_privacy;
 99
100	return 0;
101};
102EXPORT_SYMBOL_NS(sof_ptl_set_ops, "SND_SOC_SOF_INTEL_PTL");
103
104const struct sof_intel_dsp_desc ptl_chip_info = {
105	.cores_num = 5,
106	.init_core_mask = BIT(0),
107	.host_managed_cores_mask = BIT(0),
108	.ipc_req = MTL_DSP_REG_HFIPCXIDR,
109	.ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY,
110	.ipc_ack = MTL_DSP_REG_HFIPCXIDA,
111	.ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE,
112	.ipc_ctl = MTL_DSP_REG_HFIPCXCTL,
113	.rom_status_reg = LNL_DSP_REG_HFDSC,
114	.rom_init_timeout = 300,
115	.ssp_count = MTL_SSP_COUNT,
116	.d0i3_offset = MTL_HDA_VS_D0I3C,
117	.read_sdw_lcount =  hda_sdw_check_lcount_ext,
118	.check_sdw_irq = lnl_dsp_check_sdw_irq,
119	.check_sdw_wakeen_irq = lnl_sdw_check_wakeen_irq,
120	.sdw_process_wakeen = hda_sdw_process_wakeen_common,
121	.check_ipc_irq = mtl_dsp_check_ipc_irq,
122	.check_mic_privacy_irq = sof_ptl_check_mic_privacy_irq,
123	.process_mic_privacy = sof_ptl_process_mic_privacy,
124	.cl_init = mtl_dsp_cl_init,
125	.power_down_dsp = mtl_power_down_dsp,
126	.disable_interrupts = lnl_dsp_disable_interrupts,
127	.hw_ip_version = SOF_INTEL_ACE_3_0,
128	.platform = "ptl",
129};
130
131const struct sof_intel_dsp_desc wcl_chip_info = {
132	.cores_num = 3,
133	.init_core_mask = BIT(0),
134	.host_managed_cores_mask = BIT(0),
135	.ipc_req = MTL_DSP_REG_HFIPCXIDR,
136	.ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY,
137	.ipc_ack = MTL_DSP_REG_HFIPCXIDA,
138	.ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE,
139	.ipc_ctl = MTL_DSP_REG_HFIPCXCTL,
140	.rom_status_reg = LNL_DSP_REG_HFDSC,
141	.rom_init_timeout = 300,
142	.ssp_count = MTL_SSP_COUNT,
143	.d0i3_offset = MTL_HDA_VS_D0I3C,
144	.read_sdw_lcount =  hda_sdw_check_lcount_ext,
145	.check_sdw_irq = lnl_dsp_check_sdw_irq,
146	.check_sdw_wakeen_irq = lnl_sdw_check_wakeen_irq,
147	.sdw_process_wakeen = hda_sdw_process_wakeen_common,
148	.check_ipc_irq = mtl_dsp_check_ipc_irq,
149	.cl_init = mtl_dsp_cl_init,
150	.power_down_dsp = mtl_power_down_dsp,
151	.disable_interrupts = lnl_dsp_disable_interrupts,
152	.hw_ip_version = SOF_INTEL_ACE_3_0,
153	.platform = "wcl",
154};
155
156MODULE_IMPORT_NS("SND_SOC_SOF_INTEL_MTL");
157MODULE_IMPORT_NS("SND_SOC_SOF_INTEL_LNL");
158MODULE_IMPORT_NS("SND_SOC_SOF_HDA_MLINK");