nvl.c

 1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
 2//
 3// Copyright(c) 2025 Intel Corporation
 4
 5/*
 6 * Hardware interface for audio DSP on NovaLake.
 7 */
 8
 9#include <sound/hda_register.h>
10#include <sound/hda-mlink.h>
11#include <sound/sof/ipc4/header.h>
12#include "../ipc4-priv.h"
13#include "../ops.h"
14#include "hda.h"
15#include "hda-ipc.h"
16#include "../sof-audio.h"
17#include "mtl.h"
18#include "lnl.h"
19#include "ptl.h"
20#include "nvl.h"
21
22int sof_nvl_set_ops(struct snd_sof_dev *sdev, struct snd_sof_dsp_ops *dsp_ops)
23{
24	/* Use PTL ops for NVL */
25	return sof_ptl_set_ops(sdev, dsp_ops);
26};
27EXPORT_SYMBOL_NS(sof_nvl_set_ops, "SND_SOC_SOF_INTEL_NVL");
28
29const struct sof_intel_dsp_desc nvl_s_chip_info = {
30	.cores_num = 2,
31	.init_core_mask = BIT(0),
32	.host_managed_cores_mask = BIT(0),
33	.ipc_req = MTL_DSP_REG_HFIPCXIDR,
34	.ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY,
35	.ipc_ack = MTL_DSP_REG_HFIPCXIDA,
36	.ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE,
37	.ipc_ctl = MTL_DSP_REG_HFIPCXCTL,
38	.rom_status_reg = LNL_DSP_REG_HFDSC,
39	.rom_init_timeout = 300,
40	.ssp_count = MTL_SSP_COUNT,
41	.d0i3_offset = MTL_HDA_VS_D0I3C,
42	.read_sdw_lcount =  hda_sdw_check_lcount_ext,
43	.check_sdw_irq = lnl_dsp_check_sdw_irq,
44	.check_sdw_wakeen_irq = lnl_sdw_check_wakeen_irq,
45	.sdw_process_wakeen = hda_sdw_process_wakeen_common,
46	.check_ipc_irq = mtl_dsp_check_ipc_irq,
47	.cl_init = mtl_dsp_cl_init,
48	.power_down_dsp = mtl_power_down_dsp,
49	.disable_interrupts = lnl_dsp_disable_interrupts,
50	.hw_ip_version = SOF_INTEL_ACE_4_0,
51};
52
53MODULE_IMPORT_NS("SND_SOC_SOF_INTEL_MTL");
54MODULE_IMPORT_NS("SND_SOC_SOF_INTEL_LNL");
55MODULE_IMPORT_NS("SND_SOC_SOF_INTEL_PTL");