mtl.h

  1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
  2/*
  3 * This file is provided under a dual BSD/GPLv2 license.  When using or
  4 * redistributing this file, you may do so under either license.
  5 *
  6 * Copyright(c) 2020-2022 Intel Corporation
  7 */
  8
  9/* DSP Registers */
 10#define MTL_HFDSSCS			0x1000
 11#define MTL_HFDSSCS_SPA_MASK		BIT(16)
 12#define MTL_HFDSSCS_CPA_MASK		BIT(24)
 13#define MTL_HFSNDWIE			0x114C
 14#define MTL_HFPWRCTL			0x1D18
 15#define PTL_HFPWRCTL2			0x1D20
 16#define MTL_HfPWRCTL_WPIOXPG(x)		BIT((x) + 8)
 17#define MTL_HFPWRCTL_WPDSPHPXPG		BIT(0)
 18#define MTL_HFPWRSTS			0x1D1C
 19#define PTL_HFPWRSTS2			0x1D24
 20#define MTL_HFPWRSTS_DSPHPXPGS_MASK	BIT(0)
 21#define MTL_HFINTIPPTR			0x1108
 22#define MTL_IRQ_INTEN_L_HOST_IPC_MASK	BIT(0)
 23#define MTL_IRQ_INTEN_L_SOUNDWIRE_MASK	BIT(6)
 24#define MTL_HFINTIPPTR_PTR_MASK		GENMASK(20, 0)
 25
 26#define MTL_HDA_VS_D0I3C		0x1D4A
 27
 28#define MTL_DSP2CXCAP_PRIMARY_CORE	0x178D00
 29#define MTL_DSP2CXCTL_PRIMARY_CORE	0x178D04
 30#define MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK BIT(0)
 31#define MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK BIT(8)
 32#define MTL_DSP2CXCTL_PRIMARY_CORE_OSEL GENMASK(25, 24)
 33#define MTL_DSP2CXCTL_PRIMARY_CORE_OSEL_SHIFT 24
 34
 35/* IPC Registers */
 36#define MTL_DSP_REG_HFIPCXTDR		0x73200
 37#define MTL_DSP_REG_HFIPCXTDR_BUSY	BIT(31)
 38#define MTL_DSP_REG_HFIPCXTDR_MSG_MASK GENMASK(30, 0)
 39#define MTL_DSP_REG_HFIPCXTDA		0x73204
 40#define MTL_DSP_REG_HFIPCXTDA_BUSY	BIT(31)
 41#define MTL_DSP_REG_HFIPCXIDR		0x73210
 42#define MTL_DSP_REG_HFIPCXIDR_BUSY	BIT(31)
 43#define MTL_DSP_REG_HFIPCXIDR_MSG_MASK GENMASK(30, 0)
 44#define MTL_DSP_REG_HFIPCXIDA		0x73214
 45#define MTL_DSP_REG_HFIPCXIDA_DONE	BIT(31)
 46#define MTL_DSP_REG_HFIPCXIDA_MSG_MASK GENMASK(30, 0)
 47#define MTL_DSP_REG_HFIPCXCTL		0x73228
 48#define MTL_DSP_REG_HFIPCXCTL_BUSY	BIT(0)
 49#define MTL_DSP_REG_HFIPCXCTL_DONE	BIT(1)
 50#define MTL_DSP_REG_HFIPCXTDDY		0x73300
 51#define MTL_DSP_REG_HFIPCXIDDY		0x73380
 52#define MTL_DSP_REG_HfHIPCIE		0x1140
 53#define MTL_DSP_REG_HfHIPCIE_IE_MASK	BIT(0)
 54#define MTL_DSP_REG_HfSNDWIE		0x114C
 55#define MTL_DSP_REG_HfSNDWIE_IE_MASK	GENMASK(3, 0)
 56
 57#define MTL_DSP_IRQSTS			0x20
 58#define MTL_DSP_IRQSTS_IPC		BIT(0)
 59#define MTL_DSP_IRQSTS_SDW		BIT(6)
 60
 61#define MTL_DSP_REG_POLL_INTERVAL_US	10	/* 10 us */
 62
 63/* Memory windows */
 64#define MTL_SRAM_WINDOW_OFFSET(x)	(0x180000 + 0x8000 * (x))
 65
 66#define MTL_DSP_MBOX_UPLINK_OFFSET	(MTL_SRAM_WINDOW_OFFSET(0) + 0x1000)
 67#define MTL_DSP_MBOX_UPLINK_SIZE	0x1000
 68#define MTL_DSP_MBOX_DOWNLINK_OFFSET	MTL_SRAM_WINDOW_OFFSET(1)
 69#define MTL_DSP_MBOX_DOWNLINK_SIZE	0x1000
 70
 71/* FW registers */
 72#define MTL_DSP_ROM_STS			MTL_SRAM_WINDOW_OFFSET(0) /* ROM status */
 73#define MTL_DSP_ROM_ERROR		(MTL_SRAM_WINDOW_OFFSET(0) + 0x4) /* ROM error code */
 74
 75#define MTL_DSP_REG_HFFLGPXQWY		0x163200 /* DSP core0 status */
 76#define MTL_DSP_REG_HFFLGPXQWY_ERROR	0x163204 /* DSP core0 error */
 77
 78/* FSR status codes */
 79#define FSR_STATE_ROM_RESET_VECTOR_DONE		0x8
 80#define FSR_STATE_ROM_PURGE_BOOT		0x9
 81#define FSR_STATE_ROM_RESTORE_BOOT		0xA
 82#define FSR_STATE_ROM_FW_ENTRY_POINT		0xB
 83#define FSR_STATE_ROM_VALIDATE_PUB_KEY		0xC
 84#define FSR_STATE_ROM_POWER_DOWN_HPSRAM		0xD
 85#define FSR_STATE_ROM_POWER_DOWN_ULPSRAM	0xE
 86#define FSR_STATE_ROM_POWER_UP_ULPSRAM_STACK	0xF
 87#define FSR_STATE_ROM_POWER_UP_HPSRAM_DMA	0x10
 88#define FSR_STATE_ROM_BEFORE_EP_POINTER_READ	0x11
 89#define FSR_STATE_ROM_VALIDATE_MANIFEST		0x12
 90#define FSR_STATE_ROM_VALIDATE_FW_MODULE	0x13
 91#define FSR_STATE_ROM_PROTECT_IMR_REGION	0x14
 92#define FSR_STATE_ROM_PUSH_MODEL_ROUTINE	0x15
 93#define FSR_STATE_ROM_PULL_MODEL_ROUTINE	0x16
 94#define FSR_STATE_ROM_VALIDATE_PKG_DIR		0x17
 95#define FSR_STATE_ROM_VALIDATE_CPD		0x18
 96#define FSR_STATE_ROM_VALIDATE_CSS_MAN_HEADER	0x19
 97#define FSR_STATE_ROM_VALIDATE_BLOB_SVN		0x1A
 98#define FSR_STATE_ROM_VERIFY_IFWI_PARTITION	0x1B
 99#define FSR_STATE_ROM_REMOVE_ACCESS_CONTROL	0x1C
100#define FSR_STATE_ROM_AUTH_BYPASS		0x1D
101#define FSR_STATE_ROM_AUTH_ENABLED		0x1E
102#define FSR_STATE_ROM_INIT_DMA			0x1F
103#define FSR_STATE_ROM_PURGE_FW_ENTRY		0x20
104#define FSR_STATE_ROM_PURGE_FW_END		0x21
105#define FSR_STATE_ROM_CLEAN_UP_BSS_DONE		0x22
106#define FSR_STATE_ROM_IMR_RESTORE_ENTRY		0x23
107#define FSR_STATE_ROM_IMR_RESTORE_END		0x24
108#define FSR_STATE_ROM_FW_MANIFEST_IN_DMA_BUFF	0x25
109#define FSR_STATE_ROM_LOAD_CSE_MAN_TO_IMR	0x26
110#define FSR_STATE_ROM_LOAD_FW_MAN_TO_IMR	0x27
111#define FSR_STATE_ROM_LOAD_FW_CODE_TO_IMR	0x28
112#define FSR_STATE_ROM_FW_LOADING_DONE		0x29
113#define FSR_STATE_ROM_FW_CODE_LOADED		0x2A
114#define FSR_STATE_ROM_VERIFY_IMAGE_TYPE		0x2B
115#define FSR_STATE_ROM_AUTH_API_INIT		0x2C
116#define FSR_STATE_ROM_AUTH_API_PROC		0x2D
117#define FSR_STATE_ROM_AUTH_API_FIRST_BUSY	0x2E
118#define FSR_STATE_ROM_AUTH_API_FIRST_RESULT	0x2F
119#define FSR_STATE_ROM_AUTH_API_CLEANUP		0x30
120
121#define MTL_DSP_REG_HfIMRIS1		0x162088
122#define MTL_DSP_REG_HfIMRIS1_IU_MASK	BIT(0)
123
124bool mtl_dsp_check_ipc_irq(struct snd_sof_dev *sdev);
125
126void mtl_enable_ipc_interrupts(struct snd_sof_dev *sdev);
127void mtl_disable_ipc_interrupts(struct snd_sof_dev *sdev);
128
129int mtl_enable_interrupts(struct snd_sof_dev *sdev, bool enable);
130
131int mtl_power_down_dsp(struct snd_sof_dev *sdev);
132int mtl_dsp_cl_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot);
133
134int sof_mtl_set_ops(struct snd_sof_dev *sdev, struct snd_sof_dsp_ops *dsp_ops);